meson-mx-efuse.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
  4. *
  5. * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/nvmem-provider.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/sizes.h>
  19. #include <linux/slab.h>
  20. #define MESON_MX_EFUSE_CNTL1 0x04
  21. #define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
  22. #define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
  23. #define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
  24. #define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
  25. #define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
  26. #define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
  27. #define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
  28. #define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
  29. #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
  30. #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
  31. #define MESON_MX_EFUSE_CNTL2 0x08
  32. #define MESON_MX_EFUSE_CNTL4 0x10
  33. #define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
  34. struct meson_mx_efuse_platform_data {
  35. const char *name;
  36. unsigned int word_size;
  37. };
  38. struct meson_mx_efuse {
  39. void __iomem *base;
  40. struct clk *core_clk;
  41. struct nvmem_device *nvmem;
  42. struct nvmem_config config;
  43. };
  44. static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
  45. u32 mask, u32 set)
  46. {
  47. u32 data;
  48. data = readl(efuse->base + reg);
  49. data &= ~mask;
  50. data |= (set & mask);
  51. writel(data, efuse->base + reg);
  52. }
  53. static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
  54. {
  55. int err;
  56. err = clk_prepare_enable(efuse->core_clk);
  57. if (err)
  58. return err;
  59. /* power up the efuse */
  60. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  61. MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);
  62. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
  63. MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);
  64. return 0;
  65. }
  66. static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
  67. {
  68. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  69. MESON_MX_EFUSE_CNTL1_PD_ENABLE,
  70. MESON_MX_EFUSE_CNTL1_PD_ENABLE);
  71. clk_disable_unprepare(efuse->core_clk);
  72. }
  73. static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
  74. unsigned int addr, u32 *value)
  75. {
  76. int err;
  77. u32 regval;
  78. /* write the address to read */
  79. regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
  80. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  81. MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);
  82. /* inform the hardware that we changed the address */
  83. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  84. MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
  85. MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
  86. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  87. MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);
  88. /* start the read process */
  89. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  90. MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
  91. MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
  92. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  93. MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);
  94. /*
  95. * perform a dummy read to ensure that the HW has the RD_BUSY bit set
  96. * when polling for the status below.
  97. */
  98. readl(efuse->base + MESON_MX_EFUSE_CNTL1);
  99. err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
  100. regval,
  101. (!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
  102. 1, 1000);
  103. if (err) {
  104. dev_err(efuse->config.dev,
  105. "Timeout while reading efuse address %u\n", addr);
  106. return err;
  107. }
  108. *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
  109. return 0;
  110. }
  111. static int meson_mx_efuse_read(void *context, unsigned int offset,
  112. void *buf, size_t bytes)
  113. {
  114. struct meson_mx_efuse *efuse = context;
  115. u32 tmp;
  116. int err, i, addr;
  117. err = meson_mx_efuse_hw_enable(efuse);
  118. if (err)
  119. return err;
  120. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  121. MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
  122. MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);
  123. for (i = 0; i < bytes; i += efuse->config.word_size) {
  124. addr = (offset + i) / efuse->config.word_size;
  125. err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
  126. if (err)
  127. break;
  128. memcpy(buf + i, &tmp,
  129. min_t(size_t, bytes - i, efuse->config.word_size));
  130. }
  131. meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
  132. MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);
  133. meson_mx_efuse_hw_disable(efuse);
  134. return err;
  135. }
  136. static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
  137. .name = "meson6-efuse",
  138. .word_size = 1,
  139. };
  140. static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
  141. .name = "meson8-efuse",
  142. .word_size = 4,
  143. };
  144. static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
  145. .name = "meson8b-efuse",
  146. .word_size = 4,
  147. };
  148. static const struct of_device_id meson_mx_efuse_match[] = {
  149. { .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
  150. { .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
  151. { .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
  152. { /* sentinel */ },
  153. };
  154. MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);
  155. static int meson_mx_efuse_probe(struct platform_device *pdev)
  156. {
  157. const struct meson_mx_efuse_platform_data *drvdata;
  158. struct meson_mx_efuse *efuse;
  159. struct resource *res;
  160. drvdata = of_device_get_match_data(&pdev->dev);
  161. if (!drvdata)
  162. return -EINVAL;
  163. efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
  164. if (!efuse)
  165. return -ENOMEM;
  166. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  167. efuse->base = devm_ioremap_resource(&pdev->dev, res);
  168. if (IS_ERR(efuse->base))
  169. return PTR_ERR(efuse->base);
  170. efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
  171. GFP_KERNEL);
  172. efuse->config.owner = THIS_MODULE;
  173. efuse->config.dev = &pdev->dev;
  174. efuse->config.priv = efuse;
  175. efuse->config.stride = drvdata->word_size;
  176. efuse->config.word_size = drvdata->word_size;
  177. efuse->config.size = SZ_512;
  178. efuse->config.read_only = true;
  179. efuse->config.reg_read = meson_mx_efuse_read;
  180. efuse->core_clk = devm_clk_get(&pdev->dev, "core");
  181. if (IS_ERR(efuse->core_clk)) {
  182. dev_err(&pdev->dev, "Failed to get core clock\n");
  183. return PTR_ERR(efuse->core_clk);
  184. }
  185. efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
  186. return PTR_ERR_OR_ZERO(efuse->nvmem);
  187. }
  188. static struct platform_driver meson_mx_efuse_driver = {
  189. .probe = meson_mx_efuse_probe,
  190. .driver = {
  191. .name = "meson-mx-efuse",
  192. .of_match_table = meson_mx_efuse_match,
  193. },
  194. };
  195. module_platform_driver(meson_mx_efuse_driver);
  196. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  197. MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
  198. MODULE_LICENSE("GPL v2");