light-efuse.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021 Alibaba Inc.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/compiler_types.h>
  7. #include <linux/device.h>
  8. #include <linux/pm_runtime.h>
  9. #include <asm/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/mod_devicetable.h>
  13. #include <linux/nvmem-provider.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/slab.h>
  17. #include <linux/types.h>
  18. #include <linux/mfd/syscon.h>
  19. #define CON 0x00
  20. #define LCPAR 0x04
  21. #define ADDR 0x40
  22. #define WDATA 0x44
  23. #define WDATA_MASK 0x48
  24. #define WP0 0x50
  25. #define WP1 0x54
  26. #define WP2 0x58
  27. #define WP3 0x5c
  28. #define STA 0x70
  29. #define RDATA0 0x80
  30. #define SHADOW_RDATA0 0xc0
  31. #define SHADOW_RDATA1 0xc4
  32. #define SHADOW_RDATA2 0xc8
  33. #define SHADOW_RDATA3 0xcc
  34. #define SHADOW_RDATA4 0xd0
  35. #define SHADOW_RDATA5 0xd4
  36. #define SHADOW_RDATA6 0xd8
  37. #define SHADOW_RDATA7 0xdc
  38. #define TEE_SYS_EFUSE_LC_PRELD_OFF 0x64
  39. #define TEE_SYS_EFUSE_DBG_KEY1_OFF 0x70
  40. #define ENABLE_DFT_FUNC_MASK GENMASK(3, 0)
  41. #define ENABLE_DFT_FUNC 0x5
  42. #define DISABLE_DFT_FUNC 0xa
  43. /* bit definition for CON */
  44. #define EFUSE_CON_POWER_MSK BIT(14)
  45. /* bit definition for STA */
  46. #define EFUSE_STA_IDLE_MSK BIT(0)
  47. #define EFUSE_STA_RD_STATUS_POS 4
  48. #define EFUSE_STA_RD_STATUS_MSK (0x7UL << EFUSE_STA_RD_STATUS_POS)
  49. #define EFUSE_STA_WR_STATUS_POS 8
  50. #define EFUSE_STA_WR_STATUS_MSK (0x7UL << EFUSE_STA_WR_STATUS_POS)
  51. #define EFUSE_STA_CMD_ILLEGAL_POS 11
  52. #define EFUSE_STA_CMD_ILLEGAL_MSK (0x1UL << EFUSE_STA_CMD_ILLEGAL_POS)
  53. #define EFUSE_STA_KTRANS_ALARM_POS 14
  54. #define EFUSE_STA_KTRANS_ALARM_MSK (0x1UL << EFUSE_STA_KTRANS_ALARM_POS)
  55. /* Max try time for idle check */
  56. #define MAX_TRY_TIME_IDLE 10000
  57. #define DEVICE_BUSY 1
  58. #define EFUSE_CON_CMD_POS 8
  59. #define EFUSE_CON_CMD_MSK GENMASK(12, 8)
  60. #define EFUSE_CON_CMD_IDLE (0x0 << EFUSE_CON_CMD_POS)
  61. #define EFUSE_CON_CMD_READ (0x1 << EFUSE_CON_CMD_POS)
  62. #define EFUSE_CON_CMD_WRITE (0x2 << EFUSE_CON_CMD_POS)
  63. #define EFUSE_CON_CMD_BLKREAD (0x3 << EFUSE_CON_CMD_POS)
  64. #define EFUSE_CON_CMD_WP_LOCK (0x8 << EFUSE_CON_CMD_POS)
  65. #define EFUSE_CON_CMD_CP_LOCK (0x9 << EFUSE_CON_CMD_POS)
  66. #define EFUSE_CON_CMD_RP_LOCK (0xA << EFUSE_CON_CMD_POS)
  67. #define EFUSE_CON_CMD_UP_LC (0x10 << EFUSE_CON_CMD_POS)
  68. #define EFUSE_CON_START BIT(0)
  69. #define EFUSE_CON_CLEAR BIT(1)
  70. #define EFUSE_CON_KEY_TRANS_MSK BIT(13)
  71. #define EFUSE_CON_LC_READ_MSK BIT(2)
  72. #define EFUSE_CON_START_MSK BIT(0)
  73. #define EFUSE_CON_MSK (EFUSE_CON_LC_READ_MSK | \
  74. EFUSE_CON_CMD_MSK | \
  75. EFUSE_CON_KEY_TRANS_MSK | \
  76. EFUSE_CON_START_MSK)
  77. #define IS_CVKEY1(addr) ((addr >= 0x38) && (addr < 0x3C))
  78. #define IS_CVKEY2(addr) ((addr >= 0x3C) && (addr < 0x78))
  79. #define IS_USRKEY2(addr) ((addr >= 0x78) && (addr < 0xd8))
  80. /* Block width (bytes) definitions */
  81. #define LIGHT_EFUSE_LIT_BLOCK_WIDTH 16
  82. #define LIGHT_EFUSE_BIG_BLOCK_WIDTH 32
  83. #define LIGHT_EFUSE_LIT_BLOCK_NUM 52
  84. #define LIGHT_EFUSE_BIG_BLOCK_NUM 6
  85. #define RMA_LIFE_CYCLE_PARA 0x1A946F9B
  86. #define RIP_LIFE_CYCLE_PARA 0xEE45E8A7
  87. struct light_efuse_priv {
  88. struct device *dev;
  89. void __iomem *base;
  90. struct regmap *teesys_regs;
  91. struct clk *clk;
  92. u32 sysfs_rd_offset;
  93. u32 sysfs_rd_len;
  94. };
  95. static u32 perm_spi_magic[] = {
  96. 0x9804E1BC,
  97. 0x4B8B59F5,
  98. 0x36D33417,
  99. 0x7491B7D5,
  100. };
  101. static u32 update_lc_magic[] = {
  102. 0x768A7E2F,
  103. 0xE4D53282,
  104. 0x8BD97337,
  105. 0x677B9E85,
  106. };
  107. static u32 read_magic[] = {
  108. 0x32224E05,
  109. 0xC3F981D0,
  110. 0xF4D7FB08,
  111. 0xA4C8C6DE,
  112. };
  113. static u32 write_magic[] = {
  114. 0xB4BC4A0A,
  115. 0x2A8B7E6F,
  116. 0x974B25A1,
  117. 0x67DB5F5F,
  118. };
  119. static u32 block_read_magic[] = {
  120. 0x39CF83C1,
  121. 0xD0DDD6B2,
  122. 0xBD50693B,
  123. 0x5F61B752,
  124. };
  125. static u32 wp_lock_magic[] = {
  126. 0x0D11ECA6,
  127. 0x06EDF631,
  128. 0xB58CA544,
  129. 0x1EBDE503,
  130. };
  131. static u32 cp_lock_magic[] = {
  132. 0xC21E9BB8,
  133. 0x0FC428F1,
  134. 0xD8E95026,
  135. 0x1C34AC41,
  136. };
  137. static u32 rp_lock_magic[] = {
  138. 0xAEB3089A,
  139. 0x8DE56E9A,
  140. 0x453416C2,
  141. 0x969F6937,
  142. };
  143. static u32 key_tran_magic[] = {
  144. 0x1AF5952C,
  145. 0x111B5E55,
  146. 0xFAE8A83D,
  147. 0xEDFE9E7F,
  148. };
  149. static u32 *cmd_perm_magic_num[] = {
  150. perm_spi_magic,
  151. update_lc_magic,
  152. read_magic,
  153. write_magic,
  154. block_read_magic,
  155. wp_lock_magic,
  156. cp_lock_magic,
  157. rp_lock_magic,
  158. key_tran_magic
  159. };
  160. enum permission_type {
  161. CMD_SPI = 0,
  162. CMD_UPDATE_LC,
  163. CMD_READ,
  164. CMD_WRITE,
  165. CMD_BLOCK_READ,
  166. CMD_WP_LOCK,
  167. CMD_CP_LOCK,
  168. CMD_RP_LOCK,
  169. CMD_KEY_TRAN,
  170. CMD_KEY_MAX,
  171. };
  172. enum con_cmd_type {
  173. CON_CMD_IDLE = 0,
  174. CON_CMD_READ,
  175. CON_CMD_WRITE,
  176. CON_CMD_BLOCK_RD,
  177. CON_CMD_WP_LOCK,
  178. CON_CMD_CP_LOCK,
  179. CON_CMD_RP_LOCK,
  180. CON_CMD_UP_LC,
  181. CON_CMD_MAX,
  182. };
  183. static inline bool efuse_poweron_status_get(void __iomem *base)
  184. {
  185. return readl(base + CON) & EFUSE_CON_POWER_MSK ? false : true;
  186. }
  187. static inline int efuse_idle_check(void __iomem *base)
  188. {
  189. int try_cnt = MAX_TRY_TIME_IDLE;
  190. while (try_cnt--) {
  191. if (!(readl(base + STA) & EFUSE_STA_IDLE_MSK))
  192. return 0;
  193. }
  194. if (try_cnt <= 0)
  195. return -DEVICE_BUSY;
  196. return 0;
  197. }
  198. static inline int efuse_status_check(void __iomem *base)
  199. {
  200. u32 data = readl(base + STA);
  201. int errcode;
  202. errcode = data & (EFUSE_STA_RD_STATUS_MSK | EFUSE_STA_WR_STATUS_MSK |
  203. EFUSE_STA_CMD_ILLEGAL_MSK | EFUSE_STA_KTRANS_ALARM_MSK);
  204. pr_debug("[%s,%d]efuse status before clear: 0x%x\n", __func__, __LINE__, errcode);
  205. /* If error happens, write clear should be added */
  206. if (errcode) {
  207. pr_err("error efuse operation STA status: 0x%x\n", errcode);
  208. writel(data, base + STA);
  209. }
  210. return -errcode;
  211. }
  212. static inline int efuse_poweron(void __iomem *base)
  213. {
  214. u32 data;
  215. int ret;
  216. if (efuse_poweron_status_get(base))
  217. return 0;
  218. data = readl(base + CON);
  219. data &= ~EFUSE_CON_POWER_MSK;
  220. writel(data, base + CON);
  221. ret = efuse_idle_check(base);
  222. ret |= efuse_status_check(base);
  223. pr_debug("pd status: 0x%lx\n", readl(base + CON) & EFUSE_CON_POWER_MSK);
  224. return ret;
  225. }
  226. static inline u32 efuse_data_read(void __iomem *base)
  227. {
  228. return readl(base + RDATA0);
  229. }
  230. static inline void efuse_data_clear(void __iomem *base)
  231. {
  232. u32 data = readl(base + CON);
  233. data |= EFUSE_CON_CLEAR;
  234. writel(data, base + CON);
  235. }
  236. static
  237. inline void efuse_permission_magic_config(void __iomem *base, u32 *magic_num[],
  238. enum permission_type cmd)
  239. {
  240. writel(magic_num[cmd][3], base + WP0);
  241. writel(magic_num[cmd][2], base + WP1);
  242. writel(magic_num[cmd][1], base + WP2);
  243. writel(magic_num[cmd][0], base + WP3);
  244. }
  245. static inline void efuse_addr_config(void __iomem *base, u32 addr)
  246. {
  247. writel(addr, base + ADDR);
  248. pr_debug("[%s, %d]efuse addr reg: 0x%x\n", __func__, __LINE__, readl(base + ADDR));
  249. }
  250. static inline void efuse_data_mask_config(void __iomem *base, u32 mask)
  251. {
  252. writel(mask, base + WDATA_MASK);
  253. }
  254. static inline void efuse_data_config(void __iomem *base, u32 data)
  255. {
  256. writel(data, base + WDATA);
  257. pr_debug("[%s, %d]efuse data reg: 0x%x\n", __func__, __LINE__, readl(base + WDATA));
  258. }
  259. static inline void efuse_life_cycle_para_config(void __iomem *base, u32 data)
  260. {
  261. writel(data, base + LCPAR);
  262. }
  263. static inline u32 efuse_life_cycle_para_get(void __iomem *base)
  264. {
  265. return readl(base + LCPAR);
  266. }
  267. static inline int efuse_cmd_start(void __iomem *base, enum con_cmd_type cmd_type)
  268. {
  269. u32 data, cmd;
  270. switch (cmd_type) {
  271. case CON_CMD_IDLE:
  272. cmd = EFUSE_CON_CMD_IDLE;
  273. break;
  274. case CON_CMD_READ:
  275. cmd = EFUSE_CON_CMD_READ;
  276. break;
  277. case CON_CMD_WRITE:
  278. cmd = EFUSE_CON_CMD_WRITE;
  279. break;
  280. case CON_CMD_BLOCK_RD:
  281. cmd = EFUSE_CON_CMD_BLKREAD;
  282. break;
  283. case CON_CMD_WP_LOCK:
  284. cmd = EFUSE_CON_CMD_WP_LOCK;
  285. break;
  286. case CON_CMD_CP_LOCK:
  287. cmd = EFUSE_CON_CMD_CP_LOCK;
  288. break;
  289. case CON_CMD_RP_LOCK:
  290. cmd = EFUSE_CON_CMD_RP_LOCK;
  291. break;
  292. case CON_CMD_UP_LC:
  293. cmd = EFUSE_CON_CMD_UP_LC;
  294. break;
  295. default:
  296. return -EINVAL;
  297. }
  298. /* Mask LC_Read, Key_transfer, command and start bits */
  299. data = readl(base + CON);
  300. data &= ~EFUSE_CON_MSK;
  301. data |= cmd | EFUSE_CON_START;
  302. writel(data, base + CON);
  303. return 0;
  304. }
  305. static DEFINE_MUTEX(light_efuse_mutex);
  306. static int light_efuse_read_start(void __iomem *base, u32 addr, enum con_cmd_type cmd_type)
  307. {
  308. int ret = 0;
  309. enum permission_type permission;
  310. if (cmd_type == CON_CMD_READ)
  311. permission = CMD_READ;
  312. else if (cmd_type == CON_CMD_BLOCK_RD)
  313. permission = CMD_BLOCK_READ;
  314. else {
  315. pr_err("invaid efuse read command type\n");
  316. return -EINVAL;
  317. }
  318. ret = efuse_idle_check(base);
  319. if (ret) {
  320. pr_err("the device is busy\n");
  321. return ret;
  322. }
  323. efuse_permission_magic_config(base, cmd_perm_magic_num, permission);
  324. efuse_addr_config(base, addr);
  325. ret = efuse_cmd_start(base, cmd_type);
  326. if (ret)
  327. return ret;
  328. /* Wait controller completed */
  329. ret = efuse_idle_check(base);
  330. /* Check status, if there has error, reort and clear status */
  331. ret |= efuse_status_check(base);
  332. if (ret) {
  333. pr_err("error occurs while start reading at efuse byte addr: %d\n", addr * 4);
  334. return ret;
  335. }
  336. if (cmd_type == CON_CMD_BLOCK_RD) {
  337. pr_debug("=======================================\n");
  338. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA0));
  339. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA1));
  340. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA2));
  341. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA3));
  342. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA4));
  343. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA5));
  344. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA6));
  345. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA7));
  346. }
  347. return ret;
  348. }
  349. static int light_efuse_read_word(void __iomem *base, u32 addr, u32 *val)
  350. {
  351. int ret = 0;
  352. ret = efuse_idle_check(base);
  353. if (ret)
  354. return ret;
  355. ret = light_efuse_read_start(base, addr, CON_CMD_READ);
  356. if (ret) {
  357. pr_err("failed to start efuse read\n");
  358. goto exit;
  359. }
  360. *val = efuse_data_read(base);
  361. pr_debug("[%s][%d]data = 0x%x\n", __func__, __LINE__,*val);
  362. exit:
  363. efuse_data_clear(base);
  364. return ret;
  365. }
  366. static int light_efuse_write_word(void __iomem *base, u32 addr, u32 data, u32 mask)
  367. {
  368. int ret = 0;
  369. ret = efuse_idle_check(base);
  370. if (ret)
  371. return ret;
  372. /*
  373. * Check permission:
  374. * Check it every time to avoid wp0~3 are changed somewhere
  375. */
  376. efuse_permission_magic_config(base, cmd_perm_magic_num, CMD_WRITE);
  377. /* Config address */
  378. efuse_addr_config(base, addr);
  379. /* Config data */
  380. efuse_data_config(base, data);
  381. /* Config data mask , if we're in keyrange mask should be set to 0 */
  382. if (IS_CVKEY1(addr) || IS_CVKEY2(addr) || IS_USRKEY2(addr))
  383. efuse_data_mask_config(base, 0);
  384. else
  385. efuse_data_mask_config(base, mask);
  386. /* Set write command */
  387. ret = efuse_cmd_start(base, CON_CMD_WRITE);
  388. if (ret)
  389. goto exit;
  390. /* Wait controller completed */
  391. ret = efuse_idle_check(base);
  392. exit:
  393. /* Check status, if there has error, reort and clear status */
  394. ret |= efuse_status_check(base);
  395. if (ret)
  396. pr_err("error occurs while start writing at efuse byte addr: %d\n", addr * 4);
  397. efuse_data_clear(base);
  398. return ret;
  399. }
  400. static int light_efuse_read(void *context, unsigned int addr, void *data, size_t bytes)
  401. {
  402. struct light_efuse_priv *priv = context;
  403. u32 byte_offset, read_count, read_addr;
  404. u8 *pdst, *psrc;
  405. u32 value;
  406. int ret = 0;
  407. mutex_lock(&light_efuse_mutex);
  408. dev_dbg(priv->dev, "[%s]efuse addr: 0x%x, bytes: %d\n", __func__, addr, (int)bytes);
  409. ret = pm_runtime_get_sync(priv->dev);
  410. if (ret < 0) {
  411. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  412. pm_runtime_put_noidle(priv->dev);
  413. goto read_end;
  414. }
  415. if (efuse_poweron(priv->base)) {
  416. dev_err(priv->dev, "failed to power on efuse\n");
  417. ret = -EBUSY;
  418. goto read_end;
  419. }
  420. pdst = data;
  421. byte_offset = addr & 0x3;
  422. read_addr = addr / 4; /* Efuse unit is 4 bytes */
  423. /* byte_offset != 0, means not 4 bytes aligned, read first word first */
  424. if (byte_offset) {
  425. ret = light_efuse_read_word(priv->base, read_addr, &value);
  426. if (ret) {
  427. dev_err(priv->dev, "failed to read efuse data\n");
  428. goto read_end;
  429. }
  430. read_count = 4 - byte_offset;
  431. psrc = (u8 *)&value + byte_offset;
  432. if (bytes < read_count)
  433. read_count = bytes;
  434. memcpy(pdst, psrc, read_count);
  435. read_addr++;
  436. pdst += read_count;
  437. bytes -= read_count;
  438. }
  439. while (bytes >= 4) {
  440. ret = light_efuse_read_word(priv->base, read_addr, &value);
  441. if (ret) {
  442. dev_err(priv->dev, "failed to read efuse data\n");
  443. goto read_end;
  444. }
  445. memcpy(pdst, &value, 4);
  446. bytes -= 4;
  447. read_addr++; /* the hardware will span over one word length automatically */
  448. pdst += 4;
  449. }
  450. if (bytes > 0) {
  451. ret = light_efuse_read_word(priv->base, read_addr, &value);
  452. if (ret) {
  453. dev_err(priv->dev, "failed to read data from efuse\n");
  454. goto read_end;
  455. }
  456. memcpy(pdst, &value, bytes);
  457. }
  458. pm_runtime_put_sync(priv->dev);
  459. read_end:
  460. mutex_unlock(&light_efuse_mutex);
  461. return ret;
  462. }
  463. static int light_efuse_write(void *context, unsigned int addr, void *data, size_t bytes)
  464. {
  465. struct light_efuse_priv *priv = context;
  466. int ret = 0;
  467. u32 byte_offset, write_addr, value = 0;
  468. u32 write_count, mask;
  469. u8 *psrc, *pdst;
  470. size_t __maybe_unused orign_bytes = bytes;
  471. mutex_lock(&light_efuse_mutex);
  472. dev_dbg(priv->dev, "[%s]efuse addr: 0x%x, bytes: %d\n", __func__, addr, (int)bytes);
  473. ret = pm_runtime_get_sync(priv->dev);
  474. if (ret < 0) {
  475. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  476. pm_runtime_put_noidle(priv->dev);
  477. goto write_end;
  478. }
  479. if (efuse_poweron(priv->base)) {
  480. dev_err(priv->dev, "failed to power on efuse\n");
  481. ret = -EBUSY;
  482. goto write_end;
  483. }
  484. byte_offset = addr & 0x3;
  485. psrc = (u8 *)data;
  486. write_addr = addr / 4;
  487. pr_debug("[%s][%d]: write addr = 0x%x\n", __func__, __LINE__, write_addr);
  488. pr_debug("Write data: ");
  489. if (byte_offset) {
  490. write_count = 4 - byte_offset;
  491. if (bytes < write_count)
  492. write_count = bytes;
  493. pdst = (u8 *)&value + byte_offset;
  494. memcpy(pdst, psrc, write_count);
  495. pr_debug("0x%x ", *psrc);
  496. mask = ~value;
  497. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  498. if (ret) {
  499. dev_err(priv->dev, "failed to write data to efuse\n");
  500. goto write_end;
  501. }
  502. psrc += write_count;
  503. write_addr++;
  504. bytes -= write_count;
  505. }
  506. while (bytes >= 4) {
  507. value = 0;
  508. pdst = (u8 *)&value;
  509. write_count = 4;
  510. memcpy(pdst, psrc, write_count);
  511. pr_debug("0x%x ", *psrc);
  512. mask = ~value;
  513. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  514. if (ret) {
  515. dev_err(priv->dev, "failed to write data to efuse\n");
  516. goto write_end;
  517. }
  518. psrc += write_count;
  519. bytes -= write_count;
  520. write_addr++;
  521. }
  522. if (bytes > 0) {
  523. value = 0;
  524. pdst = (u8 *)&value;
  525. memcpy(pdst, psrc, bytes);
  526. pr_debug("0x%x ", *psrc);
  527. mask = ~value;
  528. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  529. if (ret) {
  530. dev_err(priv->dev, "failed to write data to efuse\n");
  531. goto write_end;
  532. }
  533. }
  534. pr_debug("\n");
  535. pm_runtime_put_sync(priv->dev);
  536. write_end:
  537. mutex_unlock(&light_efuse_mutex);
  538. return ret < 0 ? ret : orign_bytes;
  539. }
  540. static ssize_t efuse_nvmem_store(struct device *dev,
  541. struct device_attribute *attr,
  542. const char *buf, size_t count)
  543. {
  544. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  545. char *start = (char *)buf;
  546. char type;
  547. unsigned long addr, len;
  548. unsigned char *data;
  549. int i, ret;
  550. /*
  551. * echo types:
  552. * echo w offset len 0x01 0x02 0x03 ... > efuse_nvmem
  553. * echo r offset len > efuse_nvmem
  554. */
  555. while (*start == ' ') /* skip space */
  556. start++;
  557. if (*start != 'w' && *start != 'r')
  558. return -EINVAL;
  559. type = *start;
  560. start++;
  561. while (*start == ' ')
  562. start++;
  563. addr = simple_strtoul(start, &start, 0);
  564. while (*start == ' ')
  565. start++;
  566. len = simple_strtoul(start, &start, 0);
  567. priv->sysfs_rd_offset = addr;
  568. priv->sysfs_rd_len = len;
  569. if (type == 'r')
  570. goto exit;
  571. data = kzalloc(sizeof(*data) * len, GFP_KERNEL);
  572. if (!data)
  573. return -ENOMEM;
  574. pr_debug("echo data:\n");
  575. for (i = 0; i < len; i++) {
  576. while (*start == ' ')
  577. start++;
  578. data[i] = simple_strtoul(start, &start, 0);
  579. pr_debug("0x%x ", data[i]);
  580. }
  581. ret = light_efuse_write(priv, addr, data, len);
  582. if (ret < 0) {
  583. kfree(data);
  584. return ret;
  585. }
  586. kfree(data);
  587. exit:
  588. return count;
  589. }
  590. static ssize_t efuse_nvmem_show(struct device *dev,
  591. struct device_attribute *attr, char *buf)
  592. {
  593. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  594. u32 addr = priv->sysfs_rd_offset;
  595. u32 len = priv->sysfs_rd_len;
  596. int ret, i;
  597. unsigned char *data;
  598. size_t bufpos = 0, count;
  599. data = kzalloc(sizeof(*data) * len, GFP_KERNEL);
  600. if (!data)
  601. return -ENOMEM;
  602. ret = light_efuse_read(priv, addr, data, len);
  603. if (ret < 0)
  604. goto out;
  605. count = (len + 2) * 10;
  606. for (i = 0; i < len; i++) {
  607. snprintf(buf + bufpos, count - bufpos, "0x%.*x", 2, data[i]);
  608. bufpos += 4;
  609. if (i == len - 1 || (i !=0 && i % 16 == 0))
  610. buf[bufpos++] = '\n';
  611. else
  612. buf[bufpos++] = ' ';
  613. }
  614. out:
  615. kfree(data);
  616. return bufpos;
  617. }
  618. static ssize_t rma_lc_store(struct device *dev,
  619. struct device_attribute *attr,
  620. const char *buf, size_t count)
  621. {
  622. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  623. u32 value = RMA_LIFE_CYCLE_PARA;
  624. int ret;
  625. ret = pm_runtime_get_sync(priv->dev);
  626. if (ret < 0) {
  627. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  628. pm_runtime_put_noidle(priv->dev);
  629. return ret;
  630. }
  631. regmap_update_bits(priv->teesys_regs,
  632. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  633. ENABLE_DFT_FUNC_MASK,
  634. ENABLE_DFT_FUNC);
  635. efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
  636. efuse_life_cycle_para_config(priv->base, value);
  637. /* Set command */
  638. ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
  639. if (ret)
  640. goto exit;
  641. /* Wait controller completed */
  642. ret = efuse_idle_check(priv->base);
  643. pr_debug("set life cycle value: 0x%x\n", value);
  644. exit:
  645. regmap_update_bits(priv->teesys_regs,
  646. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  647. ENABLE_DFT_FUNC_MASK,
  648. DISABLE_DFT_FUNC);
  649. /* Check status, if there has error, reort and clear status */
  650. ret |= efuse_status_check(priv->base);
  651. if (ret)
  652. pr_err("error occurs while starting write\n");
  653. efuse_data_clear(priv->base);
  654. pm_runtime_put_sync(priv->dev);
  655. return ret < 0 ? ret : count;
  656. }
  657. static ssize_t rip_lc_store(struct device *dev,
  658. struct device_attribute *attr,
  659. const char *buf, size_t count)
  660. {
  661. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  662. u32 value = RIP_LIFE_CYCLE_PARA;
  663. int ret;
  664. ret = pm_runtime_get_sync(priv->dev);
  665. if (ret < 0) {
  666. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  667. pm_runtime_put_noidle(priv->dev);
  668. return ret;
  669. }
  670. efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
  671. efuse_life_cycle_para_config(priv->base, value);
  672. /* Set command */
  673. ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
  674. if (ret)
  675. goto exit;
  676. /* Wait controller completed */
  677. ret = efuse_idle_check(priv->base);
  678. exit:
  679. /* Check status, if there has error, reort and clear status */
  680. ret |= efuse_status_check(priv->base);
  681. if (ret)
  682. pr_err("error occurs while starting write\n");
  683. efuse_data_clear(priv->base);
  684. pm_runtime_put_sync(priv->dev);
  685. return ret < 0 ? ret : count;
  686. }
  687. static ssize_t lc_preld_show(struct device *dev,
  688. struct device_attribute *attr, char *buf)
  689. {
  690. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  691. int ret;
  692. u32 data;
  693. ret = regmap_read(priv->teesys_regs, TEE_SYS_EFUSE_LC_PRELD_OFF, &data);
  694. if (ret) {
  695. dev_err(dev, "failed to read data from LC_PRELD area\n");
  696. return ret;
  697. }
  698. return sprintf(buf, "0x%08x\n", data);
  699. }
  700. static ssize_t update_lc_store(struct device *dev,
  701. struct device_attribute *attr,
  702. const char *buf, size_t count)
  703. {
  704. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  705. int ret;
  706. u32 value, data;
  707. const char *p, *life_cycle = buf;
  708. int len;
  709. p = memchr(buf, '\n', count);
  710. len = p ? p - buf : count;
  711. dev_dbg(dev, "life_cycle: %s, buf: %s, len: %d\n", life_cycle, buf, len);
  712. if (!strncmp(life_cycle, "LC_RMA", len)) {
  713. /* If target life cycle is RMA, open permission in teesystem regs */
  714. ret = regmap_read(priv->teesys_regs,
  715. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  716. &data); /* Register from tee system */
  717. if (ret) {
  718. dev_err(dev, "failed to read data from DBG_KEY1 area\n");
  719. return ret;
  720. }
  721. data &= ~0xf;
  722. data |= 0x5;
  723. ret = regmap_write(priv->teesys_regs,
  724. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  725. data);
  726. if (ret) {
  727. dev_err(dev, "failed to write data to DBG_KEY1 area\n");
  728. return ret;
  729. }
  730. value = 0x1A946F9B;
  731. } else if (!strncmp(life_cycle, "LC_OEM", len))
  732. value = 0x64EA9B8E;
  733. else if (!strncmp(life_cycle, "LC_PRO", len))
  734. value = 0xB0E047A8;
  735. else if (!strncmp(life_cycle, "LC_DEV", len))
  736. value = 0x59DD3BDF;
  737. else if (!strncmp(life_cycle, "LC_RIP", len))
  738. value = 0xEE45E8A7;
  739. else if (!strncmp(life_cycle, "LC_KILL_KEY1", len))
  740. value = 0x7D8E9CA1;
  741. else if (!strncmp(life_cycle, "LC_KILL_KEY0", len))
  742. value = 0xC29F604B;
  743. else {
  744. dev_err(dev, "invalid life cycle type!\n");
  745. return -EINVAL;
  746. }
  747. /*
  748. * Check permission:
  749. * Check it every time to avoid wp0~3 are changed somewhere
  750. */
  751. efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
  752. /* Config life cycle */
  753. efuse_life_cycle_para_config(priv->base, value);
  754. /* set command */
  755. ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
  756. if (ret)
  757. goto exit;
  758. /* Wait controller completed */
  759. ret = efuse_idle_check(priv->base);
  760. exit:
  761. /* Check status, if there has error, reort and clear status */
  762. ret |= efuse_status_check(priv->base);
  763. if (ret)
  764. dev_err(dev, "error occurs while starting write\n");
  765. efuse_data_clear(priv->base);
  766. if (strncmp(life_cycle, "LC_RMA", len))
  767. goto out;
  768. dev_info(dev, "set LC_RMA life cycle\n");
  769. /* If target life cycle is RMA, close permission in teesystem regs */
  770. ret = regmap_read(priv->teesys_regs,
  771. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  772. &data); /* Register from tee system */
  773. if (ret) {
  774. dev_err(dev, "failed to read data from DBG_KEY1 area\n");
  775. return ret;
  776. }
  777. data &= ~0xf;
  778. data |= 0xa;
  779. ret = regmap_write(priv->teesys_regs,
  780. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  781. data);
  782. if (ret) {
  783. dev_err(dev, "failed to write data to DBG_KEY1 area\n");
  784. return ret;
  785. }
  786. out:
  787. return ret < 0 ? ret : count;
  788. }
  789. static DEVICE_ATTR_WO(rma_lc);
  790. static DEVICE_ATTR_WO(rip_lc);
  791. static DEVICE_ATTR_RW(efuse_nvmem);
  792. static DEVICE_ATTR_RO(lc_preld);
  793. static DEVICE_ATTR_WO(update_lc);
  794. static struct attribute *light_efuse_sysfs_entries[] = {
  795. &dev_attr_efuse_nvmem.attr,
  796. &dev_attr_rip_lc.attr,
  797. &dev_attr_rma_lc.attr,
  798. &dev_attr_lc_preld.attr,
  799. &dev_attr_update_lc.attr,
  800. NULL
  801. };
  802. static const struct attribute_group dev_attr_efuse_sysfs_group = {
  803. .attrs = light_efuse_sysfs_entries,
  804. };
  805. static const struct of_device_id light_efuse_of_match[] = {
  806. {.compatible = "thead,light-fm-efuse"},
  807. { /* sentinel */},
  808. };
  809. MODULE_DEVICE_TABLE(of, light_efuse_of_match);
  810. static int __maybe_unused light_efuse_runtime_suspend(struct device *dev)
  811. {
  812. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  813. u32 data;
  814. int ret;
  815. dev_dbg(dev, "[%s,%d]efuse runtime power down\n", __func__, __LINE__);
  816. if (!efuse_poweron_status_get(priv->base))
  817. return 0;
  818. data = readl(priv->base + CON);
  819. data |= EFUSE_CON_POWER_MSK;
  820. writel(data, priv->base + CON);
  821. ret = efuse_idle_check(priv->base);
  822. ret |= efuse_status_check(priv->base);
  823. dev_dbg(dev, "[%s,%d] ret = %d, pd status: 0x%lx\n", __func__, __LINE__, ret,
  824. readl(priv->base + CON) & EFUSE_CON_POWER_MSK);
  825. return ret;
  826. }
  827. static int __maybe_unused light_efuse_runtime_resume(struct device *dev)
  828. {
  829. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  830. dev_dbg(dev, "[%s,%d]efuse runtime power on\n", __func__, __LINE__);
  831. return efuse_poweron(priv->base);
  832. }
  833. static int light_efuse_probe(struct platform_device *pdev)
  834. {
  835. struct device *dev = &pdev->dev;
  836. struct nvmem_device *nvmem;
  837. struct nvmem_config config = {};
  838. struct light_efuse_priv *priv;
  839. int ret;
  840. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  841. if (!priv)
  842. return -ENOMEM;
  843. priv->base = devm_platform_ioremap_resource(pdev, 0);
  844. if (IS_ERR(priv->base))
  845. return PTR_ERR(priv->base);
  846. /* optional clock, default open */
  847. priv->clk = devm_clk_get(dev, NULL);
  848. if (IS_ERR(priv->clk))
  849. priv->clk = NULL;
  850. priv->teesys_regs = syscon_regmap_lookup_by_phandle(dev->of_node, "thead,teesys");
  851. if (IS_ERR(priv->teesys_regs)) {
  852. dev_err(dev, "unable to find teesys registers\n");
  853. return PTR_ERR(priv->teesys_regs);
  854. }
  855. priv->dev = dev;
  856. dev_set_drvdata(dev, priv);
  857. ret = sysfs_create_group(&dev->kobj, &dev_attr_efuse_sysfs_group);
  858. if (ret) {
  859. dev_err(dev, "failed to create efuse debug sysfs\n");
  860. return ret;
  861. }
  862. config.name = "light-efuse";
  863. config.read_only = false;
  864. config.stride = 1;
  865. config.word_size = 1; /* the least read and write unit on the upper level */
  866. config.reg_read = light_efuse_read;
  867. config.reg_write = light_efuse_write;
  868. config.size = LIGHT_EFUSE_LIT_BLOCK_NUM * LIGHT_EFUSE_LIT_BLOCK_WIDTH +
  869. LIGHT_EFUSE_BIG_BLOCK_NUM * LIGHT_EFUSE_BIG_BLOCK_WIDTH;
  870. config.priv = priv;
  871. config.dev = dev;
  872. nvmem = devm_nvmem_register(dev, &config);
  873. if (IS_ERR(nvmem))
  874. return PTR_ERR_OR_ZERO(nvmem);
  875. pm_runtime_enable(dev);
  876. dev_info(dev, "succeed to register light efuse driver\n");
  877. return 0;
  878. }
  879. static const struct dev_pm_ops efuse_runtime_pm_ops = {
  880. SET_RUNTIME_PM_OPS(light_efuse_runtime_suspend, light_efuse_runtime_resume, NULL)
  881. };
  882. static struct platform_driver light_efuse_driver = {
  883. .probe = light_efuse_probe,
  884. .driver = {
  885. .name = "light_efuse",
  886. .of_match_table = light_efuse_of_match,
  887. .pm = &efuse_runtime_pm_ops,
  888. },
  889. };
  890. module_platform_driver(light_efuse_driver);
  891. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  892. MODULE_DESCRIPTION("Thead light nvmem driver");
  893. MODULE_LICENSE("GPL v2");