jz4780-efuse.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * JZ4780 EFUSE Memory Support driver
  4. *
  5. * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
  6. * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
  7. */
  8. /*
  9. * Currently supports JZ4780 efuse which has 8K programmable bit.
  10. * Efuse is separated into seven segments as below:
  11. *
  12. * -----------------------------------------------------------------------
  13. * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
  14. * -----------------------------------------------------------------------
  15. *
  16. * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
  17. * which reads/writes based on strobes. The strobe is configured in the config
  18. * register and is based on number of cycles of the bus clock.
  19. *
  20. * Driver supports read only as the writes are done in the Factory.
  21. */
  22. #include <linux/bitops.h>
  23. #include <linux/clk.h>
  24. #include <linux/module.h>
  25. #include <linux/nvmem-provider.h>
  26. #include <linux/of.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/regmap.h>
  29. #include <linux/timer.h>
  30. #define JZ_EFUCTRL (0x0) /* Control Register */
  31. #define JZ_EFUCFG (0x4) /* Configure Register*/
  32. #define JZ_EFUSTATE (0x8) /* Status Register */
  33. #define JZ_EFUDATA(n) (0xC + (n) * 4)
  34. /* We read 32 byte chunks to avoid complexity in the driver. */
  35. #define JZ_EFU_READ_SIZE 32
  36. #define EFUCTRL_ADDR_MASK 0x3FF
  37. #define EFUCTRL_ADDR_SHIFT 21
  38. #define EFUCTRL_LEN_MASK 0x1F
  39. #define EFUCTRL_LEN_SHIFT 16
  40. #define EFUCTRL_PG_EN BIT(15)
  41. #define EFUCTRL_WR_EN BIT(1)
  42. #define EFUCTRL_RD_EN BIT(0)
  43. #define EFUCFG_INT_EN BIT(31)
  44. #define EFUCFG_RD_ADJ_MASK 0xF
  45. #define EFUCFG_RD_ADJ_SHIFT 20
  46. #define EFUCFG_RD_STR_MASK 0xF
  47. #define EFUCFG_RD_STR_SHIFT 16
  48. #define EFUCFG_WR_ADJ_MASK 0xF
  49. #define EFUCFG_WR_ADJ_SHIFT 12
  50. #define EFUCFG_WR_STR_MASK 0xFFF
  51. #define EFUCFG_WR_STR_SHIFT 0
  52. #define EFUSTATE_WR_DONE BIT(1)
  53. #define EFUSTATE_RD_DONE BIT(0)
  54. struct jz4780_efuse {
  55. struct device *dev;
  56. struct regmap *map;
  57. struct clk *clk;
  58. };
  59. /* main entry point */
  60. static int jz4780_efuse_read(void *context, unsigned int offset,
  61. void *val, size_t bytes)
  62. {
  63. struct jz4780_efuse *efuse = context;
  64. while (bytes > 0) {
  65. size_t start = offset & ~(JZ_EFU_READ_SIZE - 1);
  66. size_t chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
  67. - offset);
  68. char buf[JZ_EFU_READ_SIZE];
  69. unsigned int tmp;
  70. u32 ctrl;
  71. int ret;
  72. ctrl = (start << EFUCTRL_ADDR_SHIFT)
  73. | ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
  74. | EFUCTRL_RD_EN;
  75. regmap_update_bits(efuse->map, JZ_EFUCTRL,
  76. (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
  77. (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
  78. EFUCTRL_PG_EN | EFUCTRL_WR_EN |
  79. EFUCTRL_RD_EN,
  80. ctrl);
  81. ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
  82. tmp, tmp & EFUSTATE_RD_DONE,
  83. 1 * MSEC_PER_SEC,
  84. 50 * MSEC_PER_SEC);
  85. if (ret < 0) {
  86. dev_err(efuse->dev, "Time out while reading efuse data");
  87. return ret;
  88. }
  89. ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
  90. buf, JZ_EFU_READ_SIZE / sizeof(u32));
  91. if (ret < 0)
  92. return ret;
  93. memcpy(val, &buf[offset - start], chunk);
  94. val += chunk;
  95. offset += chunk;
  96. bytes -= chunk;
  97. }
  98. return 0;
  99. }
  100. static struct nvmem_config jz4780_efuse_nvmem_config = {
  101. .name = "jz4780-efuse",
  102. .size = 1024,
  103. .word_size = 1,
  104. .stride = 1,
  105. .owner = THIS_MODULE,
  106. .reg_read = jz4780_efuse_read,
  107. };
  108. static const struct regmap_config jz4780_efuse_regmap_config = {
  109. .reg_bits = 32,
  110. .val_bits = 32,
  111. .reg_stride = 4,
  112. .max_register = JZ_EFUDATA(7),
  113. };
  114. static void clk_disable_unprepare_helper(void *clock)
  115. {
  116. clk_disable_unprepare(clock);
  117. }
  118. static int jz4780_efuse_probe(struct platform_device *pdev)
  119. {
  120. struct nvmem_device *nvmem;
  121. struct jz4780_efuse *efuse;
  122. struct nvmem_config cfg;
  123. unsigned long clk_rate;
  124. unsigned long rd_adj;
  125. unsigned long rd_strobe;
  126. struct device *dev = &pdev->dev;
  127. void __iomem *regs;
  128. int ret;
  129. efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
  130. if (!efuse)
  131. return -ENOMEM;
  132. regs = devm_platform_ioremap_resource(pdev, 0);
  133. if (IS_ERR(regs))
  134. return PTR_ERR(regs);
  135. efuse->map = devm_regmap_init_mmio(dev, regs,
  136. &jz4780_efuse_regmap_config);
  137. if (IS_ERR(efuse->map))
  138. return PTR_ERR(efuse->map);
  139. efuse->clk = devm_clk_get(&pdev->dev, NULL);
  140. if (IS_ERR(efuse->clk))
  141. return PTR_ERR(efuse->clk);
  142. ret = clk_prepare_enable(efuse->clk);
  143. if (ret < 0)
  144. return ret;
  145. ret = devm_add_action_or_reset(&pdev->dev,
  146. clk_disable_unprepare_helper,
  147. efuse->clk);
  148. if (ret < 0)
  149. return ret;
  150. clk_rate = clk_get_rate(efuse->clk);
  151. efuse->dev = dev;
  152. /*
  153. * rd_adj and rd_strobe are 4 bit values
  154. * conditions:
  155. * bus clk_period * (rd_adj + 1) > 6.5ns
  156. * bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
  157. * i.e. rd_adj >= 6.5ns / clk_period
  158. * i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
  159. * constants:
  160. * 1 / 6.5ns == 153846154 Hz
  161. * 1 / 35ns == 28571429 Hz
  162. */
  163. rd_adj = clk_rate / 153846154;
  164. rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
  165. if (rd_adj > EFUCFG_RD_ADJ_MASK ||
  166. rd_strobe > EFUCFG_RD_STR_MASK) {
  167. dev_err(&pdev->dev, "Cannot set clock configuration\n");
  168. return -EINVAL;
  169. }
  170. regmap_update_bits(efuse->map, JZ_EFUCFG,
  171. (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
  172. (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
  173. (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
  174. (rd_strobe << EFUCFG_RD_STR_SHIFT));
  175. cfg = jz4780_efuse_nvmem_config;
  176. cfg.dev = &pdev->dev;
  177. cfg.priv = efuse;
  178. nvmem = devm_nvmem_register(dev, &cfg);
  179. return PTR_ERR_OR_ZERO(nvmem);
  180. }
  181. static const struct of_device_id jz4780_efuse_match[] = {
  182. { .compatible = "ingenic,jz4780-efuse" },
  183. { /* sentinel */ },
  184. };
  185. MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
  186. static struct platform_driver jz4780_efuse_driver = {
  187. .probe = jz4780_efuse_probe,
  188. .driver = {
  189. .name = "jz4780-efuse",
  190. .of_match_table = jz4780_efuse_match,
  191. },
  192. };
  193. module_platform_driver(jz4780_efuse_driver);
  194. MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
  195. MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
  196. MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
  197. MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
  198. MODULE_LICENSE("GPL v2");