imx-ocotp.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * i.MX6 OCOTP fusebox driver
  4. *
  5. * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
  6. *
  7. * Based on the barebox ocotp driver,
  8. * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
  9. * Orex Computed Radiography
  10. *
  11. * Write support based on the fsl_otp driver,
  12. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/device.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/nvmem-provider.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
  25. * OTP Bank0 Word0
  26. */
  27. #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
  28. * of two consecutive OTP words.
  29. */
  30. #define IMX_OCOTP_ADDR_CTRL 0x0000
  31. #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
  32. #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
  33. #define IMX_OCOTP_ADDR_TIMING 0x0010
  34. #define IMX_OCOTP_ADDR_DATA0 0x0020
  35. #define IMX_OCOTP_ADDR_DATA1 0x0030
  36. #define IMX_OCOTP_ADDR_DATA2 0x0040
  37. #define IMX_OCOTP_ADDR_DATA3 0x0050
  38. #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
  39. #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
  40. #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
  41. #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
  42. #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF
  43. #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200
  44. #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400
  45. #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800
  46. #define IMX_OCOTP_BM_CTRL_DEFAULT \
  47. { \
  48. .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \
  49. .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \
  50. .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \
  51. .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
  52. }
  53. #define IMX_OCOTP_BM_CTRL_8MP \
  54. { \
  55. .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \
  56. .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \
  57. .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \
  58. .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
  59. }
  60. #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
  61. #define TIMING_STROBE_READ_NS 37 /* Min time before read */
  62. #define TIMING_RELAX_NS 17
  63. #define DEF_FSOURCE 1001 /* > 1000 ns */
  64. #define DEF_STROBE_PROG 10000 /* IPG clocks */
  65. #define IMX_OCOTP_WR_UNLOCK 0x3E770000
  66. #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
  67. static DEFINE_MUTEX(ocotp_mutex);
  68. struct ocotp_priv {
  69. struct device *dev;
  70. struct clk *clk;
  71. void __iomem *base;
  72. const struct ocotp_params *params;
  73. struct nvmem_config *config;
  74. };
  75. struct ocotp_ctrl_reg {
  76. u32 bm_addr;
  77. u32 bm_busy;
  78. u32 bm_error;
  79. u32 bm_rel_shadows;
  80. };
  81. struct ocotp_params {
  82. unsigned int nregs;
  83. unsigned int bank_address_words;
  84. void (*set_timing)(struct ocotp_priv *priv);
  85. struct ocotp_ctrl_reg ctrl;
  86. };
  87. static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
  88. {
  89. int count;
  90. u32 c, mask;
  91. u32 bm_ctrl_busy, bm_ctrl_error;
  92. void __iomem *base = priv->base;
  93. bm_ctrl_busy = priv->params->ctrl.bm_busy;
  94. bm_ctrl_error = priv->params->ctrl.bm_error;
  95. mask = bm_ctrl_busy | bm_ctrl_error | flags;
  96. for (count = 10000; count >= 0; count--) {
  97. c = readl(base + IMX_OCOTP_ADDR_CTRL);
  98. if (!(c & mask))
  99. break;
  100. cpu_relax();
  101. }
  102. if (count < 0) {
  103. /* HW_OCOTP_CTRL[ERROR] will be set under the following
  104. * conditions:
  105. * - A write is performed to a shadow register during a shadow
  106. * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
  107. * set. In addition, the contents of the shadow register shall
  108. * not be updated.
  109. * - A write is performed to a shadow register which has been
  110. * locked.
  111. * - A read is performed to from a shadow register which has
  112. * been read locked.
  113. * - A program is performed to a fuse word which has been locked
  114. * - A read is performed to from a fuse word which has been read
  115. * locked.
  116. */
  117. if (c & bm_ctrl_error)
  118. return -EPERM;
  119. return -ETIMEDOUT;
  120. }
  121. return 0;
  122. }
  123. static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
  124. {
  125. u32 c, bm_ctrl_error;
  126. void __iomem *base = priv->base;
  127. bm_ctrl_error = priv->params->ctrl.bm_error;
  128. c = readl(base + IMX_OCOTP_ADDR_CTRL);
  129. if (!(c & bm_ctrl_error))
  130. return;
  131. writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
  132. }
  133. static int imx_ocotp_read(void *context, unsigned int offset,
  134. void *val, size_t bytes)
  135. {
  136. struct ocotp_priv *priv = context;
  137. unsigned int count;
  138. u32 *buf = val;
  139. int i, ret;
  140. u32 index;
  141. index = offset >> 2;
  142. count = bytes >> 2;
  143. if (count > (priv->params->nregs - index))
  144. count = priv->params->nregs - index;
  145. mutex_lock(&ocotp_mutex);
  146. ret = clk_prepare_enable(priv->clk);
  147. if (ret < 0) {
  148. mutex_unlock(&ocotp_mutex);
  149. dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
  150. return ret;
  151. }
  152. ret = imx_ocotp_wait_for_busy(priv, 0);
  153. if (ret < 0) {
  154. dev_err(priv->dev, "timeout during read setup\n");
  155. goto read_end;
  156. }
  157. for (i = index; i < (index + count); i++) {
  158. *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
  159. i * IMX_OCOTP_OFFSET_PER_WORD);
  160. /* 47.3.1.2
  161. * For "read locked" registers 0xBADABADA will be returned and
  162. * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
  163. * software before any new write, read or reload access can be
  164. * issued
  165. */
  166. if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
  167. imx_ocotp_clr_err_if_set(priv);
  168. }
  169. read_end:
  170. clk_disable_unprepare(priv->clk);
  171. mutex_unlock(&ocotp_mutex);
  172. return ret;
  173. }
  174. static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
  175. {
  176. unsigned long clk_rate;
  177. unsigned long strobe_read, relax, strobe_prog;
  178. u32 timing;
  179. /* 47.3.1.3.1
  180. * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
  181. * fields with timing values to match the current frequency of the
  182. * ipg_clk. OTP writes will work at maximum bus frequencies as long
  183. * as the HW_OCOTP_TIMING parameters are set correctly.
  184. *
  185. * Note: there are minimum timings required to ensure an OTP fuse burns
  186. * correctly that are independent of the ipg_clk. Those values are not
  187. * formally documented anywhere however, working from the minimum
  188. * timings given in u-boot we can say:
  189. *
  190. * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
  191. * microseconds feels about right as representative of a minimum time
  192. * to physically burn out a fuse.
  193. *
  194. * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
  195. * performing another read is 37 nanoseconds
  196. *
  197. * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
  198. * timing is not entirely clear the documentation says "This
  199. * count value specifies the time to add to all default timing
  200. * parameters other than the Tpgm and Trd. It is given in number
  201. * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
  202. * and STROBE_READ respectively. What the other timing parameters
  203. * are though, is not specified. Experience shows a zero RELAX
  204. * value will mess up a re-load of the shadow registers post OTP
  205. * burn.
  206. */
  207. clk_rate = clk_get_rate(priv->clk);
  208. relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
  209. strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
  210. 1000000000);
  211. strobe_read += 2 * (relax + 1) - 1;
  212. strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
  213. 1000000);
  214. strobe_prog += 2 * (relax + 1) - 1;
  215. timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
  216. timing |= strobe_prog & 0x00000FFF;
  217. timing |= (relax << 12) & 0x0000F000;
  218. timing |= (strobe_read << 16) & 0x003F0000;
  219. writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
  220. }
  221. static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
  222. {
  223. unsigned long clk_rate;
  224. u64 fsource, strobe_prog;
  225. u32 timing;
  226. /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
  227. * 6.4.3.3
  228. */
  229. clk_rate = clk_get_rate(priv->clk);
  230. fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
  231. NSEC_PER_SEC) + 1;
  232. strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
  233. NSEC_PER_SEC) + 1;
  234. timing = strobe_prog & 0x00000FFF;
  235. timing |= (fsource << 12) & 0x000FF000;
  236. writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
  237. }
  238. static int imx_ocotp_write(void *context, unsigned int offset, void *val,
  239. size_t bytes)
  240. {
  241. struct ocotp_priv *priv = context;
  242. u32 *buf = val;
  243. int ret;
  244. u32 ctrl;
  245. u8 waddr;
  246. u8 word = 0;
  247. /* allow only writing one complete OTP word at a time */
  248. if ((bytes != priv->config->word_size) ||
  249. (offset % priv->config->word_size))
  250. return -EINVAL;
  251. mutex_lock(&ocotp_mutex);
  252. ret = clk_prepare_enable(priv->clk);
  253. if (ret < 0) {
  254. mutex_unlock(&ocotp_mutex);
  255. dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
  256. return ret;
  257. }
  258. /* Setup the write timing values */
  259. priv->params->set_timing(priv);
  260. /* 47.3.1.3.2
  261. * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
  262. * Overlapped accesses are not supported by the controller. Any pending
  263. * write or reload must be completed before a write access can be
  264. * requested.
  265. */
  266. ret = imx_ocotp_wait_for_busy(priv, 0);
  267. if (ret < 0) {
  268. dev_err(priv->dev, "timeout during timing setup\n");
  269. goto write_end;
  270. }
  271. /* 47.3.1.3.3
  272. * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
  273. * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
  274. * for each write access. The lock code is documented in the register
  275. * description. Both the unlock code and address can be written in the
  276. * same operation.
  277. */
  278. if (priv->params->bank_address_words != 0) {
  279. /*
  280. * In banked/i.MX7 mode the OTP register bank goes into waddr
  281. * see i.MX 7Solo Applications Processor Reference Manual, Rev.
  282. * 0.1 section 6.4.3.1
  283. */
  284. offset = offset / priv->config->word_size;
  285. waddr = offset / priv->params->bank_address_words;
  286. word = offset & (priv->params->bank_address_words - 1);
  287. } else {
  288. /*
  289. * Non-banked i.MX6 mode.
  290. * OTP write/read address specifies one of 128 word address
  291. * locations
  292. */
  293. waddr = offset / 4;
  294. }
  295. ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
  296. ctrl &= ~priv->params->ctrl.bm_addr;
  297. ctrl |= waddr & priv->params->ctrl.bm_addr;
  298. ctrl |= IMX_OCOTP_WR_UNLOCK;
  299. writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
  300. /* 47.3.1.3.4
  301. * Write the data to the HW_OCOTP_DATA register. This will automatically
  302. * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
  303. * protect programming same OTP bit twice, before program OCOTP will
  304. * automatically read fuse value in OTP and use read value to mask
  305. * program data. The controller will use masked program data to program
  306. * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
  307. * fields with 1's will result in that OTP bit being programmed. Bit
  308. * fields with 0's will be ignored. At the same time that the write is
  309. * accepted, the controller makes an internal copy of
  310. * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
  311. * sequence is initiated. This copy guarantees that erroneous writes to
  312. * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
  313. * should also be noted that during the programming HW_OCOTP_DATA will
  314. * shift right (with zero fill). This shifting is required to program
  315. * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
  316. * modified.
  317. * Note: on i.MX7 there are four data fields to write for banked write
  318. * with the fuse blowing operation only taking place after data0
  319. * has been written. This is why data0 must always be the last
  320. * register written.
  321. */
  322. if (priv->params->bank_address_words != 0) {
  323. /* Banked/i.MX7 mode */
  324. switch (word) {
  325. case 0:
  326. writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
  327. writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
  328. writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
  329. writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
  330. break;
  331. case 1:
  332. writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
  333. writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
  334. writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
  335. writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
  336. break;
  337. case 2:
  338. writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
  339. writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
  340. writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
  341. writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
  342. break;
  343. case 3:
  344. writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
  345. writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
  346. writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
  347. writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
  348. break;
  349. }
  350. } else {
  351. /* Non-banked i.MX6 mode */
  352. writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
  353. }
  354. /* 47.4.1.4.5
  355. * Once complete, the controller will clear BUSY. A write request to a
  356. * protected or locked region will result in no OTP access and no
  357. * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
  358. * be set. It must be cleared by software before any new write access
  359. * can be issued.
  360. */
  361. ret = imx_ocotp_wait_for_busy(priv, 0);
  362. if (ret < 0) {
  363. if (ret == -EPERM) {
  364. dev_err(priv->dev, "failed write to locked region");
  365. imx_ocotp_clr_err_if_set(priv);
  366. } else {
  367. dev_err(priv->dev, "timeout during data write\n");
  368. }
  369. goto write_end;
  370. }
  371. /* 47.3.1.4
  372. * Write Postamble: Due to internal electrical characteristics of the
  373. * OTP during writes, all OTP operations following a write must be
  374. * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
  375. * the write.
  376. */
  377. udelay(2);
  378. /* reload all shadow registers */
  379. writel(priv->params->ctrl.bm_rel_shadows,
  380. priv->base + IMX_OCOTP_ADDR_CTRL_SET);
  381. ret = imx_ocotp_wait_for_busy(priv,
  382. priv->params->ctrl.bm_rel_shadows);
  383. if (ret < 0)
  384. dev_err(priv->dev, "timeout during shadow register reload\n");
  385. write_end:
  386. clk_disable_unprepare(priv->clk);
  387. mutex_unlock(&ocotp_mutex);
  388. return ret < 0 ? ret : bytes;
  389. }
  390. static struct nvmem_config imx_ocotp_nvmem_config = {
  391. .name = "imx-ocotp",
  392. .read_only = false,
  393. .word_size = 4,
  394. .stride = 4,
  395. .reg_read = imx_ocotp_read,
  396. .reg_write = imx_ocotp_write,
  397. };
  398. static const struct ocotp_params imx6q_params = {
  399. .nregs = 128,
  400. .bank_address_words = 0,
  401. .set_timing = imx_ocotp_set_imx6_timing,
  402. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  403. };
  404. static const struct ocotp_params imx6sl_params = {
  405. .nregs = 64,
  406. .bank_address_words = 0,
  407. .set_timing = imx_ocotp_set_imx6_timing,
  408. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  409. };
  410. static const struct ocotp_params imx6sll_params = {
  411. .nregs = 128,
  412. .bank_address_words = 0,
  413. .set_timing = imx_ocotp_set_imx6_timing,
  414. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  415. };
  416. static const struct ocotp_params imx6sx_params = {
  417. .nregs = 128,
  418. .bank_address_words = 0,
  419. .set_timing = imx_ocotp_set_imx6_timing,
  420. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  421. };
  422. static const struct ocotp_params imx6ul_params = {
  423. .nregs = 128,
  424. .bank_address_words = 0,
  425. .set_timing = imx_ocotp_set_imx6_timing,
  426. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  427. };
  428. static const struct ocotp_params imx6ull_params = {
  429. .nregs = 64,
  430. .bank_address_words = 0,
  431. .set_timing = imx_ocotp_set_imx6_timing,
  432. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  433. };
  434. static const struct ocotp_params imx7d_params = {
  435. .nregs = 64,
  436. .bank_address_words = 4,
  437. .set_timing = imx_ocotp_set_imx7_timing,
  438. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  439. };
  440. static const struct ocotp_params imx7ulp_params = {
  441. .nregs = 256,
  442. .bank_address_words = 0,
  443. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  444. };
  445. static const struct ocotp_params imx8mq_params = {
  446. .nregs = 256,
  447. .bank_address_words = 0,
  448. .set_timing = imx_ocotp_set_imx6_timing,
  449. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  450. };
  451. static const struct ocotp_params imx8mm_params = {
  452. .nregs = 256,
  453. .bank_address_words = 0,
  454. .set_timing = imx_ocotp_set_imx6_timing,
  455. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  456. };
  457. static const struct ocotp_params imx8mn_params = {
  458. .nregs = 256,
  459. .bank_address_words = 0,
  460. .set_timing = imx_ocotp_set_imx6_timing,
  461. .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
  462. };
  463. static const struct ocotp_params imx8mp_params = {
  464. .nregs = 384,
  465. .bank_address_words = 0,
  466. .set_timing = imx_ocotp_set_imx6_timing,
  467. .ctrl = IMX_OCOTP_BM_CTRL_8MP,
  468. };
  469. static const struct of_device_id imx_ocotp_dt_ids[] = {
  470. { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
  471. { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
  472. { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
  473. { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
  474. { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
  475. { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
  476. { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
  477. { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
  478. { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
  479. { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
  480. { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
  481. { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
  482. { },
  483. };
  484. MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
  485. static int imx_ocotp_probe(struct platform_device *pdev)
  486. {
  487. struct device *dev = &pdev->dev;
  488. struct ocotp_priv *priv;
  489. struct nvmem_device *nvmem;
  490. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  491. if (!priv)
  492. return -ENOMEM;
  493. priv->dev = dev;
  494. priv->base = devm_platform_ioremap_resource(pdev, 0);
  495. if (IS_ERR(priv->base))
  496. return PTR_ERR(priv->base);
  497. priv->clk = devm_clk_get(dev, NULL);
  498. if (IS_ERR(priv->clk))
  499. return PTR_ERR(priv->clk);
  500. priv->params = of_device_get_match_data(&pdev->dev);
  501. imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
  502. imx_ocotp_nvmem_config.dev = dev;
  503. imx_ocotp_nvmem_config.priv = priv;
  504. priv->config = &imx_ocotp_nvmem_config;
  505. clk_prepare_enable(priv->clk);
  506. imx_ocotp_clr_err_if_set(priv);
  507. clk_disable_unprepare(priv->clk);
  508. nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
  509. return PTR_ERR_OR_ZERO(nvmem);
  510. }
  511. static struct platform_driver imx_ocotp_driver = {
  512. .probe = imx_ocotp_probe,
  513. .driver = {
  514. .name = "imx_ocotp",
  515. .of_match_table = imx_ocotp_dt_ids,
  516. },
  517. };
  518. module_platform_driver(imx_ocotp_driver);
  519. MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
  520. MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
  521. MODULE_LICENSE("GPL v2");