bcm-ocotp.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2016 Broadcom
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/acpi.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/nvmem-provider.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. /*
  23. * # of tries for OTP Status. The time to execute a command varies. The slowest
  24. * commands are writes which also vary based on the # of bits turned on. Writing
  25. * 0xffffffff takes ~3800 us.
  26. */
  27. #define OTPC_RETRIES 5000
  28. /* Sequence to enable OTP program */
  29. #define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
  30. /* OTPC Commands */
  31. #define OTPC_CMD_READ 0x0
  32. #define OTPC_CMD_OTP_PROG_ENABLE 0x2
  33. #define OTPC_CMD_OTP_PROG_DISABLE 0x3
  34. #define OTPC_CMD_PROGRAM 0x8
  35. /* OTPC Status Bits */
  36. #define OTPC_STAT_CMD_DONE BIT(1)
  37. #define OTPC_STAT_PROG_OK BIT(2)
  38. /* OTPC register definition */
  39. #define OTPC_MODE_REG_OFFSET 0x0
  40. #define OTPC_MODE_REG_OTPC_MODE 0
  41. #define OTPC_COMMAND_OFFSET 0x4
  42. #define OTPC_COMMAND_COMMAND_WIDTH 6
  43. #define OTPC_CMD_START_OFFSET 0x8
  44. #define OTPC_CMD_START_START 0
  45. #define OTPC_CPU_STATUS_OFFSET 0xc
  46. #define OTPC_CPUADDR_REG_OFFSET 0x28
  47. #define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
  48. #define OTPC_CPU_WRITE_REG_OFFSET 0x2c
  49. #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
  50. #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
  51. struct otpc_map {
  52. /* in words. */
  53. u32 otpc_row_size;
  54. /* 128 bit row / 4 words support. */
  55. u16 data_r_offset[4];
  56. /* 128 bit row / 4 words support. */
  57. u16 data_w_offset[4];
  58. };
  59. static struct otpc_map otp_map = {
  60. .otpc_row_size = 1,
  61. .data_r_offset = {0x10},
  62. .data_w_offset = {0x2c},
  63. };
  64. static struct otpc_map otp_map_v2 = {
  65. .otpc_row_size = 2,
  66. .data_r_offset = {0x10, 0x5c},
  67. .data_w_offset = {0x2c, 0x64},
  68. };
  69. struct otpc_priv {
  70. struct device *dev;
  71. void __iomem *base;
  72. const struct otpc_map *map;
  73. struct nvmem_config *config;
  74. };
  75. static inline void set_command(void __iomem *base, u32 command)
  76. {
  77. writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
  78. }
  79. static inline void set_cpu_address(void __iomem *base, u32 addr)
  80. {
  81. writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
  82. }
  83. static inline void set_start_bit(void __iomem *base)
  84. {
  85. writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
  86. }
  87. static inline void reset_start_bit(void __iomem *base)
  88. {
  89. writel(0, base + OTPC_CMD_START_OFFSET);
  90. }
  91. static inline void write_cpu_data(void __iomem *base, u32 value)
  92. {
  93. writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
  94. }
  95. static int poll_cpu_status(void __iomem *base, u32 value)
  96. {
  97. u32 status;
  98. u32 retries;
  99. for (retries = 0; retries < OTPC_RETRIES; retries++) {
  100. status = readl(base + OTPC_CPU_STATUS_OFFSET);
  101. if (status & value)
  102. break;
  103. udelay(1);
  104. }
  105. if (retries == OTPC_RETRIES)
  106. return -EAGAIN;
  107. return 0;
  108. }
  109. static int enable_ocotp_program(void __iomem *base)
  110. {
  111. static const u32 vals[] = OTPC_PROG_EN_SEQ;
  112. int i;
  113. int ret;
  114. /* Write the magic sequence to enable programming */
  115. set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
  116. for (i = 0; i < ARRAY_SIZE(vals); i++) {
  117. write_cpu_data(base, vals[i]);
  118. set_start_bit(base);
  119. ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
  120. reset_start_bit(base);
  121. if (ret)
  122. return ret;
  123. }
  124. return poll_cpu_status(base, OTPC_STAT_PROG_OK);
  125. }
  126. static int disable_ocotp_program(void __iomem *base)
  127. {
  128. int ret;
  129. set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
  130. set_start_bit(base);
  131. ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
  132. reset_start_bit(base);
  133. return ret;
  134. }
  135. static int bcm_otpc_read(void *context, unsigned int offset, void *val,
  136. size_t bytes)
  137. {
  138. struct otpc_priv *priv = context;
  139. u32 *buf = val;
  140. u32 bytes_read;
  141. u32 address = offset / priv->config->word_size;
  142. int i, ret;
  143. for (bytes_read = 0; bytes_read < bytes;) {
  144. set_command(priv->base, OTPC_CMD_READ);
  145. set_cpu_address(priv->base, address++);
  146. set_start_bit(priv->base);
  147. ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
  148. if (ret) {
  149. dev_err(priv->dev, "otp read error: 0x%x", ret);
  150. return -EIO;
  151. }
  152. for (i = 0; i < priv->map->otpc_row_size; i++) {
  153. *buf++ = readl(priv->base +
  154. priv->map->data_r_offset[i]);
  155. bytes_read += sizeof(*buf);
  156. }
  157. reset_start_bit(priv->base);
  158. }
  159. return 0;
  160. }
  161. static int bcm_otpc_write(void *context, unsigned int offset, void *val,
  162. size_t bytes)
  163. {
  164. struct otpc_priv *priv = context;
  165. u32 *buf = val;
  166. u32 bytes_written;
  167. u32 address = offset / priv->config->word_size;
  168. int i, ret;
  169. if (offset % priv->config->word_size)
  170. return -EINVAL;
  171. ret = enable_ocotp_program(priv->base);
  172. if (ret)
  173. return -EIO;
  174. for (bytes_written = 0; bytes_written < bytes;) {
  175. set_command(priv->base, OTPC_CMD_PROGRAM);
  176. set_cpu_address(priv->base, address++);
  177. for (i = 0; i < priv->map->otpc_row_size; i++) {
  178. writel(*buf, priv->base + priv->map->data_w_offset[i]);
  179. buf++;
  180. bytes_written += sizeof(*buf);
  181. }
  182. set_start_bit(priv->base);
  183. ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
  184. reset_start_bit(priv->base);
  185. if (ret) {
  186. dev_err(priv->dev, "otp write error: 0x%x", ret);
  187. return -EIO;
  188. }
  189. }
  190. disable_ocotp_program(priv->base);
  191. return 0;
  192. }
  193. static struct nvmem_config bcm_otpc_nvmem_config = {
  194. .name = "bcm-ocotp",
  195. .read_only = false,
  196. .word_size = 4,
  197. .stride = 4,
  198. .reg_read = bcm_otpc_read,
  199. .reg_write = bcm_otpc_write,
  200. };
  201. static const struct of_device_id bcm_otpc_dt_ids[] = {
  202. { .compatible = "brcm,ocotp", .data = &otp_map },
  203. { .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
  204. { },
  205. };
  206. MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
  207. static const struct acpi_device_id bcm_otpc_acpi_ids[] = {
  208. { .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
  209. { .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
  210. { /* sentinel */ }
  211. };
  212. MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
  213. static int bcm_otpc_probe(struct platform_device *pdev)
  214. {
  215. struct device *dev = &pdev->dev;
  216. struct resource *res;
  217. struct otpc_priv *priv;
  218. struct nvmem_device *nvmem;
  219. int err;
  220. u32 num_words;
  221. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  222. if (!priv)
  223. return -ENOMEM;
  224. priv->map = device_get_match_data(dev);
  225. if (!priv->map)
  226. return -ENODEV;
  227. /* Get OTP base address register. */
  228. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  229. priv->base = devm_ioremap_resource(dev, res);
  230. if (IS_ERR(priv->base)) {
  231. dev_err(dev, "unable to map I/O memory\n");
  232. return PTR_ERR(priv->base);
  233. }
  234. /* Enable CPU access to OTPC. */
  235. writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
  236. BIT(OTPC_MODE_REG_OTPC_MODE),
  237. priv->base + OTPC_MODE_REG_OFFSET);
  238. reset_start_bit(priv->base);
  239. /* Read size of memory in words. */
  240. err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
  241. if (err) {
  242. dev_err(dev, "size parameter not specified\n");
  243. return -EINVAL;
  244. } else if (num_words == 0) {
  245. dev_err(dev, "size must be > 0\n");
  246. return -EINVAL;
  247. }
  248. bcm_otpc_nvmem_config.size = 4 * num_words;
  249. bcm_otpc_nvmem_config.dev = dev;
  250. bcm_otpc_nvmem_config.priv = priv;
  251. if (priv->map == &otp_map_v2) {
  252. bcm_otpc_nvmem_config.word_size = 8;
  253. bcm_otpc_nvmem_config.stride = 8;
  254. }
  255. priv->config = &bcm_otpc_nvmem_config;
  256. nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
  257. if (IS_ERR(nvmem)) {
  258. dev_err(dev, "error registering nvmem config\n");
  259. return PTR_ERR(nvmem);
  260. }
  261. return 0;
  262. }
  263. static struct platform_driver bcm_otpc_driver = {
  264. .probe = bcm_otpc_probe,
  265. .driver = {
  266. .name = "brcm-otpc",
  267. .of_match_table = bcm_otpc_dt_ids,
  268. .acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
  269. },
  270. };
  271. module_platform_driver(bcm_otpc_driver);
  272. MODULE_DESCRIPTION("Broadcom OTPC driver");
  273. MODULE_LICENSE("GPL v2");