region_devs.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
  4. */
  5. #include <linux/scatterlist.h>
  6. #include <linux/memregion.h>
  7. #include <linux/highmem.h>
  8. #include <linux/sched.h>
  9. #include <linux/slab.h>
  10. #include <linux/hash.h>
  11. #include <linux/sort.h>
  12. #include <linux/io.h>
  13. #include <linux/nd.h>
  14. #include "nd-core.h"
  15. #include "nd.h"
  16. /*
  17. * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is
  18. * irrelevant.
  19. */
  20. #include <linux/io-64-nonatomic-hi-lo.h>
  21. static DEFINE_PER_CPU(int, flush_idx);
  22. static int nvdimm_map_flush(struct device *dev, struct nvdimm *nvdimm, int dimm,
  23. struct nd_region_data *ndrd)
  24. {
  25. int i, j;
  26. dev_dbg(dev, "%s: map %d flush address%s\n", nvdimm_name(nvdimm),
  27. nvdimm->num_flush, nvdimm->num_flush == 1 ? "" : "es");
  28. for (i = 0; i < (1 << ndrd->hints_shift); i++) {
  29. struct resource *res = &nvdimm->flush_wpq[i];
  30. unsigned long pfn = PHYS_PFN(res->start);
  31. void __iomem *flush_page;
  32. /* check if flush hints share a page */
  33. for (j = 0; j < i; j++) {
  34. struct resource *res_j = &nvdimm->flush_wpq[j];
  35. unsigned long pfn_j = PHYS_PFN(res_j->start);
  36. if (pfn == pfn_j)
  37. break;
  38. }
  39. if (j < i)
  40. flush_page = (void __iomem *) ((unsigned long)
  41. ndrd_get_flush_wpq(ndrd, dimm, j)
  42. & PAGE_MASK);
  43. else
  44. flush_page = devm_nvdimm_ioremap(dev,
  45. PFN_PHYS(pfn), PAGE_SIZE);
  46. if (!flush_page)
  47. return -ENXIO;
  48. ndrd_set_flush_wpq(ndrd, dimm, i, flush_page
  49. + (res->start & ~PAGE_MASK));
  50. }
  51. return 0;
  52. }
  53. int nd_region_activate(struct nd_region *nd_region)
  54. {
  55. int i, j, num_flush = 0;
  56. struct nd_region_data *ndrd;
  57. struct device *dev = &nd_region->dev;
  58. size_t flush_data_size = sizeof(void *);
  59. nvdimm_bus_lock(&nd_region->dev);
  60. for (i = 0; i < nd_region->ndr_mappings; i++) {
  61. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  62. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  63. if (test_bit(NDD_SECURITY_OVERWRITE, &nvdimm->flags)) {
  64. nvdimm_bus_unlock(&nd_region->dev);
  65. return -EBUSY;
  66. }
  67. /* at least one null hint slot per-dimm for the "no-hint" case */
  68. flush_data_size += sizeof(void *);
  69. num_flush = min_not_zero(num_flush, nvdimm->num_flush);
  70. if (!nvdimm->num_flush)
  71. continue;
  72. flush_data_size += nvdimm->num_flush * sizeof(void *);
  73. }
  74. nvdimm_bus_unlock(&nd_region->dev);
  75. ndrd = devm_kzalloc(dev, sizeof(*ndrd) + flush_data_size, GFP_KERNEL);
  76. if (!ndrd)
  77. return -ENOMEM;
  78. dev_set_drvdata(dev, ndrd);
  79. if (!num_flush)
  80. return 0;
  81. ndrd->hints_shift = ilog2(num_flush);
  82. for (i = 0; i < nd_region->ndr_mappings; i++) {
  83. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  84. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  85. int rc = nvdimm_map_flush(&nd_region->dev, nvdimm, i, ndrd);
  86. if (rc)
  87. return rc;
  88. }
  89. /*
  90. * Clear out entries that are duplicates. This should prevent the
  91. * extra flushings.
  92. */
  93. for (i = 0; i < nd_region->ndr_mappings - 1; i++) {
  94. /* ignore if NULL already */
  95. if (!ndrd_get_flush_wpq(ndrd, i, 0))
  96. continue;
  97. for (j = i + 1; j < nd_region->ndr_mappings; j++)
  98. if (ndrd_get_flush_wpq(ndrd, i, 0) ==
  99. ndrd_get_flush_wpq(ndrd, j, 0))
  100. ndrd_set_flush_wpq(ndrd, j, 0, NULL);
  101. }
  102. return 0;
  103. }
  104. static void nd_region_release(struct device *dev)
  105. {
  106. struct nd_region *nd_region = to_nd_region(dev);
  107. u16 i;
  108. for (i = 0; i < nd_region->ndr_mappings; i++) {
  109. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  110. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  111. put_device(&nvdimm->dev);
  112. }
  113. free_percpu(nd_region->lane);
  114. memregion_free(nd_region->id);
  115. if (is_nd_blk(dev))
  116. kfree(to_nd_blk_region(dev));
  117. else
  118. kfree(nd_region);
  119. }
  120. struct nd_region *to_nd_region(struct device *dev)
  121. {
  122. struct nd_region *nd_region = container_of(dev, struct nd_region, dev);
  123. WARN_ON(dev->type->release != nd_region_release);
  124. return nd_region;
  125. }
  126. EXPORT_SYMBOL_GPL(to_nd_region);
  127. struct device *nd_region_dev(struct nd_region *nd_region)
  128. {
  129. if (!nd_region)
  130. return NULL;
  131. return &nd_region->dev;
  132. }
  133. EXPORT_SYMBOL_GPL(nd_region_dev);
  134. struct nd_blk_region *to_nd_blk_region(struct device *dev)
  135. {
  136. struct nd_region *nd_region = to_nd_region(dev);
  137. WARN_ON(!is_nd_blk(dev));
  138. return container_of(nd_region, struct nd_blk_region, nd_region);
  139. }
  140. EXPORT_SYMBOL_GPL(to_nd_blk_region);
  141. void *nd_region_provider_data(struct nd_region *nd_region)
  142. {
  143. return nd_region->provider_data;
  144. }
  145. EXPORT_SYMBOL_GPL(nd_region_provider_data);
  146. void *nd_blk_region_provider_data(struct nd_blk_region *ndbr)
  147. {
  148. return ndbr->blk_provider_data;
  149. }
  150. EXPORT_SYMBOL_GPL(nd_blk_region_provider_data);
  151. void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data)
  152. {
  153. ndbr->blk_provider_data = data;
  154. }
  155. EXPORT_SYMBOL_GPL(nd_blk_region_set_provider_data);
  156. /**
  157. * nd_region_to_nstype() - region to an integer namespace type
  158. * @nd_region: region-device to interrogate
  159. *
  160. * This is the 'nstype' attribute of a region as well, an input to the
  161. * MODALIAS for namespace devices, and bit number for a nvdimm_bus to match
  162. * namespace devices with namespace drivers.
  163. */
  164. int nd_region_to_nstype(struct nd_region *nd_region)
  165. {
  166. if (is_memory(&nd_region->dev)) {
  167. u16 i, label;
  168. for (i = 0, label = 0; i < nd_region->ndr_mappings; i++) {
  169. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  170. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  171. if (test_bit(NDD_LABELING, &nvdimm->flags))
  172. label++;
  173. }
  174. if (label)
  175. return ND_DEVICE_NAMESPACE_PMEM;
  176. else
  177. return ND_DEVICE_NAMESPACE_IO;
  178. } else if (is_nd_blk(&nd_region->dev)) {
  179. return ND_DEVICE_NAMESPACE_BLK;
  180. }
  181. return 0;
  182. }
  183. EXPORT_SYMBOL(nd_region_to_nstype);
  184. static unsigned long long region_size(struct nd_region *nd_region)
  185. {
  186. if (is_memory(&nd_region->dev)) {
  187. return nd_region->ndr_size;
  188. } else if (nd_region->ndr_mappings == 1) {
  189. struct nd_mapping *nd_mapping = &nd_region->mapping[0];
  190. return nd_mapping->size;
  191. }
  192. return 0;
  193. }
  194. static ssize_t size_show(struct device *dev,
  195. struct device_attribute *attr, char *buf)
  196. {
  197. struct nd_region *nd_region = to_nd_region(dev);
  198. return sprintf(buf, "%llu\n", region_size(nd_region));
  199. }
  200. static DEVICE_ATTR_RO(size);
  201. static ssize_t deep_flush_show(struct device *dev,
  202. struct device_attribute *attr, char *buf)
  203. {
  204. struct nd_region *nd_region = to_nd_region(dev);
  205. /*
  206. * NOTE: in the nvdimm_has_flush() error case this attribute is
  207. * not visible.
  208. */
  209. return sprintf(buf, "%d\n", nvdimm_has_flush(nd_region));
  210. }
  211. static ssize_t deep_flush_store(struct device *dev, struct device_attribute *attr,
  212. const char *buf, size_t len)
  213. {
  214. bool flush;
  215. int rc = strtobool(buf, &flush);
  216. struct nd_region *nd_region = to_nd_region(dev);
  217. if (rc)
  218. return rc;
  219. if (!flush)
  220. return -EINVAL;
  221. rc = nvdimm_flush(nd_region, NULL);
  222. if (rc)
  223. return rc;
  224. return len;
  225. }
  226. static DEVICE_ATTR_RW(deep_flush);
  227. static ssize_t mappings_show(struct device *dev,
  228. struct device_attribute *attr, char *buf)
  229. {
  230. struct nd_region *nd_region = to_nd_region(dev);
  231. return sprintf(buf, "%d\n", nd_region->ndr_mappings);
  232. }
  233. static DEVICE_ATTR_RO(mappings);
  234. static ssize_t nstype_show(struct device *dev,
  235. struct device_attribute *attr, char *buf)
  236. {
  237. struct nd_region *nd_region = to_nd_region(dev);
  238. return sprintf(buf, "%d\n", nd_region_to_nstype(nd_region));
  239. }
  240. static DEVICE_ATTR_RO(nstype);
  241. static ssize_t set_cookie_show(struct device *dev,
  242. struct device_attribute *attr, char *buf)
  243. {
  244. struct nd_region *nd_region = to_nd_region(dev);
  245. struct nd_interleave_set *nd_set = nd_region->nd_set;
  246. ssize_t rc = 0;
  247. if (is_memory(dev) && nd_set)
  248. /* pass, should be precluded by region_visible */;
  249. else
  250. return -ENXIO;
  251. /*
  252. * The cookie to show depends on which specification of the
  253. * labels we are using. If there are not labels then default to
  254. * the v1.1 namespace label cookie definition. To read all this
  255. * data we need to wait for probing to settle.
  256. */
  257. nd_device_lock(dev);
  258. nvdimm_bus_lock(dev);
  259. wait_nvdimm_bus_probe_idle(dev);
  260. if (nd_region->ndr_mappings) {
  261. struct nd_mapping *nd_mapping = &nd_region->mapping[0];
  262. struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
  263. if (ndd) {
  264. struct nd_namespace_index *nsindex;
  265. nsindex = to_namespace_index(ndd, ndd->ns_current);
  266. rc = sprintf(buf, "%#llx\n",
  267. nd_region_interleave_set_cookie(nd_region,
  268. nsindex));
  269. }
  270. }
  271. nvdimm_bus_unlock(dev);
  272. nd_device_unlock(dev);
  273. if (rc)
  274. return rc;
  275. return sprintf(buf, "%#llx\n", nd_set->cookie1);
  276. }
  277. static DEVICE_ATTR_RO(set_cookie);
  278. resource_size_t nd_region_available_dpa(struct nd_region *nd_region)
  279. {
  280. resource_size_t blk_max_overlap = 0, available, overlap;
  281. int i;
  282. WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev));
  283. retry:
  284. available = 0;
  285. overlap = blk_max_overlap;
  286. for (i = 0; i < nd_region->ndr_mappings; i++) {
  287. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  288. struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
  289. /* if a dimm is disabled the available capacity is zero */
  290. if (!ndd)
  291. return 0;
  292. if (is_memory(&nd_region->dev)) {
  293. available += nd_pmem_available_dpa(nd_region,
  294. nd_mapping, &overlap);
  295. if (overlap > blk_max_overlap) {
  296. blk_max_overlap = overlap;
  297. goto retry;
  298. }
  299. } else if (is_nd_blk(&nd_region->dev))
  300. available += nd_blk_available_dpa(nd_region);
  301. }
  302. return available;
  303. }
  304. resource_size_t nd_region_allocatable_dpa(struct nd_region *nd_region)
  305. {
  306. resource_size_t available = 0;
  307. int i;
  308. if (is_memory(&nd_region->dev))
  309. available = PHYS_ADDR_MAX;
  310. WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev));
  311. for (i = 0; i < nd_region->ndr_mappings; i++) {
  312. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  313. if (is_memory(&nd_region->dev))
  314. available = min(available,
  315. nd_pmem_max_contiguous_dpa(nd_region,
  316. nd_mapping));
  317. else if (is_nd_blk(&nd_region->dev))
  318. available += nd_blk_available_dpa(nd_region);
  319. }
  320. if (is_memory(&nd_region->dev))
  321. return available * nd_region->ndr_mappings;
  322. return available;
  323. }
  324. static ssize_t available_size_show(struct device *dev,
  325. struct device_attribute *attr, char *buf)
  326. {
  327. struct nd_region *nd_region = to_nd_region(dev);
  328. unsigned long long available = 0;
  329. /*
  330. * Flush in-flight updates and grab a snapshot of the available
  331. * size. Of course, this value is potentially invalidated the
  332. * memory nvdimm_bus_lock() is dropped, but that's userspace's
  333. * problem to not race itself.
  334. */
  335. nd_device_lock(dev);
  336. nvdimm_bus_lock(dev);
  337. wait_nvdimm_bus_probe_idle(dev);
  338. available = nd_region_available_dpa(nd_region);
  339. nvdimm_bus_unlock(dev);
  340. nd_device_unlock(dev);
  341. return sprintf(buf, "%llu\n", available);
  342. }
  343. static DEVICE_ATTR_RO(available_size);
  344. static ssize_t max_available_extent_show(struct device *dev,
  345. struct device_attribute *attr, char *buf)
  346. {
  347. struct nd_region *nd_region = to_nd_region(dev);
  348. unsigned long long available = 0;
  349. nd_device_lock(dev);
  350. nvdimm_bus_lock(dev);
  351. wait_nvdimm_bus_probe_idle(dev);
  352. available = nd_region_allocatable_dpa(nd_region);
  353. nvdimm_bus_unlock(dev);
  354. nd_device_unlock(dev);
  355. return sprintf(buf, "%llu\n", available);
  356. }
  357. static DEVICE_ATTR_RO(max_available_extent);
  358. static ssize_t init_namespaces_show(struct device *dev,
  359. struct device_attribute *attr, char *buf)
  360. {
  361. struct nd_region_data *ndrd = dev_get_drvdata(dev);
  362. ssize_t rc;
  363. nvdimm_bus_lock(dev);
  364. if (ndrd)
  365. rc = sprintf(buf, "%d/%d\n", ndrd->ns_active, ndrd->ns_count);
  366. else
  367. rc = -ENXIO;
  368. nvdimm_bus_unlock(dev);
  369. return rc;
  370. }
  371. static DEVICE_ATTR_RO(init_namespaces);
  372. static ssize_t namespace_seed_show(struct device *dev,
  373. struct device_attribute *attr, char *buf)
  374. {
  375. struct nd_region *nd_region = to_nd_region(dev);
  376. ssize_t rc;
  377. nvdimm_bus_lock(dev);
  378. if (nd_region->ns_seed)
  379. rc = sprintf(buf, "%s\n", dev_name(nd_region->ns_seed));
  380. else
  381. rc = sprintf(buf, "\n");
  382. nvdimm_bus_unlock(dev);
  383. return rc;
  384. }
  385. static DEVICE_ATTR_RO(namespace_seed);
  386. static ssize_t btt_seed_show(struct device *dev,
  387. struct device_attribute *attr, char *buf)
  388. {
  389. struct nd_region *nd_region = to_nd_region(dev);
  390. ssize_t rc;
  391. nvdimm_bus_lock(dev);
  392. if (nd_region->btt_seed)
  393. rc = sprintf(buf, "%s\n", dev_name(nd_region->btt_seed));
  394. else
  395. rc = sprintf(buf, "\n");
  396. nvdimm_bus_unlock(dev);
  397. return rc;
  398. }
  399. static DEVICE_ATTR_RO(btt_seed);
  400. static ssize_t pfn_seed_show(struct device *dev,
  401. struct device_attribute *attr, char *buf)
  402. {
  403. struct nd_region *nd_region = to_nd_region(dev);
  404. ssize_t rc;
  405. nvdimm_bus_lock(dev);
  406. if (nd_region->pfn_seed)
  407. rc = sprintf(buf, "%s\n", dev_name(nd_region->pfn_seed));
  408. else
  409. rc = sprintf(buf, "\n");
  410. nvdimm_bus_unlock(dev);
  411. return rc;
  412. }
  413. static DEVICE_ATTR_RO(pfn_seed);
  414. static ssize_t dax_seed_show(struct device *dev,
  415. struct device_attribute *attr, char *buf)
  416. {
  417. struct nd_region *nd_region = to_nd_region(dev);
  418. ssize_t rc;
  419. nvdimm_bus_lock(dev);
  420. if (nd_region->dax_seed)
  421. rc = sprintf(buf, "%s\n", dev_name(nd_region->dax_seed));
  422. else
  423. rc = sprintf(buf, "\n");
  424. nvdimm_bus_unlock(dev);
  425. return rc;
  426. }
  427. static DEVICE_ATTR_RO(dax_seed);
  428. static ssize_t read_only_show(struct device *dev,
  429. struct device_attribute *attr, char *buf)
  430. {
  431. struct nd_region *nd_region = to_nd_region(dev);
  432. return sprintf(buf, "%d\n", nd_region->ro);
  433. }
  434. static ssize_t read_only_store(struct device *dev,
  435. struct device_attribute *attr, const char *buf, size_t len)
  436. {
  437. bool ro;
  438. int rc = strtobool(buf, &ro);
  439. struct nd_region *nd_region = to_nd_region(dev);
  440. if (rc)
  441. return rc;
  442. nd_region->ro = ro;
  443. return len;
  444. }
  445. static DEVICE_ATTR_RW(read_only);
  446. static ssize_t align_show(struct device *dev,
  447. struct device_attribute *attr, char *buf)
  448. {
  449. struct nd_region *nd_region = to_nd_region(dev);
  450. return sprintf(buf, "%#lx\n", nd_region->align);
  451. }
  452. static ssize_t align_store(struct device *dev,
  453. struct device_attribute *attr, const char *buf, size_t len)
  454. {
  455. struct nd_region *nd_region = to_nd_region(dev);
  456. unsigned long val, dpa;
  457. u32 remainder;
  458. int rc;
  459. rc = kstrtoul(buf, 0, &val);
  460. if (rc)
  461. return rc;
  462. if (!nd_region->ndr_mappings)
  463. return -ENXIO;
  464. /*
  465. * Ensure space-align is evenly divisible by the region
  466. * interleave-width because the kernel typically has no facility
  467. * to determine which DIMM(s), dimm-physical-addresses, would
  468. * contribute to the tail capacity in system-physical-address
  469. * space for the namespace.
  470. */
  471. dpa = div_u64_rem(val, nd_region->ndr_mappings, &remainder);
  472. if (!is_power_of_2(dpa) || dpa < PAGE_SIZE
  473. || val > region_size(nd_region) || remainder)
  474. return -EINVAL;
  475. /*
  476. * Given that space allocation consults this value multiple
  477. * times ensure it does not change for the duration of the
  478. * allocation.
  479. */
  480. nvdimm_bus_lock(dev);
  481. nd_region->align = val;
  482. nvdimm_bus_unlock(dev);
  483. return len;
  484. }
  485. static DEVICE_ATTR_RW(align);
  486. static ssize_t region_badblocks_show(struct device *dev,
  487. struct device_attribute *attr, char *buf)
  488. {
  489. struct nd_region *nd_region = to_nd_region(dev);
  490. ssize_t rc;
  491. nd_device_lock(dev);
  492. if (dev->driver)
  493. rc = badblocks_show(&nd_region->bb, buf, 0);
  494. else
  495. rc = -ENXIO;
  496. nd_device_unlock(dev);
  497. return rc;
  498. }
  499. static DEVICE_ATTR(badblocks, 0444, region_badblocks_show, NULL);
  500. static ssize_t resource_show(struct device *dev,
  501. struct device_attribute *attr, char *buf)
  502. {
  503. struct nd_region *nd_region = to_nd_region(dev);
  504. return sprintf(buf, "%#llx\n", nd_region->ndr_start);
  505. }
  506. static DEVICE_ATTR_ADMIN_RO(resource);
  507. static ssize_t persistence_domain_show(struct device *dev,
  508. struct device_attribute *attr, char *buf)
  509. {
  510. struct nd_region *nd_region = to_nd_region(dev);
  511. if (test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags))
  512. return sprintf(buf, "cpu_cache\n");
  513. else if (test_bit(ND_REGION_PERSIST_MEMCTRL, &nd_region->flags))
  514. return sprintf(buf, "memory_controller\n");
  515. else
  516. return sprintf(buf, "\n");
  517. }
  518. static DEVICE_ATTR_RO(persistence_domain);
  519. static struct attribute *nd_region_attributes[] = {
  520. &dev_attr_size.attr,
  521. &dev_attr_align.attr,
  522. &dev_attr_nstype.attr,
  523. &dev_attr_mappings.attr,
  524. &dev_attr_btt_seed.attr,
  525. &dev_attr_pfn_seed.attr,
  526. &dev_attr_dax_seed.attr,
  527. &dev_attr_deep_flush.attr,
  528. &dev_attr_read_only.attr,
  529. &dev_attr_set_cookie.attr,
  530. &dev_attr_available_size.attr,
  531. &dev_attr_max_available_extent.attr,
  532. &dev_attr_namespace_seed.attr,
  533. &dev_attr_init_namespaces.attr,
  534. &dev_attr_badblocks.attr,
  535. &dev_attr_resource.attr,
  536. &dev_attr_persistence_domain.attr,
  537. NULL,
  538. };
  539. static umode_t region_visible(struct kobject *kobj, struct attribute *a, int n)
  540. {
  541. struct device *dev = container_of(kobj, typeof(*dev), kobj);
  542. struct nd_region *nd_region = to_nd_region(dev);
  543. struct nd_interleave_set *nd_set = nd_region->nd_set;
  544. int type = nd_region_to_nstype(nd_region);
  545. if (!is_memory(dev) && a == &dev_attr_pfn_seed.attr)
  546. return 0;
  547. if (!is_memory(dev) && a == &dev_attr_dax_seed.attr)
  548. return 0;
  549. if (!is_memory(dev) && a == &dev_attr_badblocks.attr)
  550. return 0;
  551. if (a == &dev_attr_resource.attr && !is_memory(dev))
  552. return 0;
  553. if (a == &dev_attr_deep_flush.attr) {
  554. int has_flush = nvdimm_has_flush(nd_region);
  555. if (has_flush == 1)
  556. return a->mode;
  557. else if (has_flush == 0)
  558. return 0444;
  559. else
  560. return 0;
  561. }
  562. if (a == &dev_attr_persistence_domain.attr) {
  563. if ((nd_region->flags & (BIT(ND_REGION_PERSIST_CACHE)
  564. | BIT(ND_REGION_PERSIST_MEMCTRL))) == 0)
  565. return 0;
  566. return a->mode;
  567. }
  568. if (a == &dev_attr_align.attr)
  569. return a->mode;
  570. if (a != &dev_attr_set_cookie.attr
  571. && a != &dev_attr_available_size.attr)
  572. return a->mode;
  573. if ((type == ND_DEVICE_NAMESPACE_PMEM
  574. || type == ND_DEVICE_NAMESPACE_BLK)
  575. && a == &dev_attr_available_size.attr)
  576. return a->mode;
  577. else if (is_memory(dev) && nd_set)
  578. return a->mode;
  579. return 0;
  580. }
  581. static ssize_t mappingN(struct device *dev, char *buf, int n)
  582. {
  583. struct nd_region *nd_region = to_nd_region(dev);
  584. struct nd_mapping *nd_mapping;
  585. struct nvdimm *nvdimm;
  586. if (n >= nd_region->ndr_mappings)
  587. return -ENXIO;
  588. nd_mapping = &nd_region->mapping[n];
  589. nvdimm = nd_mapping->nvdimm;
  590. return sprintf(buf, "%s,%llu,%llu,%d\n", dev_name(&nvdimm->dev),
  591. nd_mapping->start, nd_mapping->size,
  592. nd_mapping->position);
  593. }
  594. #define REGION_MAPPING(idx) \
  595. static ssize_t mapping##idx##_show(struct device *dev, \
  596. struct device_attribute *attr, char *buf) \
  597. { \
  598. return mappingN(dev, buf, idx); \
  599. } \
  600. static DEVICE_ATTR_RO(mapping##idx)
  601. /*
  602. * 32 should be enough for a while, even in the presence of socket
  603. * interleave a 32-way interleave set is a degenerate case.
  604. */
  605. REGION_MAPPING(0);
  606. REGION_MAPPING(1);
  607. REGION_MAPPING(2);
  608. REGION_MAPPING(3);
  609. REGION_MAPPING(4);
  610. REGION_MAPPING(5);
  611. REGION_MAPPING(6);
  612. REGION_MAPPING(7);
  613. REGION_MAPPING(8);
  614. REGION_MAPPING(9);
  615. REGION_MAPPING(10);
  616. REGION_MAPPING(11);
  617. REGION_MAPPING(12);
  618. REGION_MAPPING(13);
  619. REGION_MAPPING(14);
  620. REGION_MAPPING(15);
  621. REGION_MAPPING(16);
  622. REGION_MAPPING(17);
  623. REGION_MAPPING(18);
  624. REGION_MAPPING(19);
  625. REGION_MAPPING(20);
  626. REGION_MAPPING(21);
  627. REGION_MAPPING(22);
  628. REGION_MAPPING(23);
  629. REGION_MAPPING(24);
  630. REGION_MAPPING(25);
  631. REGION_MAPPING(26);
  632. REGION_MAPPING(27);
  633. REGION_MAPPING(28);
  634. REGION_MAPPING(29);
  635. REGION_MAPPING(30);
  636. REGION_MAPPING(31);
  637. static umode_t mapping_visible(struct kobject *kobj, struct attribute *a, int n)
  638. {
  639. struct device *dev = container_of(kobj, struct device, kobj);
  640. struct nd_region *nd_region = to_nd_region(dev);
  641. if (n < nd_region->ndr_mappings)
  642. return a->mode;
  643. return 0;
  644. }
  645. static struct attribute *mapping_attributes[] = {
  646. &dev_attr_mapping0.attr,
  647. &dev_attr_mapping1.attr,
  648. &dev_attr_mapping2.attr,
  649. &dev_attr_mapping3.attr,
  650. &dev_attr_mapping4.attr,
  651. &dev_attr_mapping5.attr,
  652. &dev_attr_mapping6.attr,
  653. &dev_attr_mapping7.attr,
  654. &dev_attr_mapping8.attr,
  655. &dev_attr_mapping9.attr,
  656. &dev_attr_mapping10.attr,
  657. &dev_attr_mapping11.attr,
  658. &dev_attr_mapping12.attr,
  659. &dev_attr_mapping13.attr,
  660. &dev_attr_mapping14.attr,
  661. &dev_attr_mapping15.attr,
  662. &dev_attr_mapping16.attr,
  663. &dev_attr_mapping17.attr,
  664. &dev_attr_mapping18.attr,
  665. &dev_attr_mapping19.attr,
  666. &dev_attr_mapping20.attr,
  667. &dev_attr_mapping21.attr,
  668. &dev_attr_mapping22.attr,
  669. &dev_attr_mapping23.attr,
  670. &dev_attr_mapping24.attr,
  671. &dev_attr_mapping25.attr,
  672. &dev_attr_mapping26.attr,
  673. &dev_attr_mapping27.attr,
  674. &dev_attr_mapping28.attr,
  675. &dev_attr_mapping29.attr,
  676. &dev_attr_mapping30.attr,
  677. &dev_attr_mapping31.attr,
  678. NULL,
  679. };
  680. static const struct attribute_group nd_mapping_attribute_group = {
  681. .is_visible = mapping_visible,
  682. .attrs = mapping_attributes,
  683. };
  684. static const struct attribute_group nd_region_attribute_group = {
  685. .attrs = nd_region_attributes,
  686. .is_visible = region_visible,
  687. };
  688. static const struct attribute_group *nd_region_attribute_groups[] = {
  689. &nd_device_attribute_group,
  690. &nd_region_attribute_group,
  691. &nd_numa_attribute_group,
  692. &nd_mapping_attribute_group,
  693. NULL,
  694. };
  695. static const struct device_type nd_blk_device_type = {
  696. .name = "nd_blk",
  697. .release = nd_region_release,
  698. .groups = nd_region_attribute_groups,
  699. };
  700. static const struct device_type nd_pmem_device_type = {
  701. .name = "nd_pmem",
  702. .release = nd_region_release,
  703. .groups = nd_region_attribute_groups,
  704. };
  705. static const struct device_type nd_volatile_device_type = {
  706. .name = "nd_volatile",
  707. .release = nd_region_release,
  708. .groups = nd_region_attribute_groups,
  709. };
  710. bool is_nd_pmem(struct device *dev)
  711. {
  712. return dev ? dev->type == &nd_pmem_device_type : false;
  713. }
  714. bool is_nd_blk(struct device *dev)
  715. {
  716. return dev ? dev->type == &nd_blk_device_type : false;
  717. }
  718. bool is_nd_volatile(struct device *dev)
  719. {
  720. return dev ? dev->type == &nd_volatile_device_type : false;
  721. }
  722. u64 nd_region_interleave_set_cookie(struct nd_region *nd_region,
  723. struct nd_namespace_index *nsindex)
  724. {
  725. struct nd_interleave_set *nd_set = nd_region->nd_set;
  726. if (!nd_set)
  727. return 0;
  728. if (nsindex && __le16_to_cpu(nsindex->major) == 1
  729. && __le16_to_cpu(nsindex->minor) == 1)
  730. return nd_set->cookie1;
  731. return nd_set->cookie2;
  732. }
  733. u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region)
  734. {
  735. struct nd_interleave_set *nd_set = nd_region->nd_set;
  736. if (nd_set)
  737. return nd_set->altcookie;
  738. return 0;
  739. }
  740. void nd_mapping_free_labels(struct nd_mapping *nd_mapping)
  741. {
  742. struct nd_label_ent *label_ent, *e;
  743. lockdep_assert_held(&nd_mapping->lock);
  744. list_for_each_entry_safe(label_ent, e, &nd_mapping->labels, list) {
  745. list_del(&label_ent->list);
  746. kfree(label_ent);
  747. }
  748. }
  749. /*
  750. * When a namespace is activated create new seeds for the next
  751. * namespace, or namespace-personality to be configured.
  752. */
  753. void nd_region_advance_seeds(struct nd_region *nd_region, struct device *dev)
  754. {
  755. nvdimm_bus_lock(dev);
  756. if (nd_region->ns_seed == dev) {
  757. nd_region_create_ns_seed(nd_region);
  758. } else if (is_nd_btt(dev)) {
  759. struct nd_btt *nd_btt = to_nd_btt(dev);
  760. if (nd_region->btt_seed == dev)
  761. nd_region_create_btt_seed(nd_region);
  762. if (nd_region->ns_seed == &nd_btt->ndns->dev)
  763. nd_region_create_ns_seed(nd_region);
  764. } else if (is_nd_pfn(dev)) {
  765. struct nd_pfn *nd_pfn = to_nd_pfn(dev);
  766. if (nd_region->pfn_seed == dev)
  767. nd_region_create_pfn_seed(nd_region);
  768. if (nd_region->ns_seed == &nd_pfn->ndns->dev)
  769. nd_region_create_ns_seed(nd_region);
  770. } else if (is_nd_dax(dev)) {
  771. struct nd_dax *nd_dax = to_nd_dax(dev);
  772. if (nd_region->dax_seed == dev)
  773. nd_region_create_dax_seed(nd_region);
  774. if (nd_region->ns_seed == &nd_dax->nd_pfn.ndns->dev)
  775. nd_region_create_ns_seed(nd_region);
  776. }
  777. nvdimm_bus_unlock(dev);
  778. }
  779. int nd_blk_region_init(struct nd_region *nd_region)
  780. {
  781. struct device *dev = &nd_region->dev;
  782. struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(dev);
  783. if (!is_nd_blk(dev))
  784. return 0;
  785. if (nd_region->ndr_mappings < 1) {
  786. dev_dbg(dev, "invalid BLK region\n");
  787. return -ENXIO;
  788. }
  789. return to_nd_blk_region(dev)->enable(nvdimm_bus, dev);
  790. }
  791. /**
  792. * nd_region_acquire_lane - allocate and lock a lane
  793. * @nd_region: region id and number of lanes possible
  794. *
  795. * A lane correlates to a BLK-data-window and/or a log slot in the BTT.
  796. * We optimize for the common case where there are 256 lanes, one
  797. * per-cpu. For larger systems we need to lock to share lanes. For now
  798. * this implementation assumes the cost of maintaining an allocator for
  799. * free lanes is on the order of the lock hold time, so it implements a
  800. * static lane = cpu % num_lanes mapping.
  801. *
  802. * In the case of a BTT instance on top of a BLK namespace a lane may be
  803. * acquired recursively. We lock on the first instance.
  804. *
  805. * In the case of a BTT instance on top of PMEM, we only acquire a lane
  806. * for the BTT metadata updates.
  807. */
  808. unsigned int nd_region_acquire_lane(struct nd_region *nd_region)
  809. {
  810. unsigned int cpu, lane;
  811. cpu = get_cpu();
  812. if (nd_region->num_lanes < nr_cpu_ids) {
  813. struct nd_percpu_lane *ndl_lock, *ndl_count;
  814. lane = cpu % nd_region->num_lanes;
  815. ndl_count = per_cpu_ptr(nd_region->lane, cpu);
  816. ndl_lock = per_cpu_ptr(nd_region->lane, lane);
  817. if (ndl_count->count++ == 0)
  818. spin_lock(&ndl_lock->lock);
  819. } else
  820. lane = cpu;
  821. return lane;
  822. }
  823. EXPORT_SYMBOL(nd_region_acquire_lane);
  824. void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane)
  825. {
  826. if (nd_region->num_lanes < nr_cpu_ids) {
  827. unsigned int cpu = get_cpu();
  828. struct nd_percpu_lane *ndl_lock, *ndl_count;
  829. ndl_count = per_cpu_ptr(nd_region->lane, cpu);
  830. ndl_lock = per_cpu_ptr(nd_region->lane, lane);
  831. if (--ndl_count->count == 0)
  832. spin_unlock(&ndl_lock->lock);
  833. put_cpu();
  834. }
  835. put_cpu();
  836. }
  837. EXPORT_SYMBOL(nd_region_release_lane);
  838. /*
  839. * PowerPC requires this alignment for memremap_pages(). All other archs
  840. * should be ok with SUBSECTION_SIZE (see memremap_compat_align()).
  841. */
  842. #define MEMREMAP_COMPAT_ALIGN_MAX SZ_16M
  843. static unsigned long default_align(struct nd_region *nd_region)
  844. {
  845. unsigned long align;
  846. int i, mappings;
  847. u32 remainder;
  848. if (is_nd_blk(&nd_region->dev))
  849. align = PAGE_SIZE;
  850. else
  851. align = MEMREMAP_COMPAT_ALIGN_MAX;
  852. for (i = 0; i < nd_region->ndr_mappings; i++) {
  853. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  854. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  855. if (test_bit(NDD_ALIASING, &nvdimm->flags)) {
  856. align = MEMREMAP_COMPAT_ALIGN_MAX;
  857. break;
  858. }
  859. }
  860. if (nd_region->ndr_size < MEMREMAP_COMPAT_ALIGN_MAX)
  861. align = PAGE_SIZE;
  862. mappings = max_t(u16, 1, nd_region->ndr_mappings);
  863. div_u64_rem(align, mappings, &remainder);
  864. if (remainder)
  865. align *= mappings;
  866. return align;
  867. }
  868. static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus,
  869. struct nd_region_desc *ndr_desc,
  870. const struct device_type *dev_type, const char *caller)
  871. {
  872. struct nd_region *nd_region;
  873. struct device *dev;
  874. void *region_buf;
  875. unsigned int i;
  876. int ro = 0;
  877. for (i = 0; i < ndr_desc->num_mappings; i++) {
  878. struct nd_mapping_desc *mapping = &ndr_desc->mapping[i];
  879. struct nvdimm *nvdimm = mapping->nvdimm;
  880. if ((mapping->start | mapping->size) % PAGE_SIZE) {
  881. dev_err(&nvdimm_bus->dev,
  882. "%s: %s mapping%d is not %ld aligned\n",
  883. caller, dev_name(&nvdimm->dev), i, PAGE_SIZE);
  884. return NULL;
  885. }
  886. if (test_bit(NDD_UNARMED, &nvdimm->flags))
  887. ro = 1;
  888. if (test_bit(NDD_NOBLK, &nvdimm->flags)
  889. && dev_type == &nd_blk_device_type) {
  890. dev_err(&nvdimm_bus->dev, "%s: %s mapping%d is not BLK capable\n",
  891. caller, dev_name(&nvdimm->dev), i);
  892. return NULL;
  893. }
  894. }
  895. if (dev_type == &nd_blk_device_type) {
  896. struct nd_blk_region_desc *ndbr_desc;
  897. struct nd_blk_region *ndbr;
  898. ndbr_desc = to_blk_region_desc(ndr_desc);
  899. ndbr = kzalloc(sizeof(*ndbr) + sizeof(struct nd_mapping)
  900. * ndr_desc->num_mappings,
  901. GFP_KERNEL);
  902. if (ndbr) {
  903. nd_region = &ndbr->nd_region;
  904. ndbr->enable = ndbr_desc->enable;
  905. ndbr->do_io = ndbr_desc->do_io;
  906. }
  907. region_buf = ndbr;
  908. } else {
  909. nd_region = kzalloc(struct_size(nd_region, mapping,
  910. ndr_desc->num_mappings),
  911. GFP_KERNEL);
  912. region_buf = nd_region;
  913. }
  914. if (!region_buf)
  915. return NULL;
  916. nd_region->id = memregion_alloc(GFP_KERNEL);
  917. if (nd_region->id < 0)
  918. goto err_id;
  919. nd_region->lane = alloc_percpu(struct nd_percpu_lane);
  920. if (!nd_region->lane)
  921. goto err_percpu;
  922. for (i = 0; i < nr_cpu_ids; i++) {
  923. struct nd_percpu_lane *ndl;
  924. ndl = per_cpu_ptr(nd_region->lane, i);
  925. spin_lock_init(&ndl->lock);
  926. ndl->count = 0;
  927. }
  928. for (i = 0; i < ndr_desc->num_mappings; i++) {
  929. struct nd_mapping_desc *mapping = &ndr_desc->mapping[i];
  930. struct nvdimm *nvdimm = mapping->nvdimm;
  931. nd_region->mapping[i].nvdimm = nvdimm;
  932. nd_region->mapping[i].start = mapping->start;
  933. nd_region->mapping[i].size = mapping->size;
  934. nd_region->mapping[i].position = mapping->position;
  935. INIT_LIST_HEAD(&nd_region->mapping[i].labels);
  936. mutex_init(&nd_region->mapping[i].lock);
  937. get_device(&nvdimm->dev);
  938. }
  939. nd_region->ndr_mappings = ndr_desc->num_mappings;
  940. nd_region->provider_data = ndr_desc->provider_data;
  941. nd_region->nd_set = ndr_desc->nd_set;
  942. nd_region->num_lanes = ndr_desc->num_lanes;
  943. nd_region->flags = ndr_desc->flags;
  944. nd_region->ro = ro;
  945. nd_region->numa_node = ndr_desc->numa_node;
  946. nd_region->target_node = ndr_desc->target_node;
  947. ida_init(&nd_region->ns_ida);
  948. ida_init(&nd_region->btt_ida);
  949. ida_init(&nd_region->pfn_ida);
  950. ida_init(&nd_region->dax_ida);
  951. dev = &nd_region->dev;
  952. dev_set_name(dev, "region%d", nd_region->id);
  953. dev->parent = &nvdimm_bus->dev;
  954. dev->type = dev_type;
  955. dev->groups = ndr_desc->attr_groups;
  956. dev->of_node = ndr_desc->of_node;
  957. nd_region->ndr_size = resource_size(ndr_desc->res);
  958. nd_region->ndr_start = ndr_desc->res->start;
  959. nd_region->align = default_align(nd_region);
  960. if (ndr_desc->flush)
  961. nd_region->flush = ndr_desc->flush;
  962. else
  963. nd_region->flush = NULL;
  964. nd_device_register(dev);
  965. return nd_region;
  966. err_percpu:
  967. memregion_free(nd_region->id);
  968. err_id:
  969. kfree(region_buf);
  970. return NULL;
  971. }
  972. struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus,
  973. struct nd_region_desc *ndr_desc)
  974. {
  975. ndr_desc->num_lanes = ND_MAX_LANES;
  976. return nd_region_create(nvdimm_bus, ndr_desc, &nd_pmem_device_type,
  977. __func__);
  978. }
  979. EXPORT_SYMBOL_GPL(nvdimm_pmem_region_create);
  980. struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus,
  981. struct nd_region_desc *ndr_desc)
  982. {
  983. if (ndr_desc->num_mappings > 1)
  984. return NULL;
  985. ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES);
  986. return nd_region_create(nvdimm_bus, ndr_desc, &nd_blk_device_type,
  987. __func__);
  988. }
  989. EXPORT_SYMBOL_GPL(nvdimm_blk_region_create);
  990. struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus,
  991. struct nd_region_desc *ndr_desc)
  992. {
  993. ndr_desc->num_lanes = ND_MAX_LANES;
  994. return nd_region_create(nvdimm_bus, ndr_desc, &nd_volatile_device_type,
  995. __func__);
  996. }
  997. EXPORT_SYMBOL_GPL(nvdimm_volatile_region_create);
  998. int nvdimm_flush(struct nd_region *nd_region, struct bio *bio)
  999. {
  1000. int rc = 0;
  1001. if (!nd_region->flush)
  1002. rc = generic_nvdimm_flush(nd_region);
  1003. else {
  1004. if (nd_region->flush(nd_region, bio))
  1005. rc = -EIO;
  1006. }
  1007. return rc;
  1008. }
  1009. /**
  1010. * nvdimm_flush - flush any posted write queues between the cpu and pmem media
  1011. * @nd_region: blk or interleaved pmem region
  1012. */
  1013. int generic_nvdimm_flush(struct nd_region *nd_region)
  1014. {
  1015. struct nd_region_data *ndrd = dev_get_drvdata(&nd_region->dev);
  1016. int i, idx;
  1017. /*
  1018. * Try to encourage some diversity in flush hint addresses
  1019. * across cpus assuming a limited number of flush hints.
  1020. */
  1021. idx = this_cpu_read(flush_idx);
  1022. idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8));
  1023. /*
  1024. * The pmem_wmb() is needed to 'sfence' all
  1025. * previous writes such that they are architecturally visible for
  1026. * the platform buffer flush. Note that we've already arranged for pmem
  1027. * writes to avoid the cache via memcpy_flushcache(). The final
  1028. * wmb() ensures ordering for the NVDIMM flush write.
  1029. */
  1030. pmem_wmb();
  1031. for (i = 0; i < nd_region->ndr_mappings; i++)
  1032. if (ndrd_get_flush_wpq(ndrd, i, 0))
  1033. writeq(1, ndrd_get_flush_wpq(ndrd, i, idx));
  1034. wmb();
  1035. return 0;
  1036. }
  1037. EXPORT_SYMBOL_GPL(nvdimm_flush);
  1038. /**
  1039. * nvdimm_has_flush - determine write flushing requirements
  1040. * @nd_region: blk or interleaved pmem region
  1041. *
  1042. * Returns 1 if writes require flushing
  1043. * Returns 0 if writes do not require flushing
  1044. * Returns -ENXIO if flushing capability can not be determined
  1045. */
  1046. int nvdimm_has_flush(struct nd_region *nd_region)
  1047. {
  1048. int i;
  1049. /* no nvdimm or pmem api == flushing capability unknown */
  1050. if (nd_region->ndr_mappings == 0
  1051. || !IS_ENABLED(CONFIG_ARCH_HAS_PMEM_API))
  1052. return -ENXIO;
  1053. /* Test if an explicit flush function is defined */
  1054. if (test_bit(ND_REGION_ASYNC, &nd_region->flags) && nd_region->flush)
  1055. return 1;
  1056. /* Test if any flush hints for the region are available */
  1057. for (i = 0; i < nd_region->ndr_mappings; i++) {
  1058. struct nd_mapping *nd_mapping = &nd_region->mapping[i];
  1059. struct nvdimm *nvdimm = nd_mapping->nvdimm;
  1060. /* flush hints present / available */
  1061. if (nvdimm->num_flush)
  1062. return 1;
  1063. }
  1064. /*
  1065. * The platform defines dimm devices without hints nor explicit flush,
  1066. * assume platform persistence mechanism like ADR
  1067. */
  1068. return 0;
  1069. }
  1070. EXPORT_SYMBOL_GPL(nvdimm_has_flush);
  1071. int nvdimm_has_cache(struct nd_region *nd_region)
  1072. {
  1073. return is_nd_pmem(&nd_region->dev) &&
  1074. !test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags);
  1075. }
  1076. EXPORT_SYMBOL_GPL(nvdimm_has_cache);
  1077. bool is_nvdimm_sync(struct nd_region *nd_region)
  1078. {
  1079. if (is_nd_volatile(&nd_region->dev))
  1080. return true;
  1081. return is_nd_pmem(&nd_region->dev) &&
  1082. !test_bit(ND_REGION_ASYNC, &nd_region->flags);
  1083. }
  1084. EXPORT_SYMBOL_GPL(is_nvdimm_sync);
  1085. struct conflict_context {
  1086. struct nd_region *nd_region;
  1087. resource_size_t start, size;
  1088. };
  1089. static int region_conflict(struct device *dev, void *data)
  1090. {
  1091. struct nd_region *nd_region;
  1092. struct conflict_context *ctx = data;
  1093. resource_size_t res_end, region_end, region_start;
  1094. if (!is_memory(dev))
  1095. return 0;
  1096. nd_region = to_nd_region(dev);
  1097. if (nd_region == ctx->nd_region)
  1098. return 0;
  1099. res_end = ctx->start + ctx->size;
  1100. region_start = nd_region->ndr_start;
  1101. region_end = region_start + nd_region->ndr_size;
  1102. if (ctx->start >= region_start && ctx->start < region_end)
  1103. return -EBUSY;
  1104. if (res_end > region_start && res_end <= region_end)
  1105. return -EBUSY;
  1106. return 0;
  1107. }
  1108. int nd_region_conflict(struct nd_region *nd_region, resource_size_t start,
  1109. resource_size_t size)
  1110. {
  1111. struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(&nd_region->dev);
  1112. struct conflict_context ctx = {
  1113. .nd_region = nd_region,
  1114. .start = start,
  1115. .size = size,
  1116. };
  1117. return device_for_each_child(&nvdimm_bus->dev, &ctx, region_conflict);
  1118. }