defxx.c 116 KB

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  1. /*
  2. * File Name:
  3. * defxx.c
  4. *
  5. * Copyright Information:
  6. * Copyright Digital Equipment Corporation 1996.
  7. *
  8. * This software may be used and distributed according to the terms of
  9. * the GNU General Public License, incorporated herein by reference.
  10. *
  11. * Abstract:
  12. * A Linux device driver supporting the Digital Equipment Corporation
  13. * FDDI TURBOchannel, EISA and PCI controller families. Supported
  14. * adapters include:
  15. *
  16. * DEC FDDIcontroller/TURBOchannel (DEFTA)
  17. * DEC FDDIcontroller/EISA (DEFEA)
  18. * DEC FDDIcontroller/PCI (DEFPA)
  19. *
  20. * The original author:
  21. * LVS Lawrence V. Stefani <lstefani@yahoo.com>
  22. *
  23. * Maintainers:
  24. * macro Maciej W. Rozycki <macro@linux-mips.org>
  25. *
  26. * Credits:
  27. * I'd like to thank Patricia Cross for helping me get started with
  28. * Linux, David Davies for a lot of help upgrading and configuring
  29. * my development system and for answering many OS and driver
  30. * development questions, and Alan Cox for recommendations and
  31. * integration help on getting FDDI support into Linux. LVS
  32. *
  33. * Driver Architecture:
  34. * The driver architecture is largely based on previous driver work
  35. * for other operating systems. The upper edge interface and
  36. * functions were largely taken from existing Linux device drivers
  37. * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
  38. * driver.
  39. *
  40. * Adapter Probe -
  41. * The driver scans for supported EISA adapters by reading the
  42. * SLOT ID register for each EISA slot and making a match
  43. * against the expected value.
  44. *
  45. * Bus-Specific Initialization -
  46. * This driver currently supports both EISA and PCI controller
  47. * families. While the custom DMA chip and FDDI logic is similar
  48. * or identical, the bus logic is very different. After
  49. * initialization, the only bus-specific differences is in how the
  50. * driver enables and disables interrupts. Other than that, the
  51. * run-time critical code behaves the same on both families.
  52. * It's important to note that both adapter families are configured
  53. * to I/O map, rather than memory map, the adapter registers.
  54. *
  55. * Driver Open/Close -
  56. * In the driver open routine, the driver ISR (interrupt service
  57. * routine) is registered and the adapter is brought to an
  58. * operational state. In the driver close routine, the opposite
  59. * occurs; the driver ISR is deregistered and the adapter is
  60. * brought to a safe, but closed state. Users may use consecutive
  61. * commands to bring the adapter up and down as in the following
  62. * example:
  63. * ifconfig fddi0 up
  64. * ifconfig fddi0 down
  65. * ifconfig fddi0 up
  66. *
  67. * Driver Shutdown -
  68. * Apparently, there is no shutdown or halt routine support under
  69. * Linux. This routine would be called during "reboot" or
  70. * "shutdown" to allow the driver to place the adapter in a safe
  71. * state before a warm reboot occurs. To be really safe, the user
  72. * should close the adapter before shutdown (eg. ifconfig fddi0 down)
  73. * to ensure that the adapter DMA engine is taken off-line. However,
  74. * the current driver code anticipates this problem and always issues
  75. * a soft reset of the adapter at the beginning of driver initialization.
  76. * A future driver enhancement in this area may occur in 2.1.X where
  77. * Alan indicated that a shutdown handler may be implemented.
  78. *
  79. * Interrupt Service Routine -
  80. * The driver supports shared interrupts, so the ISR is registered for
  81. * each board with the appropriate flag and the pointer to that board's
  82. * device structure. This provides the context during interrupt
  83. * processing to support shared interrupts and multiple boards.
  84. *
  85. * Interrupt enabling/disabling can occur at many levels. At the host
  86. * end, you can disable system interrupts, or disable interrupts at the
  87. * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
  88. * have a bus-logic chip interrupt enable/disable as well as a DMA
  89. * controller interrupt enable/disable.
  90. *
  91. * The driver currently enables and disables adapter interrupts at the
  92. * bus-logic chip and assumes that Linux will take care of clearing or
  93. * acknowledging any host-based interrupt chips.
  94. *
  95. * Control Functions -
  96. * Control functions are those used to support functions such as adding
  97. * or deleting multicast addresses, enabling or disabling packet
  98. * reception filters, or other custom/proprietary commands. Presently,
  99. * the driver supports the "get statistics", "set multicast list", and
  100. * "set mac address" functions defined by Linux. A list of possible
  101. * enhancements include:
  102. *
  103. * - Custom ioctl interface for executing port interface commands
  104. * - Custom ioctl interface for adding unicast addresses to
  105. * adapter CAM (to support bridge functions).
  106. * - Custom ioctl interface for supporting firmware upgrades.
  107. *
  108. * Hardware (port interface) Support Routines -
  109. * The driver function names that start with "dfx_hw_" represent
  110. * low-level port interface routines that are called frequently. They
  111. * include issuing a DMA or port control command to the adapter,
  112. * resetting the adapter, or reading the adapter state. Since the
  113. * driver initialization and run-time code must make calls into the
  114. * port interface, these routines were written to be as generic and
  115. * usable as possible.
  116. *
  117. * Receive Path -
  118. * The adapter DMA engine supports a 256 entry receive descriptor block
  119. * of which up to 255 entries can be used at any given time. The
  120. * architecture is a standard producer, consumer, completion model in
  121. * which the driver "produces" receive buffers to the adapter, the
  122. * adapter "consumes" the receive buffers by DMAing incoming packet data,
  123. * and the driver "completes" the receive buffers by servicing the
  124. * incoming packet, then "produces" a new buffer and starts the cycle
  125. * again. Receive buffers can be fragmented in up to 16 fragments
  126. * (descriptor entries). For simplicity, this driver posts
  127. * single-fragment receive buffers of 4608 bytes, then allocates a
  128. * sk_buff, copies the data, then reposts the buffer. To reduce CPU
  129. * utilization, a better approach would be to pass up the receive
  130. * buffer (no extra copy) then allocate and post a replacement buffer.
  131. * This is a performance enhancement that should be looked into at
  132. * some point.
  133. *
  134. * Transmit Path -
  135. * Like the receive path, the adapter DMA engine supports a 256 entry
  136. * transmit descriptor block of which up to 255 entries can be used at
  137. * any given time. Transmit buffers can be fragmented in up to 255
  138. * fragments (descriptor entries). This driver always posts one
  139. * fragment per transmit packet request.
  140. *
  141. * The fragment contains the entire packet from FC to end of data.
  142. * Before posting the buffer to the adapter, the driver sets a three-byte
  143. * packet request header (PRH) which is required by the Motorola MAC chip
  144. * used on the adapters. The PRH tells the MAC the type of token to
  145. * receive/send, whether or not to generate and append the CRC, whether
  146. * synchronous or asynchronous framing is used, etc. Since the PRH
  147. * definition is not necessarily consistent across all FDDI chipsets,
  148. * the driver, rather than the common FDDI packet handler routines,
  149. * sets these bytes.
  150. *
  151. * To reduce the amount of descriptor fetches needed per transmit request,
  152. * the driver takes advantage of the fact that there are at least three
  153. * bytes available before the skb->data field on the outgoing transmit
  154. * request. This is guaranteed by having fddi_setup() in net_init.c set
  155. * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
  156. * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
  157. * bytes which we'll use to store the PRH.
  158. *
  159. * There's a subtle advantage to adding these pad bytes to the
  160. * hard_header_len, it ensures that the data portion of the packet for
  161. * an 802.2 SNAP frame is longword aligned. Other FDDI driver
  162. * implementations may not need the extra padding and can start copying
  163. * or DMAing directly from the FC byte which starts at skb->data. Should
  164. * another driver implementation need ADDITIONAL padding, the net_init.c
  165. * module should be updated and dev->hard_header_len should be increased.
  166. * NOTE: To maintain the alignment on the data portion of the packet,
  167. * dev->hard_header_len should always be evenly divisible by 4 and at
  168. * least 24 bytes in size.
  169. *
  170. * Modification History:
  171. * Date Name Description
  172. * 16-Aug-96 LVS Created.
  173. * 20-Aug-96 LVS Updated dfx_probe so that version information
  174. * string is only displayed if 1 or more cards are
  175. * found. Changed dfx_rcv_queue_process to copy
  176. * 3 NULL bytes before FC to ensure that data is
  177. * longword aligned in receive buffer.
  178. * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
  179. * LLC group promiscuous mode if multicast list
  180. * is too large. LLC individual/group promiscuous
  181. * mode is now disabled if IFF_PROMISC flag not set.
  182. * dfx_xmt_queue_pkt no longer checks for NULL skb
  183. * on Alan Cox recommendation. Added node address
  184. * override support.
  185. * 12-Sep-96 LVS Reset current address to factory address during
  186. * device open. Updated transmit path to post a
  187. * single fragment which includes PRH->end of data.
  188. * Mar 2000 AC Did various cleanups for 2.3.x
  189. * Jun 2000 jgarzik PCI and resource alloc cleanups
  190. * Jul 2000 tjeerd Much cleanup and some bug fixes
  191. * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
  192. * Feb 2001 Skb allocation fixes
  193. * Feb 2001 davej PCI enable cleanups.
  194. * 04 Aug 2003 macro Converted to the DMA API.
  195. * 14 Aug 2004 macro Fix device names reported.
  196. * 14 Jun 2005 macro Use irqreturn_t.
  197. * 23 Oct 2006 macro Big-endian host support.
  198. * 14 Dec 2006 macro TURBOchannel support.
  199. * 01 Jul 2014 macro Fixes for DMA on 64-bit hosts.
  200. */
  201. /* Include files */
  202. #include <linux/bitops.h>
  203. #include <linux/compiler.h>
  204. #include <linux/delay.h>
  205. #include <linux/dma-mapping.h>
  206. #include <linux/eisa.h>
  207. #include <linux/errno.h>
  208. #include <linux/fddidevice.h>
  209. #include <linux/interrupt.h>
  210. #include <linux/ioport.h>
  211. #include <linux/kernel.h>
  212. #include <linux/module.h>
  213. #include <linux/netdevice.h>
  214. #include <linux/pci.h>
  215. #include <linux/skbuff.h>
  216. #include <linux/slab.h>
  217. #include <linux/string.h>
  218. #include <linux/tc.h>
  219. #include <asm/byteorder.h>
  220. #include <asm/io.h>
  221. #include "defxx.h"
  222. /* Version information string should be updated prior to each new release! */
  223. #define DRV_NAME "defxx"
  224. #define DRV_VERSION "v1.11"
  225. #define DRV_RELDATE "2014/07/01"
  226. static const char version[] =
  227. DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
  228. " Lawrence V. Stefani and others\n";
  229. #define DYNAMIC_BUFFERS 1
  230. #define SKBUFF_RX_COPYBREAK 200
  231. /*
  232. * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
  233. * alignment for compatibility with old EISA boards.
  234. */
  235. #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
  236. #ifdef CONFIG_EISA
  237. #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type)
  238. #else
  239. #define DFX_BUS_EISA(dev) 0
  240. #endif
  241. #ifdef CONFIG_TC
  242. #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type)
  243. #else
  244. #define DFX_BUS_TC(dev) 0
  245. #endif
  246. #ifdef CONFIG_DEFXX_MMIO
  247. #define DFX_MMIO 1
  248. #else
  249. #define DFX_MMIO 0
  250. #endif
  251. /* Define module-wide (static) routines */
  252. static void dfx_bus_init(struct net_device *dev);
  253. static void dfx_bus_uninit(struct net_device *dev);
  254. static void dfx_bus_config_check(DFX_board_t *bp);
  255. static int dfx_driver_init(struct net_device *dev,
  256. const char *print_name,
  257. resource_size_t bar_start);
  258. static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
  259. static int dfx_open(struct net_device *dev);
  260. static int dfx_close(struct net_device *dev);
  261. static void dfx_int_pr_halt_id(DFX_board_t *bp);
  262. static void dfx_int_type_0_process(DFX_board_t *bp);
  263. static void dfx_int_common(struct net_device *dev);
  264. static irqreturn_t dfx_interrupt(int irq, void *dev_id);
  265. static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
  266. static void dfx_ctl_set_multicast_list(struct net_device *dev);
  267. static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
  268. static int dfx_ctl_update_cam(DFX_board_t *bp);
  269. static int dfx_ctl_update_filters(DFX_board_t *bp);
  270. static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
  271. static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
  272. static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
  273. static int dfx_hw_adap_state_rd(DFX_board_t *bp);
  274. static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
  275. static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
  276. static void dfx_rcv_queue_process(DFX_board_t *bp);
  277. #ifdef DYNAMIC_BUFFERS
  278. static void dfx_rcv_flush(DFX_board_t *bp);
  279. #else
  280. static inline void dfx_rcv_flush(DFX_board_t *bp) {}
  281. #endif
  282. static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb,
  283. struct net_device *dev);
  284. static int dfx_xmt_done(DFX_board_t *bp);
  285. static void dfx_xmt_flush(DFX_board_t *bp);
  286. /* Define module-wide (static) variables */
  287. static struct pci_driver dfx_pci_driver;
  288. static struct eisa_driver dfx_eisa_driver;
  289. static struct tc_driver dfx_tc_driver;
  290. /*
  291. * =======================
  292. * = dfx_port_write_long =
  293. * = dfx_port_read_long =
  294. * =======================
  295. *
  296. * Overview:
  297. * Routines for reading and writing values from/to adapter
  298. *
  299. * Returns:
  300. * None
  301. *
  302. * Arguments:
  303. * bp - pointer to board information
  304. * offset - register offset from base I/O address
  305. * data - for dfx_port_write_long, this is a value to write;
  306. * for dfx_port_read_long, this is a pointer to store
  307. * the read value
  308. *
  309. * Functional Description:
  310. * These routines perform the correct operation to read or write
  311. * the adapter register.
  312. *
  313. * EISA port block base addresses are based on the slot number in which the
  314. * controller is installed. For example, if the EISA controller is installed
  315. * in slot 4, the port block base address is 0x4000. If the controller is
  316. * installed in slot 2, the port block base address is 0x2000, and so on.
  317. * This port block can be used to access PDQ, ESIC, and DEFEA on-board
  318. * registers using the register offsets defined in DEFXX.H.
  319. *
  320. * PCI port block base addresses are assigned by the PCI BIOS or system
  321. * firmware. There is one 128 byte port block which can be accessed. It
  322. * allows for I/O mapping of both PDQ and PFI registers using the register
  323. * offsets defined in DEFXX.H.
  324. *
  325. * Return Codes:
  326. * None
  327. *
  328. * Assumptions:
  329. * bp->base is a valid base I/O address for this adapter.
  330. * offset is a valid register offset for this adapter.
  331. *
  332. * Side Effects:
  333. * Rather than produce macros for these functions, these routines
  334. * are defined using "inline" to ensure that the compiler will
  335. * generate inline code and not waste a procedure call and return.
  336. * This provides all the benefits of macros, but with the
  337. * advantage of strict data type checking.
  338. */
  339. static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data)
  340. {
  341. writel(data, bp->base.mem + offset);
  342. mb();
  343. }
  344. static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data)
  345. {
  346. outl(data, bp->base.port + offset);
  347. }
  348. static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data)
  349. {
  350. struct device __maybe_unused *bdev = bp->bus_dev;
  351. int dfx_bus_tc = DFX_BUS_TC(bdev);
  352. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  353. if (dfx_use_mmio)
  354. dfx_writel(bp, offset, data);
  355. else
  356. dfx_outl(bp, offset, data);
  357. }
  358. static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data)
  359. {
  360. mb();
  361. *data = readl(bp->base.mem + offset);
  362. }
  363. static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data)
  364. {
  365. *data = inl(bp->base.port + offset);
  366. }
  367. static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data)
  368. {
  369. struct device __maybe_unused *bdev = bp->bus_dev;
  370. int dfx_bus_tc = DFX_BUS_TC(bdev);
  371. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  372. if (dfx_use_mmio)
  373. dfx_readl(bp, offset, data);
  374. else
  375. dfx_inl(bp, offset, data);
  376. }
  377. /*
  378. * ================
  379. * = dfx_get_bars =
  380. * ================
  381. *
  382. * Overview:
  383. * Retrieves the address ranges used to access control and status
  384. * registers.
  385. *
  386. * Returns:
  387. * None
  388. *
  389. * Arguments:
  390. * bdev - pointer to device information
  391. * bar_start - pointer to store the start addresses
  392. * bar_len - pointer to store the lengths of the areas
  393. *
  394. * Assumptions:
  395. * I am sure there are some.
  396. *
  397. * Side Effects:
  398. * None
  399. */
  400. static void dfx_get_bars(struct device *bdev,
  401. resource_size_t *bar_start, resource_size_t *bar_len)
  402. {
  403. int dfx_bus_pci = dev_is_pci(bdev);
  404. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  405. int dfx_bus_tc = DFX_BUS_TC(bdev);
  406. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  407. if (dfx_bus_pci) {
  408. int num = dfx_use_mmio ? 0 : 1;
  409. bar_start[0] = pci_resource_start(to_pci_dev(bdev), num);
  410. bar_len[0] = pci_resource_len(to_pci_dev(bdev), num);
  411. bar_start[2] = bar_start[1] = 0;
  412. bar_len[2] = bar_len[1] = 0;
  413. }
  414. if (dfx_bus_eisa) {
  415. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  416. resource_size_t bar_lo;
  417. resource_size_t bar_hi;
  418. if (dfx_use_mmio) {
  419. bar_lo = inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_2);
  420. bar_lo <<= 8;
  421. bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_1);
  422. bar_lo <<= 8;
  423. bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_0);
  424. bar_lo <<= 8;
  425. bar_start[0] = bar_lo;
  426. bar_hi = inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_2);
  427. bar_hi <<= 8;
  428. bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_1);
  429. bar_hi <<= 8;
  430. bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_0);
  431. bar_hi <<= 8;
  432. bar_len[0] = ((bar_hi - bar_lo) | PI_MEM_ADD_MASK_M) +
  433. 1;
  434. } else {
  435. bar_start[0] = base_addr;
  436. bar_len[0] = PI_ESIC_K_CSR_IO_LEN;
  437. }
  438. bar_start[1] = base_addr + PI_DEFEA_K_BURST_HOLDOFF;
  439. bar_len[1] = PI_ESIC_K_BURST_HOLDOFF_LEN;
  440. bar_start[2] = base_addr + PI_ESIC_K_ESIC_CSR;
  441. bar_len[2] = PI_ESIC_K_ESIC_CSR_LEN;
  442. }
  443. if (dfx_bus_tc) {
  444. bar_start[0] = to_tc_dev(bdev)->resource.start +
  445. PI_TC_K_CSR_OFFSET;
  446. bar_len[0] = PI_TC_K_CSR_LEN;
  447. bar_start[2] = bar_start[1] = 0;
  448. bar_len[2] = bar_len[1] = 0;
  449. }
  450. }
  451. static const struct net_device_ops dfx_netdev_ops = {
  452. .ndo_open = dfx_open,
  453. .ndo_stop = dfx_close,
  454. .ndo_start_xmit = dfx_xmt_queue_pkt,
  455. .ndo_get_stats = dfx_ctl_get_stats,
  456. .ndo_set_rx_mode = dfx_ctl_set_multicast_list,
  457. .ndo_set_mac_address = dfx_ctl_set_mac_address,
  458. };
  459. static void dfx_register_res_alloc_err(const char *print_name, bool mmio,
  460. bool eisa)
  461. {
  462. pr_err("%s: Cannot use %s, no address set, aborting\n",
  463. print_name, mmio ? "MMIO" : "I/O");
  464. pr_err("%s: Recompile driver with \"CONFIG_DEFXX_MMIO=%c\"\n",
  465. print_name, mmio ? 'n' : 'y');
  466. if (eisa && mmio)
  467. pr_err("%s: Or run ECU and set adapter's MMIO location\n",
  468. print_name);
  469. }
  470. static void dfx_register_res_err(const char *print_name, bool mmio,
  471. unsigned long start, unsigned long len)
  472. {
  473. pr_err("%s: Cannot reserve %s resource 0x%lx @ 0x%lx, aborting\n",
  474. print_name, mmio ? "MMIO" : "I/O", len, start);
  475. }
  476. /*
  477. * ================
  478. * = dfx_register =
  479. * ================
  480. *
  481. * Overview:
  482. * Initializes a supported FDDI controller
  483. *
  484. * Returns:
  485. * Condition code
  486. *
  487. * Arguments:
  488. * bdev - pointer to device information
  489. *
  490. * Functional Description:
  491. *
  492. * Return Codes:
  493. * 0 - This device (fddi0, fddi1, etc) configured successfully
  494. * -EBUSY - Failed to get resources, or dfx_driver_init failed.
  495. *
  496. * Assumptions:
  497. * It compiles so it should work :-( (PCI cards do :-)
  498. *
  499. * Side Effects:
  500. * Device structures for FDDI adapters (fddi0, fddi1, etc) are
  501. * initialized and the board resources are read and stored in
  502. * the device structure.
  503. */
  504. static int dfx_register(struct device *bdev)
  505. {
  506. static int version_disp;
  507. int dfx_bus_pci = dev_is_pci(bdev);
  508. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  509. int dfx_bus_tc = DFX_BUS_TC(bdev);
  510. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  511. const char *print_name = dev_name(bdev);
  512. struct net_device *dev;
  513. DFX_board_t *bp; /* board pointer */
  514. resource_size_t bar_start[3] = {0}; /* pointers to ports */
  515. resource_size_t bar_len[3] = {0}; /* resource length */
  516. int alloc_size; /* total buffer size used */
  517. struct resource *region;
  518. int err = 0;
  519. if (!version_disp) { /* display version info if adapter is found */
  520. version_disp = 1; /* set display flag to TRUE so that */
  521. printk(version); /* we only display this string ONCE */
  522. }
  523. dev = alloc_fddidev(sizeof(*bp));
  524. if (!dev) {
  525. printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n",
  526. print_name);
  527. return -ENOMEM;
  528. }
  529. /* Enable PCI device. */
  530. if (dfx_bus_pci) {
  531. err = pci_enable_device(to_pci_dev(bdev));
  532. if (err) {
  533. pr_err("%s: Cannot enable PCI device, aborting\n",
  534. print_name);
  535. goto err_out;
  536. }
  537. }
  538. SET_NETDEV_DEV(dev, bdev);
  539. bp = netdev_priv(dev);
  540. bp->bus_dev = bdev;
  541. dev_set_drvdata(bdev, dev);
  542. dfx_get_bars(bdev, bar_start, bar_len);
  543. if (bar_len[0] == 0 ||
  544. (dfx_bus_eisa && dfx_use_mmio && bar_start[0] == 0)) {
  545. dfx_register_res_alloc_err(print_name, dfx_use_mmio,
  546. dfx_bus_eisa);
  547. err = -ENXIO;
  548. goto err_out_disable;
  549. }
  550. if (dfx_use_mmio)
  551. region = request_mem_region(bar_start[0], bar_len[0],
  552. print_name);
  553. else
  554. region = request_region(bar_start[0], bar_len[0], print_name);
  555. if (!region) {
  556. dfx_register_res_err(print_name, dfx_use_mmio,
  557. bar_start[0], bar_len[0]);
  558. err = -EBUSY;
  559. goto err_out_disable;
  560. }
  561. if (bar_start[1] != 0) {
  562. region = request_region(bar_start[1], bar_len[1], print_name);
  563. if (!region) {
  564. dfx_register_res_err(print_name, 0,
  565. bar_start[1], bar_len[1]);
  566. err = -EBUSY;
  567. goto err_out_csr_region;
  568. }
  569. }
  570. if (bar_start[2] != 0) {
  571. region = request_region(bar_start[2], bar_len[2], print_name);
  572. if (!region) {
  573. dfx_register_res_err(print_name, 0,
  574. bar_start[2], bar_len[2]);
  575. err = -EBUSY;
  576. goto err_out_bh_region;
  577. }
  578. }
  579. /* Set up I/O base address. */
  580. if (dfx_use_mmio) {
  581. bp->base.mem = ioremap(bar_start[0], bar_len[0]);
  582. if (!bp->base.mem) {
  583. printk(KERN_ERR "%s: Cannot map MMIO\n", print_name);
  584. err = -ENOMEM;
  585. goto err_out_esic_region;
  586. }
  587. } else {
  588. bp->base.port = bar_start[0];
  589. dev->base_addr = bar_start[0];
  590. }
  591. /* Initialize new device structure */
  592. dev->netdev_ops = &dfx_netdev_ops;
  593. if (dfx_bus_pci)
  594. pci_set_master(to_pci_dev(bdev));
  595. if (dfx_driver_init(dev, print_name, bar_start[0]) != DFX_K_SUCCESS) {
  596. err = -ENODEV;
  597. goto err_out_unmap;
  598. }
  599. err = register_netdev(dev);
  600. if (err)
  601. goto err_out_kfree;
  602. printk("%s: registered as %s\n", print_name, dev->name);
  603. return 0;
  604. err_out_kfree:
  605. alloc_size = sizeof(PI_DESCR_BLOCK) +
  606. PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
  607. #ifndef DYNAMIC_BUFFERS
  608. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  609. #endif
  610. sizeof(PI_CONSUMER_BLOCK) +
  611. (PI_ALIGN_K_DESC_BLK - 1);
  612. if (bp->kmalloced)
  613. dma_free_coherent(bdev, alloc_size,
  614. bp->kmalloced, bp->kmalloced_dma);
  615. err_out_unmap:
  616. if (dfx_use_mmio)
  617. iounmap(bp->base.mem);
  618. err_out_esic_region:
  619. if (bar_start[2] != 0)
  620. release_region(bar_start[2], bar_len[2]);
  621. err_out_bh_region:
  622. if (bar_start[1] != 0)
  623. release_region(bar_start[1], bar_len[1]);
  624. err_out_csr_region:
  625. if (dfx_use_mmio)
  626. release_mem_region(bar_start[0], bar_len[0]);
  627. else
  628. release_region(bar_start[0], bar_len[0]);
  629. err_out_disable:
  630. if (dfx_bus_pci)
  631. pci_disable_device(to_pci_dev(bdev));
  632. err_out:
  633. free_netdev(dev);
  634. return err;
  635. }
  636. /*
  637. * ================
  638. * = dfx_bus_init =
  639. * ================
  640. *
  641. * Overview:
  642. * Initializes the bus-specific controller logic.
  643. *
  644. * Returns:
  645. * None
  646. *
  647. * Arguments:
  648. * dev - pointer to device information
  649. *
  650. * Functional Description:
  651. * Determine and save adapter IRQ in device table,
  652. * then perform bus-specific logic initialization.
  653. *
  654. * Return Codes:
  655. * None
  656. *
  657. * Assumptions:
  658. * bp->base has already been set with the proper
  659. * base I/O address for this device.
  660. *
  661. * Side Effects:
  662. * Interrupts are enabled at the adapter bus-specific logic.
  663. * Note: Interrupts at the DMA engine (PDQ chip) are not
  664. * enabled yet.
  665. */
  666. static void dfx_bus_init(struct net_device *dev)
  667. {
  668. DFX_board_t *bp = netdev_priv(dev);
  669. struct device *bdev = bp->bus_dev;
  670. int dfx_bus_pci = dev_is_pci(bdev);
  671. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  672. int dfx_bus_tc = DFX_BUS_TC(bdev);
  673. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  674. u8 val;
  675. DBG_printk("In dfx_bus_init...\n");
  676. /* Initialize a pointer back to the net_device struct */
  677. bp->dev = dev;
  678. /* Initialize adapter based on bus type */
  679. if (dfx_bus_tc)
  680. dev->irq = to_tc_dev(bdev)->interrupt;
  681. if (dfx_bus_eisa) {
  682. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  683. /* Disable the board before fiddling with the decoders. */
  684. outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL);
  685. /* Get the interrupt level from the ESIC chip. */
  686. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  687. val &= PI_CONFIG_STAT_0_M_IRQ;
  688. val >>= PI_CONFIG_STAT_0_V_IRQ;
  689. switch (val) {
  690. case PI_CONFIG_STAT_0_IRQ_K_9:
  691. dev->irq = 9;
  692. break;
  693. case PI_CONFIG_STAT_0_IRQ_K_10:
  694. dev->irq = 10;
  695. break;
  696. case PI_CONFIG_STAT_0_IRQ_K_11:
  697. dev->irq = 11;
  698. break;
  699. case PI_CONFIG_STAT_0_IRQ_K_15:
  700. dev->irq = 15;
  701. break;
  702. }
  703. /*
  704. * Enable memory decoding (MEMCS1) and/or port decoding
  705. * (IOCS1/IOCS0) as appropriate in Function Control
  706. * Register. MEMCS1 or IOCS0 is used for PDQ registers,
  707. * taking 16 32-bit words, while IOCS1 is used for the
  708. * Burst Holdoff register, taking a single 32-bit word
  709. * only. We use the slot-specific I/O range as per the
  710. * ESIC spec, that is set bits 15:12 in the mask registers
  711. * to mask them out.
  712. */
  713. /* Set the decode range of the board. */
  714. val = 0;
  715. outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1);
  716. val = PI_DEFEA_K_CSR_IO;
  717. outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0);
  718. val = PI_IO_CMP_M_SLOT;
  719. outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1);
  720. val = (PI_ESIC_K_CSR_IO_LEN - 1) & ~3;
  721. outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0);
  722. val = 0;
  723. outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1);
  724. val = PI_DEFEA_K_BURST_HOLDOFF;
  725. outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0);
  726. val = PI_IO_CMP_M_SLOT;
  727. outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1);
  728. val = (PI_ESIC_K_BURST_HOLDOFF_LEN - 1) & ~3;
  729. outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0);
  730. /* Enable the decoders. */
  731. val = PI_FUNCTION_CNTRL_M_IOCS1;
  732. if (dfx_use_mmio)
  733. val |= PI_FUNCTION_CNTRL_M_MEMCS1;
  734. else
  735. val |= PI_FUNCTION_CNTRL_M_IOCS0;
  736. outb(val, base_addr + PI_ESIC_K_FUNCTION_CNTRL);
  737. /*
  738. * Enable access to the rest of the module
  739. * (including PDQ and packet memory).
  740. */
  741. val = PI_SLOT_CNTRL_M_ENB;
  742. outb(val, base_addr + PI_ESIC_K_SLOT_CNTRL);
  743. /*
  744. * Map PDQ registers into memory or port space. This is
  745. * done with a bit in the Burst Holdoff register.
  746. */
  747. val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
  748. if (dfx_use_mmio)
  749. val |= PI_BURST_HOLDOFF_M_MEM_MAP;
  750. else
  751. val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;
  752. outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);
  753. /* Enable interrupts at EISA bus interface chip (ESIC) */
  754. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  755. val |= PI_CONFIG_STAT_0_M_INT_ENB;
  756. outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  757. }
  758. if (dfx_bus_pci) {
  759. struct pci_dev *pdev = to_pci_dev(bdev);
  760. /* Get the interrupt level from the PCI Configuration Table */
  761. dev->irq = pdev->irq;
  762. /* Check Latency Timer and set if less than minimal */
  763. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
  764. if (val < PFI_K_LAT_TIMER_MIN) {
  765. val = PFI_K_LAT_TIMER_DEF;
  766. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
  767. }
  768. /* Enable interrupts at PCI bus interface chip (PFI) */
  769. val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB;
  770. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val);
  771. }
  772. }
  773. /*
  774. * ==================
  775. * = dfx_bus_uninit =
  776. * ==================
  777. *
  778. * Overview:
  779. * Uninitializes the bus-specific controller logic.
  780. *
  781. * Returns:
  782. * None
  783. *
  784. * Arguments:
  785. * dev - pointer to device information
  786. *
  787. * Functional Description:
  788. * Perform bus-specific logic uninitialization.
  789. *
  790. * Return Codes:
  791. * None
  792. *
  793. * Assumptions:
  794. * bp->base has already been set with the proper
  795. * base I/O address for this device.
  796. *
  797. * Side Effects:
  798. * Interrupts are disabled at the adapter bus-specific logic.
  799. */
  800. static void dfx_bus_uninit(struct net_device *dev)
  801. {
  802. DFX_board_t *bp = netdev_priv(dev);
  803. struct device *bdev = bp->bus_dev;
  804. int dfx_bus_pci = dev_is_pci(bdev);
  805. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  806. u8 val;
  807. DBG_printk("In dfx_bus_uninit...\n");
  808. /* Uninitialize adapter based on bus type */
  809. if (dfx_bus_eisa) {
  810. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  811. /* Disable interrupts at EISA bus interface chip (ESIC) */
  812. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  813. val &= ~PI_CONFIG_STAT_0_M_INT_ENB;
  814. outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  815. /* Disable the board. */
  816. outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL);
  817. /* Disable memory and port decoders. */
  818. outb(0, base_addr + PI_ESIC_K_FUNCTION_CNTRL);
  819. }
  820. if (dfx_bus_pci) {
  821. /* Disable interrupts at PCI bus interface chip (PFI) */
  822. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0);
  823. }
  824. }
  825. /*
  826. * ========================
  827. * = dfx_bus_config_check =
  828. * ========================
  829. *
  830. * Overview:
  831. * Checks the configuration (burst size, full-duplex, etc.) If any parameters
  832. * are illegal, then this routine will set new defaults.
  833. *
  834. * Returns:
  835. * None
  836. *
  837. * Arguments:
  838. * bp - pointer to board information
  839. *
  840. * Functional Description:
  841. * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
  842. * PDQ, and all FDDI PCI controllers, all values are legal.
  843. *
  844. * Return Codes:
  845. * None
  846. *
  847. * Assumptions:
  848. * dfx_adap_init has NOT been called yet so burst size and other items have
  849. * not been set.
  850. *
  851. * Side Effects:
  852. * None
  853. */
  854. static void dfx_bus_config_check(DFX_board_t *bp)
  855. {
  856. struct device __maybe_unused *bdev = bp->bus_dev;
  857. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  858. int status; /* return code from adapter port control call */
  859. u32 host_data; /* LW data returned from port control call */
  860. DBG_printk("In dfx_bus_config_check...\n");
  861. /* Configuration check only valid for EISA adapter */
  862. if (dfx_bus_eisa) {
  863. /*
  864. * First check if revision 2 EISA controller. Rev. 1 cards used
  865. * PDQ revision B, so no workaround needed in this case. Rev. 3
  866. * cards used PDQ revision E, so no workaround needed in this
  867. * case, either. Only Rev. 2 cards used either Rev. D or E
  868. * chips, so we must verify the chip revision on Rev. 2 cards.
  869. */
  870. if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) {
  871. /*
  872. * Revision 2 FDDI EISA controller found,
  873. * so let's check PDQ revision of adapter.
  874. */
  875. status = dfx_hw_port_ctrl_req(bp,
  876. PI_PCTRL_M_SUB_CMD,
  877. PI_SUB_CMD_K_PDQ_REV_GET,
  878. 0,
  879. &host_data);
  880. if ((status != DFX_K_SUCCESS) || (host_data == 2))
  881. {
  882. /*
  883. * Either we couldn't determine the PDQ revision, or
  884. * we determined that it is at revision D. In either case,
  885. * we need to implement the workaround.
  886. */
  887. /* Ensure that the burst size is set to 8 longwords or less */
  888. switch (bp->burst_size)
  889. {
  890. case PI_PDATA_B_DMA_BURST_SIZE_32:
  891. case PI_PDATA_B_DMA_BURST_SIZE_16:
  892. bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
  893. break;
  894. default:
  895. break;
  896. }
  897. /* Ensure that full-duplex mode is not enabled */
  898. bp->full_duplex_enb = PI_SNMP_K_FALSE;
  899. }
  900. }
  901. }
  902. }
  903. /*
  904. * ===================
  905. * = dfx_driver_init =
  906. * ===================
  907. *
  908. * Overview:
  909. * Initializes remaining adapter board structure information
  910. * and makes sure adapter is in a safe state prior to dfx_open().
  911. *
  912. * Returns:
  913. * Condition code
  914. *
  915. * Arguments:
  916. * dev - pointer to device information
  917. * print_name - printable device name
  918. *
  919. * Functional Description:
  920. * This function allocates additional resources such as the host memory
  921. * blocks needed by the adapter (eg. descriptor and consumer blocks).
  922. * Remaining bus initialization steps are also completed. The adapter
  923. * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
  924. * must call dfx_open() to open the adapter and bring it on-line.
  925. *
  926. * Return Codes:
  927. * DFX_K_SUCCESS - initialization succeeded
  928. * DFX_K_FAILURE - initialization failed - could not allocate memory
  929. * or read adapter MAC address
  930. *
  931. * Assumptions:
  932. * Memory allocated from pci_alloc_consistent() call is physically
  933. * contiguous, locked memory.
  934. *
  935. * Side Effects:
  936. * Adapter is reset and should be in DMA_UNAVAILABLE state before
  937. * returning from this routine.
  938. */
  939. static int dfx_driver_init(struct net_device *dev, const char *print_name,
  940. resource_size_t bar_start)
  941. {
  942. DFX_board_t *bp = netdev_priv(dev);
  943. struct device *bdev = bp->bus_dev;
  944. int dfx_bus_pci = dev_is_pci(bdev);
  945. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  946. int dfx_bus_tc = DFX_BUS_TC(bdev);
  947. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  948. int alloc_size; /* total buffer size needed */
  949. char *top_v, *curr_v; /* virtual addrs into memory block */
  950. dma_addr_t top_p, curr_p; /* physical addrs into memory block */
  951. u32 data; /* host data register value */
  952. __le32 le32;
  953. char *board_name = NULL;
  954. DBG_printk("In dfx_driver_init...\n");
  955. /* Initialize bus-specific hardware registers */
  956. dfx_bus_init(dev);
  957. /*
  958. * Initialize default values for configurable parameters
  959. *
  960. * Note: All of these parameters are ones that a user may
  961. * want to customize. It'd be nice to break these
  962. * out into Space.c or someplace else that's more
  963. * accessible/understandable than this file.
  964. */
  965. bp->full_duplex_enb = PI_SNMP_K_FALSE;
  966. bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
  967. bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
  968. bp->rcv_bufs_to_post = RCV_BUFS_DEF;
  969. /*
  970. * Ensure that HW configuration is OK
  971. *
  972. * Note: Depending on the hardware revision, we may need to modify
  973. * some of the configurable parameters to workaround hardware
  974. * limitations. We'll perform this configuration check AFTER
  975. * setting the parameters to their default values.
  976. */
  977. dfx_bus_config_check(bp);
  978. /* Disable PDQ interrupts first */
  979. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  980. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  981. (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
  982. /* Read the factory MAC address from the adapter then save it */
  983. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
  984. &data) != DFX_K_SUCCESS) {
  985. printk("%s: Could not read adapter factory MAC address!\n",
  986. print_name);
  987. return DFX_K_FAILURE;
  988. }
  989. le32 = cpu_to_le32(data);
  990. memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32));
  991. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
  992. &data) != DFX_K_SUCCESS) {
  993. printk("%s: Could not read adapter factory MAC address!\n",
  994. print_name);
  995. return DFX_K_FAILURE;
  996. }
  997. le32 = cpu_to_le32(data);
  998. memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16));
  999. /*
  1000. * Set current address to factory address
  1001. *
  1002. * Note: Node address override support is handled through
  1003. * dfx_ctl_set_mac_address.
  1004. */
  1005. memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
  1006. if (dfx_bus_tc)
  1007. board_name = "DEFTA";
  1008. if (dfx_bus_eisa)
  1009. board_name = "DEFEA";
  1010. if (dfx_bus_pci)
  1011. board_name = "DEFPA";
  1012. pr_info("%s: %s at %s addr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n",
  1013. print_name, board_name, dfx_use_mmio ? "MMIO" : "I/O",
  1014. (long long)bar_start, dev->irq, dev->dev_addr);
  1015. /*
  1016. * Get memory for descriptor block, consumer block, and other buffers
  1017. * that need to be DMA read or written to by the adapter.
  1018. */
  1019. alloc_size = sizeof(PI_DESCR_BLOCK) +
  1020. PI_CMD_REQ_K_SIZE_MAX +
  1021. PI_CMD_RSP_K_SIZE_MAX +
  1022. #ifndef DYNAMIC_BUFFERS
  1023. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  1024. #endif
  1025. sizeof(PI_CONSUMER_BLOCK) +
  1026. (PI_ALIGN_K_DESC_BLK - 1);
  1027. bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size,
  1028. &bp->kmalloced_dma,
  1029. GFP_ATOMIC);
  1030. if (top_v == NULL)
  1031. return DFX_K_FAILURE;
  1032. top_p = bp->kmalloced_dma; /* get physical address of buffer */
  1033. /*
  1034. * To guarantee the 8K alignment required for the descriptor block, 8K - 1
  1035. * plus the amount of memory needed was allocated. The physical address
  1036. * is now 8K aligned. By carving up the memory in a specific order,
  1037. * we'll guarantee the alignment requirements for all other structures.
  1038. *
  1039. * Note: If the assumptions change regarding the non-paged, non-cached,
  1040. * physically contiguous nature of the memory block or the address
  1041. * alignments, then we'll need to implement a different algorithm
  1042. * for allocating the needed memory.
  1043. */
  1044. curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
  1045. curr_v = top_v + (curr_p - top_p);
  1046. /* Reserve space for descriptor block */
  1047. bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
  1048. bp->descr_block_phys = curr_p;
  1049. curr_v += sizeof(PI_DESCR_BLOCK);
  1050. curr_p += sizeof(PI_DESCR_BLOCK);
  1051. /* Reserve space for command request buffer */
  1052. bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
  1053. bp->cmd_req_phys = curr_p;
  1054. curr_v += PI_CMD_REQ_K_SIZE_MAX;
  1055. curr_p += PI_CMD_REQ_K_SIZE_MAX;
  1056. /* Reserve space for command response buffer */
  1057. bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
  1058. bp->cmd_rsp_phys = curr_p;
  1059. curr_v += PI_CMD_RSP_K_SIZE_MAX;
  1060. curr_p += PI_CMD_RSP_K_SIZE_MAX;
  1061. /* Reserve space for the LLC host receive queue buffers */
  1062. bp->rcv_block_virt = curr_v;
  1063. bp->rcv_block_phys = curr_p;
  1064. #ifndef DYNAMIC_BUFFERS
  1065. curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
  1066. curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
  1067. #endif
  1068. /* Reserve space for the consumer block */
  1069. bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
  1070. bp->cons_block_phys = curr_p;
  1071. /* Display virtual and physical addresses if debug driver */
  1072. DBG_printk("%s: Descriptor block virt = %p, phys = %pad\n",
  1073. print_name, bp->descr_block_virt, &bp->descr_block_phys);
  1074. DBG_printk("%s: Command Request buffer virt = %p, phys = %pad\n",
  1075. print_name, bp->cmd_req_virt, &bp->cmd_req_phys);
  1076. DBG_printk("%s: Command Response buffer virt = %p, phys = %pad\n",
  1077. print_name, bp->cmd_rsp_virt, &bp->cmd_rsp_phys);
  1078. DBG_printk("%s: Receive buffer block virt = %p, phys = %pad\n",
  1079. print_name, bp->rcv_block_virt, &bp->rcv_block_phys);
  1080. DBG_printk("%s: Consumer block virt = %p, phys = %pad\n",
  1081. print_name, bp->cons_block_virt, &bp->cons_block_phys);
  1082. return DFX_K_SUCCESS;
  1083. }
  1084. /*
  1085. * =================
  1086. * = dfx_adap_init =
  1087. * =================
  1088. *
  1089. * Overview:
  1090. * Brings the adapter to the link avail/link unavailable state.
  1091. *
  1092. * Returns:
  1093. * Condition code
  1094. *
  1095. * Arguments:
  1096. * bp - pointer to board information
  1097. * get_buffers - non-zero if buffers to be allocated
  1098. *
  1099. * Functional Description:
  1100. * Issues the low-level firmware/hardware calls necessary to bring
  1101. * the adapter up, or to properly reset and restore adapter during
  1102. * run-time.
  1103. *
  1104. * Return Codes:
  1105. * DFX_K_SUCCESS - Adapter brought up successfully
  1106. * DFX_K_FAILURE - Adapter initialization failed
  1107. *
  1108. * Assumptions:
  1109. * bp->reset_type should be set to a valid reset type value before
  1110. * calling this routine.
  1111. *
  1112. * Side Effects:
  1113. * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
  1114. * upon a successful return of this routine.
  1115. */
  1116. static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
  1117. {
  1118. DBG_printk("In dfx_adap_init...\n");
  1119. /* Disable PDQ interrupts first */
  1120. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1121. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  1122. if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
  1123. {
  1124. printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
  1125. return DFX_K_FAILURE;
  1126. }
  1127. /*
  1128. * When the PDQ is reset, some false Type 0 interrupts may be pending,
  1129. * so we'll acknowledge all Type 0 interrupts now before continuing.
  1130. */
  1131. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
  1132. /*
  1133. * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
  1134. *
  1135. * Note: We only need to clear host copies of these registers. The PDQ reset
  1136. * takes care of the on-board register values.
  1137. */
  1138. bp->cmd_req_reg.lword = 0;
  1139. bp->cmd_rsp_reg.lword = 0;
  1140. bp->rcv_xmt_reg.lword = 0;
  1141. /* Clear consumer block before going to DMA_AVAILABLE state */
  1142. memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
  1143. /* Initialize the DMA Burst Size */
  1144. if (dfx_hw_port_ctrl_req(bp,
  1145. PI_PCTRL_M_SUB_CMD,
  1146. PI_SUB_CMD_K_BURST_SIZE_SET,
  1147. bp->burst_size,
  1148. NULL) != DFX_K_SUCCESS)
  1149. {
  1150. printk("%s: Could not set adapter burst size!\n", bp->dev->name);
  1151. return DFX_K_FAILURE;
  1152. }
  1153. /*
  1154. * Set base address of Consumer Block
  1155. *
  1156. * Assumption: 32-bit physical address of consumer block is 64 byte
  1157. * aligned. That is, bits 0-5 of the address must be zero.
  1158. */
  1159. if (dfx_hw_port_ctrl_req(bp,
  1160. PI_PCTRL_M_CONS_BLOCK,
  1161. bp->cons_block_phys,
  1162. 0,
  1163. NULL) != DFX_K_SUCCESS)
  1164. {
  1165. printk("%s: Could not set consumer block address!\n", bp->dev->name);
  1166. return DFX_K_FAILURE;
  1167. }
  1168. /*
  1169. * Set the base address of Descriptor Block and bring adapter
  1170. * to DMA_AVAILABLE state.
  1171. *
  1172. * Note: We also set the literal and data swapping requirements
  1173. * in this command.
  1174. *
  1175. * Assumption: 32-bit physical address of descriptor block
  1176. * is 8Kbyte aligned.
  1177. */
  1178. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
  1179. (u32)(bp->descr_block_phys |
  1180. PI_PDATA_A_INIT_M_BSWAP_INIT),
  1181. 0, NULL) != DFX_K_SUCCESS) {
  1182. printk("%s: Could not set descriptor block address!\n",
  1183. bp->dev->name);
  1184. return DFX_K_FAILURE;
  1185. }
  1186. /* Set transmit flush timeout value */
  1187. bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
  1188. bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
  1189. bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
  1190. bp->cmd_req_virt->char_set.item[0].item_index = 0;
  1191. bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
  1192. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1193. {
  1194. printk("%s: DMA command request failed!\n", bp->dev->name);
  1195. return DFX_K_FAILURE;
  1196. }
  1197. /* Set the initial values for eFDXEnable and MACTReq MIB objects */
  1198. bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
  1199. bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
  1200. bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
  1201. bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
  1202. bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
  1203. bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
  1204. bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
  1205. bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
  1206. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1207. {
  1208. printk("%s: DMA command request failed!\n", bp->dev->name);
  1209. return DFX_K_FAILURE;
  1210. }
  1211. /* Initialize adapter CAM */
  1212. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  1213. {
  1214. printk("%s: Adapter CAM update failed!\n", bp->dev->name);
  1215. return DFX_K_FAILURE;
  1216. }
  1217. /* Initialize adapter filters */
  1218. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  1219. {
  1220. printk("%s: Adapter filters update failed!\n", bp->dev->name);
  1221. return DFX_K_FAILURE;
  1222. }
  1223. /*
  1224. * Remove any existing dynamic buffers (i.e. if the adapter is being
  1225. * reinitialized)
  1226. */
  1227. if (get_buffers)
  1228. dfx_rcv_flush(bp);
  1229. /* Initialize receive descriptor block and produce buffers */
  1230. if (dfx_rcv_init(bp, get_buffers))
  1231. {
  1232. printk("%s: Receive buffer allocation failed\n", bp->dev->name);
  1233. if (get_buffers)
  1234. dfx_rcv_flush(bp);
  1235. return DFX_K_FAILURE;
  1236. }
  1237. /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
  1238. bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
  1239. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1240. {
  1241. printk("%s: Start command failed\n", bp->dev->name);
  1242. if (get_buffers)
  1243. dfx_rcv_flush(bp);
  1244. return DFX_K_FAILURE;
  1245. }
  1246. /* Initialization succeeded, reenable PDQ interrupts */
  1247. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
  1248. return DFX_K_SUCCESS;
  1249. }
  1250. /*
  1251. * ============
  1252. * = dfx_open =
  1253. * ============
  1254. *
  1255. * Overview:
  1256. * Opens the adapter
  1257. *
  1258. * Returns:
  1259. * Condition code
  1260. *
  1261. * Arguments:
  1262. * dev - pointer to device information
  1263. *
  1264. * Functional Description:
  1265. * This function brings the adapter to an operational state.
  1266. *
  1267. * Return Codes:
  1268. * 0 - Adapter was successfully opened
  1269. * -EAGAIN - Could not register IRQ or adapter initialization failed
  1270. *
  1271. * Assumptions:
  1272. * This routine should only be called for a device that was
  1273. * initialized successfully.
  1274. *
  1275. * Side Effects:
  1276. * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
  1277. * if the open is successful.
  1278. */
  1279. static int dfx_open(struct net_device *dev)
  1280. {
  1281. DFX_board_t *bp = netdev_priv(dev);
  1282. int ret;
  1283. DBG_printk("In dfx_open...\n");
  1284. /* Register IRQ - support shared interrupts by passing device ptr */
  1285. ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name,
  1286. dev);
  1287. if (ret) {
  1288. printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
  1289. return ret;
  1290. }
  1291. /*
  1292. * Set current address to factory MAC address
  1293. *
  1294. * Note: We've already done this step in dfx_driver_init.
  1295. * However, it's possible that a user has set a node
  1296. * address override, then closed and reopened the
  1297. * adapter. Unless we reset the device address field
  1298. * now, we'll continue to use the existing modified
  1299. * address.
  1300. */
  1301. memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
  1302. /* Clear local unicast/multicast address tables and counts */
  1303. memset(bp->uc_table, 0, sizeof(bp->uc_table));
  1304. memset(bp->mc_table, 0, sizeof(bp->mc_table));
  1305. bp->uc_count = 0;
  1306. bp->mc_count = 0;
  1307. /* Disable promiscuous filter settings */
  1308. bp->ind_group_prom = PI_FSTATE_K_BLOCK;
  1309. bp->group_prom = PI_FSTATE_K_BLOCK;
  1310. spin_lock_init(&bp->lock);
  1311. /* Reset and initialize adapter */
  1312. bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
  1313. if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
  1314. {
  1315. printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
  1316. free_irq(dev->irq, dev);
  1317. return -EAGAIN;
  1318. }
  1319. /* Set device structure info */
  1320. netif_start_queue(dev);
  1321. return 0;
  1322. }
  1323. /*
  1324. * =============
  1325. * = dfx_close =
  1326. * =============
  1327. *
  1328. * Overview:
  1329. * Closes the device/module.
  1330. *
  1331. * Returns:
  1332. * Condition code
  1333. *
  1334. * Arguments:
  1335. * dev - pointer to device information
  1336. *
  1337. * Functional Description:
  1338. * This routine closes the adapter and brings it to a safe state.
  1339. * The interrupt service routine is deregistered with the OS.
  1340. * The adapter can be opened again with another call to dfx_open().
  1341. *
  1342. * Return Codes:
  1343. * Always return 0.
  1344. *
  1345. * Assumptions:
  1346. * No further requests for this adapter are made after this routine is
  1347. * called. dfx_open() can be called to reset and reinitialize the
  1348. * adapter.
  1349. *
  1350. * Side Effects:
  1351. * Adapter should be in DMA_UNAVAILABLE state upon completion of this
  1352. * routine.
  1353. */
  1354. static int dfx_close(struct net_device *dev)
  1355. {
  1356. DFX_board_t *bp = netdev_priv(dev);
  1357. DBG_printk("In dfx_close...\n");
  1358. /* Disable PDQ interrupts first */
  1359. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1360. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  1361. (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
  1362. /*
  1363. * Flush any pending transmit buffers
  1364. *
  1365. * Note: It's important that we flush the transmit buffers
  1366. * BEFORE we clear our copy of the Type 2 register.
  1367. * Otherwise, we'll have no idea how many buffers
  1368. * we need to free.
  1369. */
  1370. dfx_xmt_flush(bp);
  1371. /*
  1372. * Clear Type 1 and Type 2 registers after adapter reset
  1373. *
  1374. * Note: Even though we're closing the adapter, it's
  1375. * possible that an interrupt will occur after
  1376. * dfx_close is called. Without some assurance to
  1377. * the contrary we want to make sure that we don't
  1378. * process receive and transmit LLC frames and update
  1379. * the Type 2 register with bad information.
  1380. */
  1381. bp->cmd_req_reg.lword = 0;
  1382. bp->cmd_rsp_reg.lword = 0;
  1383. bp->rcv_xmt_reg.lword = 0;
  1384. /* Clear consumer block for the same reason given above */
  1385. memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
  1386. /* Release all dynamically allocate skb in the receive ring. */
  1387. dfx_rcv_flush(bp);
  1388. /* Clear device structure flags */
  1389. netif_stop_queue(dev);
  1390. /* Deregister (free) IRQ */
  1391. free_irq(dev->irq, dev);
  1392. return 0;
  1393. }
  1394. /*
  1395. * ======================
  1396. * = dfx_int_pr_halt_id =
  1397. * ======================
  1398. *
  1399. * Overview:
  1400. * Displays halt id's in string form.
  1401. *
  1402. * Returns:
  1403. * None
  1404. *
  1405. * Arguments:
  1406. * bp - pointer to board information
  1407. *
  1408. * Functional Description:
  1409. * Determine current halt id and display appropriate string.
  1410. *
  1411. * Return Codes:
  1412. * None
  1413. *
  1414. * Assumptions:
  1415. * None
  1416. *
  1417. * Side Effects:
  1418. * None
  1419. */
  1420. static void dfx_int_pr_halt_id(DFX_board_t *bp)
  1421. {
  1422. PI_UINT32 port_status; /* PDQ port status register value */
  1423. PI_UINT32 halt_id; /* PDQ port status halt ID */
  1424. /* Read the latest port status */
  1425. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  1426. /* Display halt state transition information */
  1427. halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
  1428. switch (halt_id)
  1429. {
  1430. case PI_HALT_ID_K_SELFTEST_TIMEOUT:
  1431. printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
  1432. break;
  1433. case PI_HALT_ID_K_PARITY_ERROR:
  1434. printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
  1435. break;
  1436. case PI_HALT_ID_K_HOST_DIR_HALT:
  1437. printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
  1438. break;
  1439. case PI_HALT_ID_K_SW_FAULT:
  1440. printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
  1441. break;
  1442. case PI_HALT_ID_K_HW_FAULT:
  1443. printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
  1444. break;
  1445. case PI_HALT_ID_K_PC_TRACE:
  1446. printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
  1447. break;
  1448. case PI_HALT_ID_K_DMA_ERROR:
  1449. printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
  1450. break;
  1451. case PI_HALT_ID_K_IMAGE_CRC_ERROR:
  1452. printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
  1453. break;
  1454. case PI_HALT_ID_K_BUS_EXCEPTION:
  1455. printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
  1456. break;
  1457. default:
  1458. printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
  1459. break;
  1460. }
  1461. }
  1462. /*
  1463. * ==========================
  1464. * = dfx_int_type_0_process =
  1465. * ==========================
  1466. *
  1467. * Overview:
  1468. * Processes Type 0 interrupts.
  1469. *
  1470. * Returns:
  1471. * None
  1472. *
  1473. * Arguments:
  1474. * bp - pointer to board information
  1475. *
  1476. * Functional Description:
  1477. * Processes all enabled Type 0 interrupts. If the reason for the interrupt
  1478. * is a serious fault on the adapter, then an error message is displayed
  1479. * and the adapter is reset.
  1480. *
  1481. * One tricky potential timing window is the rapid succession of "link avail"
  1482. * "link unavail" state change interrupts. The acknowledgement of the Type 0
  1483. * interrupt must be done before reading the state from the Port Status
  1484. * register. This is true because a state change could occur after reading
  1485. * the data, but before acknowledging the interrupt. If this state change
  1486. * does happen, it would be lost because the driver is using the old state,
  1487. * and it will never know about the new state because it subsequently
  1488. * acknowledges the state change interrupt.
  1489. *
  1490. * INCORRECT CORRECT
  1491. * read type 0 int reasons read type 0 int reasons
  1492. * read adapter state ack type 0 interrupts
  1493. * ack type 0 interrupts read adapter state
  1494. * ... process interrupt ... ... process interrupt ...
  1495. *
  1496. * Return Codes:
  1497. * None
  1498. *
  1499. * Assumptions:
  1500. * None
  1501. *
  1502. * Side Effects:
  1503. * An adapter reset may occur if the adapter has any Type 0 error interrupts
  1504. * or if the port status indicates that the adapter is halted. The driver
  1505. * is responsible for reinitializing the adapter with the current CAM
  1506. * contents and adapter filter settings.
  1507. */
  1508. static void dfx_int_type_0_process(DFX_board_t *bp)
  1509. {
  1510. PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
  1511. PI_UINT32 state; /* current adap state (from port status) */
  1512. /*
  1513. * Read host interrupt Type 0 register to determine which Type 0
  1514. * interrupts are pending. Immediately write it back out to clear
  1515. * those interrupts.
  1516. */
  1517. dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
  1518. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
  1519. /* Check for Type 0 error interrupts */
  1520. if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
  1521. PI_TYPE_0_STAT_M_PM_PAR_ERR |
  1522. PI_TYPE_0_STAT_M_BUS_PAR_ERR))
  1523. {
  1524. /* Check for Non-Existent Memory error */
  1525. if (type_0_status & PI_TYPE_0_STAT_M_NXM)
  1526. printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
  1527. /* Check for Packet Memory Parity error */
  1528. if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
  1529. printk("%s: Packet Memory Parity Error\n", bp->dev->name);
  1530. /* Check for Host Bus Parity error */
  1531. if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
  1532. printk("%s: Host Bus Parity Error\n", bp->dev->name);
  1533. /* Reset adapter and bring it back on-line */
  1534. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1535. bp->reset_type = 0; /* rerun on-board diagnostics */
  1536. printk("%s: Resetting adapter...\n", bp->dev->name);
  1537. if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
  1538. {
  1539. printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
  1540. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1541. return;
  1542. }
  1543. printk("%s: Adapter reset successful!\n", bp->dev->name);
  1544. return;
  1545. }
  1546. /* Check for transmit flush interrupt */
  1547. if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
  1548. {
  1549. /* Flush any pending xmt's and acknowledge the flush interrupt */
  1550. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1551. dfx_xmt_flush(bp); /* flush any outstanding packets */
  1552. (void) dfx_hw_port_ctrl_req(bp,
  1553. PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
  1554. 0,
  1555. 0,
  1556. NULL);
  1557. }
  1558. /* Check for adapter state change */
  1559. if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
  1560. {
  1561. /* Get latest adapter state */
  1562. state = dfx_hw_adap_state_rd(bp); /* get adapter state */
  1563. if (state == PI_STATE_K_HALTED)
  1564. {
  1565. /*
  1566. * Adapter has transitioned to HALTED state, try to reset
  1567. * adapter to bring it back on-line. If reset fails,
  1568. * leave the adapter in the broken state.
  1569. */
  1570. printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
  1571. dfx_int_pr_halt_id(bp); /* display halt id as string */
  1572. /* Reset adapter and bring it back on-line */
  1573. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1574. bp->reset_type = 0; /* rerun on-board diagnostics */
  1575. printk("%s: Resetting adapter...\n", bp->dev->name);
  1576. if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
  1577. {
  1578. printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
  1579. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1580. return;
  1581. }
  1582. printk("%s: Adapter reset successful!\n", bp->dev->name);
  1583. }
  1584. else if (state == PI_STATE_K_LINK_AVAIL)
  1585. {
  1586. bp->link_available = PI_K_TRUE; /* set link available flag */
  1587. }
  1588. }
  1589. }
  1590. /*
  1591. * ==================
  1592. * = dfx_int_common =
  1593. * ==================
  1594. *
  1595. * Overview:
  1596. * Interrupt service routine (ISR)
  1597. *
  1598. * Returns:
  1599. * None
  1600. *
  1601. * Arguments:
  1602. * bp - pointer to board information
  1603. *
  1604. * Functional Description:
  1605. * This is the ISR which processes incoming adapter interrupts.
  1606. *
  1607. * Return Codes:
  1608. * None
  1609. *
  1610. * Assumptions:
  1611. * This routine assumes PDQ interrupts have not been disabled.
  1612. * When interrupts are disabled at the PDQ, the Port Status register
  1613. * is automatically cleared. This routine uses the Port Status
  1614. * register value to determine whether a Type 0 interrupt occurred,
  1615. * so it's important that adapter interrupts are not normally
  1616. * enabled/disabled at the PDQ.
  1617. *
  1618. * It's vital that this routine is NOT reentered for the
  1619. * same board and that the OS is not in another section of
  1620. * code (eg. dfx_xmt_queue_pkt) for the same board on a
  1621. * different thread.
  1622. *
  1623. * Side Effects:
  1624. * Pending interrupts are serviced. Depending on the type of
  1625. * interrupt, acknowledging and clearing the interrupt at the
  1626. * PDQ involves writing a register to clear the interrupt bit
  1627. * or updating completion indices.
  1628. */
  1629. static void dfx_int_common(struct net_device *dev)
  1630. {
  1631. DFX_board_t *bp = netdev_priv(dev);
  1632. PI_UINT32 port_status; /* Port Status register */
  1633. /* Process xmt interrupts - frequent case, so always call this routine */
  1634. if(dfx_xmt_done(bp)) /* free consumed xmt packets */
  1635. netif_wake_queue(dev);
  1636. /* Process rcv interrupts - frequent case, so always call this routine */
  1637. dfx_rcv_queue_process(bp); /* service received LLC frames */
  1638. /*
  1639. * Transmit and receive producer and completion indices are updated on the
  1640. * adapter by writing to the Type 2 Producer register. Since the frequent
  1641. * case is that we'll be processing either LLC transmit or receive buffers,
  1642. * we'll optimize I/O writes by doing a single register write here.
  1643. */
  1644. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  1645. /* Read PDQ Port Status register to find out which interrupts need processing */
  1646. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  1647. /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
  1648. if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
  1649. dfx_int_type_0_process(bp); /* process Type 0 interrupts */
  1650. }
  1651. /*
  1652. * =================
  1653. * = dfx_interrupt =
  1654. * =================
  1655. *
  1656. * Overview:
  1657. * Interrupt processing routine
  1658. *
  1659. * Returns:
  1660. * Whether a valid interrupt was seen.
  1661. *
  1662. * Arguments:
  1663. * irq - interrupt vector
  1664. * dev_id - pointer to device information
  1665. *
  1666. * Functional Description:
  1667. * This routine calls the interrupt processing routine for this adapter. It
  1668. * disables and reenables adapter interrupts, as appropriate. We can support
  1669. * shared interrupts since the incoming dev_id pointer provides our device
  1670. * structure context.
  1671. *
  1672. * Return Codes:
  1673. * IRQ_HANDLED - an IRQ was handled.
  1674. * IRQ_NONE - no IRQ was handled.
  1675. *
  1676. * Assumptions:
  1677. * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
  1678. * on Intel-based systems) is done by the operating system outside this
  1679. * routine.
  1680. *
  1681. * System interrupts are enabled through this call.
  1682. *
  1683. * Side Effects:
  1684. * Interrupts are disabled, then reenabled at the adapter.
  1685. */
  1686. static irqreturn_t dfx_interrupt(int irq, void *dev_id)
  1687. {
  1688. struct net_device *dev = dev_id;
  1689. DFX_board_t *bp = netdev_priv(dev);
  1690. struct device *bdev = bp->bus_dev;
  1691. int dfx_bus_pci = dev_is_pci(bdev);
  1692. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  1693. int dfx_bus_tc = DFX_BUS_TC(bdev);
  1694. /* Service adapter interrupts */
  1695. if (dfx_bus_pci) {
  1696. u32 status;
  1697. dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
  1698. if (!(status & PFI_STATUS_M_PDQ_INT))
  1699. return IRQ_NONE;
  1700. spin_lock(&bp->lock);
  1701. /* Disable PDQ-PFI interrupts at PFI */
  1702. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
  1703. PFI_MODE_M_DMA_ENB);
  1704. /* Call interrupt service routine for this adapter */
  1705. dfx_int_common(dev);
  1706. /* Clear PDQ interrupt status bit and reenable interrupts */
  1707. dfx_port_write_long(bp, PFI_K_REG_STATUS,
  1708. PFI_STATUS_M_PDQ_INT);
  1709. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
  1710. (PFI_MODE_M_PDQ_INT_ENB |
  1711. PFI_MODE_M_DMA_ENB));
  1712. spin_unlock(&bp->lock);
  1713. }
  1714. if (dfx_bus_eisa) {
  1715. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  1716. u8 status;
  1717. status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1718. if (!(status & PI_CONFIG_STAT_0_M_PEND))
  1719. return IRQ_NONE;
  1720. spin_lock(&bp->lock);
  1721. /* Disable interrupts at the ESIC */
  1722. status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
  1723. outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1724. /* Call interrupt service routine for this adapter */
  1725. dfx_int_common(dev);
  1726. /* Reenable interrupts at the ESIC */
  1727. status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1728. status |= PI_CONFIG_STAT_0_M_INT_ENB;
  1729. outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1730. spin_unlock(&bp->lock);
  1731. }
  1732. if (dfx_bus_tc) {
  1733. u32 status;
  1734. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status);
  1735. if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING |
  1736. PI_PSTATUS_M_XMT_DATA_PENDING |
  1737. PI_PSTATUS_M_SMT_HOST_PENDING |
  1738. PI_PSTATUS_M_UNSOL_PENDING |
  1739. PI_PSTATUS_M_CMD_RSP_PENDING |
  1740. PI_PSTATUS_M_CMD_REQ_PENDING |
  1741. PI_PSTATUS_M_TYPE_0_PENDING)))
  1742. return IRQ_NONE;
  1743. spin_lock(&bp->lock);
  1744. /* Call interrupt service routine for this adapter */
  1745. dfx_int_common(dev);
  1746. spin_unlock(&bp->lock);
  1747. }
  1748. return IRQ_HANDLED;
  1749. }
  1750. /*
  1751. * =====================
  1752. * = dfx_ctl_get_stats =
  1753. * =====================
  1754. *
  1755. * Overview:
  1756. * Get statistics for FDDI adapter
  1757. *
  1758. * Returns:
  1759. * Pointer to FDDI statistics structure
  1760. *
  1761. * Arguments:
  1762. * dev - pointer to device information
  1763. *
  1764. * Functional Description:
  1765. * Gets current MIB objects from adapter, then
  1766. * returns FDDI statistics structure as defined
  1767. * in if_fddi.h.
  1768. *
  1769. * Note: Since the FDDI statistics structure is
  1770. * still new and the device structure doesn't
  1771. * have an FDDI-specific get statistics handler,
  1772. * we'll return the FDDI statistics structure as
  1773. * a pointer to an Ethernet statistics structure.
  1774. * That way, at least the first part of the statistics
  1775. * structure can be decoded properly, and it allows
  1776. * "smart" applications to perform a second cast to
  1777. * decode the FDDI-specific statistics.
  1778. *
  1779. * We'll have to pay attention to this routine as the
  1780. * device structure becomes more mature and LAN media
  1781. * independent.
  1782. *
  1783. * Return Codes:
  1784. * None
  1785. *
  1786. * Assumptions:
  1787. * None
  1788. *
  1789. * Side Effects:
  1790. * None
  1791. */
  1792. static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
  1793. {
  1794. DFX_board_t *bp = netdev_priv(dev);
  1795. /* Fill the bp->stats structure with driver-maintained counters */
  1796. bp->stats.gen.rx_packets = bp->rcv_total_frames;
  1797. bp->stats.gen.tx_packets = bp->xmt_total_frames;
  1798. bp->stats.gen.rx_bytes = bp->rcv_total_bytes;
  1799. bp->stats.gen.tx_bytes = bp->xmt_total_bytes;
  1800. bp->stats.gen.rx_errors = bp->rcv_crc_errors +
  1801. bp->rcv_frame_status_errors +
  1802. bp->rcv_length_errors;
  1803. bp->stats.gen.tx_errors = bp->xmt_length_errors;
  1804. bp->stats.gen.rx_dropped = bp->rcv_discards;
  1805. bp->stats.gen.tx_dropped = bp->xmt_discards;
  1806. bp->stats.gen.multicast = bp->rcv_multicast_frames;
  1807. bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */
  1808. /* Get FDDI SMT MIB objects */
  1809. bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
  1810. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1811. return (struct net_device_stats *)&bp->stats;
  1812. /* Fill the bp->stats structure with the SMT MIB object values */
  1813. memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
  1814. bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
  1815. bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
  1816. bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
  1817. memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
  1818. bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
  1819. bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
  1820. bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
  1821. bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
  1822. bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
  1823. bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
  1824. bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
  1825. bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
  1826. bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
  1827. bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
  1828. bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
  1829. bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
  1830. bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
  1831. bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
  1832. bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
  1833. bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
  1834. bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
  1835. bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
  1836. bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
  1837. bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
  1838. bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
  1839. bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
  1840. bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
  1841. bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
  1842. memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
  1843. memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
  1844. memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
  1845. memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
  1846. bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
  1847. bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
  1848. bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
  1849. memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
  1850. bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
  1851. bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
  1852. bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
  1853. bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
  1854. bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
  1855. bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
  1856. bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
  1857. bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
  1858. bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
  1859. bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
  1860. bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
  1861. bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
  1862. bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
  1863. bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
  1864. bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
  1865. bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
  1866. memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
  1867. bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
  1868. bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
  1869. bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
  1870. bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
  1871. bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
  1872. bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
  1873. bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
  1874. bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
  1875. bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
  1876. bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
  1877. memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
  1878. memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
  1879. bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
  1880. bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
  1881. bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
  1882. bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
  1883. bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
  1884. bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
  1885. bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
  1886. bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
  1887. bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
  1888. bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
  1889. bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
  1890. bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
  1891. bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
  1892. bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
  1893. bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
  1894. bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
  1895. bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
  1896. bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
  1897. bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
  1898. bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
  1899. bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
  1900. bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
  1901. bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
  1902. bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
  1903. bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
  1904. bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
  1905. /* Get FDDI counters */
  1906. bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
  1907. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1908. return (struct net_device_stats *)&bp->stats;
  1909. /* Fill the bp->stats structure with the FDDI counter values */
  1910. bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
  1911. bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
  1912. bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
  1913. bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
  1914. bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
  1915. bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
  1916. bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
  1917. bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
  1918. bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
  1919. bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
  1920. bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
  1921. return (struct net_device_stats *)&bp->stats;
  1922. }
  1923. /*
  1924. * ==============================
  1925. * = dfx_ctl_set_multicast_list =
  1926. * ==============================
  1927. *
  1928. * Overview:
  1929. * Enable/Disable LLC frame promiscuous mode reception
  1930. * on the adapter and/or update multicast address table.
  1931. *
  1932. * Returns:
  1933. * None
  1934. *
  1935. * Arguments:
  1936. * dev - pointer to device information
  1937. *
  1938. * Functional Description:
  1939. * This routine follows a fairly simple algorithm for setting the
  1940. * adapter filters and CAM:
  1941. *
  1942. * if IFF_PROMISC flag is set
  1943. * enable LLC individual/group promiscuous mode
  1944. * else
  1945. * disable LLC individual/group promiscuous mode
  1946. * if number of incoming multicast addresses >
  1947. * (CAM max size - number of unicast addresses in CAM)
  1948. * enable LLC group promiscuous mode
  1949. * set driver-maintained multicast address count to zero
  1950. * else
  1951. * disable LLC group promiscuous mode
  1952. * set driver-maintained multicast address count to incoming count
  1953. * update adapter CAM
  1954. * update adapter filters
  1955. *
  1956. * Return Codes:
  1957. * None
  1958. *
  1959. * Assumptions:
  1960. * Multicast addresses are presented in canonical (LSB) format.
  1961. *
  1962. * Side Effects:
  1963. * On-board adapter CAM and filters are updated.
  1964. */
  1965. static void dfx_ctl_set_multicast_list(struct net_device *dev)
  1966. {
  1967. DFX_board_t *bp = netdev_priv(dev);
  1968. int i; /* used as index in for loop */
  1969. struct netdev_hw_addr *ha;
  1970. /* Enable LLC frame promiscuous mode, if necessary */
  1971. if (dev->flags & IFF_PROMISC)
  1972. bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
  1973. /* Else, update multicast address table */
  1974. else
  1975. {
  1976. bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
  1977. /*
  1978. * Check whether incoming multicast address count exceeds table size
  1979. *
  1980. * Note: The adapters utilize an on-board 64 entry CAM for
  1981. * supporting perfect filtering of multicast packets
  1982. * and bridge functions when adding unicast addresses.
  1983. * There is no hash function available. To support
  1984. * additional multicast addresses, the all multicast
  1985. * filter (LLC group promiscuous mode) must be enabled.
  1986. *
  1987. * The firmware reserves two CAM entries for SMT-related
  1988. * multicast addresses, which leaves 62 entries available.
  1989. * The following code ensures that we're not being asked
  1990. * to add more than 62 addresses to the CAM. If we are,
  1991. * the driver will enable the all multicast filter.
  1992. * Should the number of multicast addresses drop below
  1993. * the high water mark, the filter will be disabled and
  1994. * perfect filtering will be used.
  1995. */
  1996. if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
  1997. {
  1998. bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
  1999. bp->mc_count = 0; /* Don't add mc addrs to CAM */
  2000. }
  2001. else
  2002. {
  2003. bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
  2004. bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */
  2005. }
  2006. /* Copy addresses to multicast address table, then update adapter CAM */
  2007. i = 0;
  2008. netdev_for_each_mc_addr(ha, dev)
  2009. memcpy(&bp->mc_table[i++ * FDDI_K_ALEN],
  2010. ha->addr, FDDI_K_ALEN);
  2011. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  2012. {
  2013. DBG_printk("%s: Could not update multicast address table!\n", dev->name);
  2014. }
  2015. else
  2016. {
  2017. DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
  2018. }
  2019. }
  2020. /* Update adapter filters */
  2021. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  2022. {
  2023. DBG_printk("%s: Could not update adapter filters!\n", dev->name);
  2024. }
  2025. else
  2026. {
  2027. DBG_printk("%s: Adapter filters updated!\n", dev->name);
  2028. }
  2029. }
  2030. /*
  2031. * ===========================
  2032. * = dfx_ctl_set_mac_address =
  2033. * ===========================
  2034. *
  2035. * Overview:
  2036. * Add node address override (unicast address) to adapter
  2037. * CAM and update dev_addr field in device table.
  2038. *
  2039. * Returns:
  2040. * None
  2041. *
  2042. * Arguments:
  2043. * dev - pointer to device information
  2044. * addr - pointer to sockaddr structure containing unicast address to add
  2045. *
  2046. * Functional Description:
  2047. * The adapter supports node address overrides by adding one or more
  2048. * unicast addresses to the adapter CAM. This is similar to adding
  2049. * multicast addresses. In this routine we'll update the driver and
  2050. * device structures with the new address, then update the adapter CAM
  2051. * to ensure that the adapter will copy and strip frames destined and
  2052. * sourced by that address.
  2053. *
  2054. * Return Codes:
  2055. * Always returns zero.
  2056. *
  2057. * Assumptions:
  2058. * The address pointed to by addr->sa_data is a valid unicast
  2059. * address and is presented in canonical (LSB) format.
  2060. *
  2061. * Side Effects:
  2062. * On-board adapter CAM is updated. On-board adapter filters
  2063. * may be updated.
  2064. */
  2065. static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
  2066. {
  2067. struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
  2068. DFX_board_t *bp = netdev_priv(dev);
  2069. /* Copy unicast address to driver-maintained structs and update count */
  2070. memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
  2071. memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
  2072. bp->uc_count = 1;
  2073. /*
  2074. * Verify we're not exceeding the CAM size by adding unicast address
  2075. *
  2076. * Note: It's possible that before entering this routine we've
  2077. * already filled the CAM with 62 multicast addresses.
  2078. * Since we need to place the node address override into
  2079. * the CAM, we have to check to see that we're not
  2080. * exceeding the CAM size. If we are, we have to enable
  2081. * the LLC group (multicast) promiscuous mode filter as
  2082. * in dfx_ctl_set_multicast_list.
  2083. */
  2084. if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
  2085. {
  2086. bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
  2087. bp->mc_count = 0; /* Don't add mc addrs to CAM */
  2088. /* Update adapter filters */
  2089. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  2090. {
  2091. DBG_printk("%s: Could not update adapter filters!\n", dev->name);
  2092. }
  2093. else
  2094. {
  2095. DBG_printk("%s: Adapter filters updated!\n", dev->name);
  2096. }
  2097. }
  2098. /* Update adapter CAM with new unicast address */
  2099. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  2100. {
  2101. DBG_printk("%s: Could not set new MAC address!\n", dev->name);
  2102. }
  2103. else
  2104. {
  2105. DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
  2106. }
  2107. return 0; /* always return zero */
  2108. }
  2109. /*
  2110. * ======================
  2111. * = dfx_ctl_update_cam =
  2112. * ======================
  2113. *
  2114. * Overview:
  2115. * Procedure to update adapter CAM (Content Addressable Memory)
  2116. * with desired unicast and multicast address entries.
  2117. *
  2118. * Returns:
  2119. * Condition code
  2120. *
  2121. * Arguments:
  2122. * bp - pointer to board information
  2123. *
  2124. * Functional Description:
  2125. * Updates adapter CAM with current contents of board structure
  2126. * unicast and multicast address tables. Since there are only 62
  2127. * free entries in CAM, this routine ensures that the command
  2128. * request buffer is not overrun.
  2129. *
  2130. * Return Codes:
  2131. * DFX_K_SUCCESS - Request succeeded
  2132. * DFX_K_FAILURE - Request failed
  2133. *
  2134. * Assumptions:
  2135. * All addresses being added (unicast and multicast) are in canonical
  2136. * order.
  2137. *
  2138. * Side Effects:
  2139. * On-board adapter CAM is updated.
  2140. */
  2141. static int dfx_ctl_update_cam(DFX_board_t *bp)
  2142. {
  2143. int i; /* used as index */
  2144. PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
  2145. /*
  2146. * Fill in command request information
  2147. *
  2148. * Note: Even though both the unicast and multicast address
  2149. * table entries are stored as contiguous 6 byte entries,
  2150. * the firmware address filter set command expects each
  2151. * entry to be two longwords (8 bytes total). We must be
  2152. * careful to only copy the six bytes of each unicast and
  2153. * multicast table entry into each command entry. This
  2154. * is also why we must first clear the entire command
  2155. * request buffer.
  2156. */
  2157. memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
  2158. bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
  2159. p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
  2160. /* Now add unicast addresses to command request buffer, if any */
  2161. for (i=0; i < (int)bp->uc_count; i++)
  2162. {
  2163. if (i < PI_CMD_ADDR_FILTER_K_SIZE)
  2164. {
  2165. memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
  2166. p_addr++; /* point to next command entry */
  2167. }
  2168. }
  2169. /* Now add multicast addresses to command request buffer, if any */
  2170. for (i=0; i < (int)bp->mc_count; i++)
  2171. {
  2172. if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
  2173. {
  2174. memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
  2175. p_addr++; /* point to next command entry */
  2176. }
  2177. }
  2178. /* Issue command to update adapter CAM, then return */
  2179. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  2180. return DFX_K_FAILURE;
  2181. return DFX_K_SUCCESS;
  2182. }
  2183. /*
  2184. * ==========================
  2185. * = dfx_ctl_update_filters =
  2186. * ==========================
  2187. *
  2188. * Overview:
  2189. * Procedure to update adapter filters with desired
  2190. * filter settings.
  2191. *
  2192. * Returns:
  2193. * Condition code
  2194. *
  2195. * Arguments:
  2196. * bp - pointer to board information
  2197. *
  2198. * Functional Description:
  2199. * Enables or disables filter using current filter settings.
  2200. *
  2201. * Return Codes:
  2202. * DFX_K_SUCCESS - Request succeeded.
  2203. * DFX_K_FAILURE - Request failed.
  2204. *
  2205. * Assumptions:
  2206. * We must always pass up packets destined to the broadcast
  2207. * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
  2208. * broadcast filter enabled.
  2209. *
  2210. * Side Effects:
  2211. * On-board adapter filters are updated.
  2212. */
  2213. static int dfx_ctl_update_filters(DFX_board_t *bp)
  2214. {
  2215. int i = 0; /* used as index */
  2216. /* Fill in command request information */
  2217. bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
  2218. /* Initialize Broadcast filter - * ALWAYS ENABLED * */
  2219. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
  2220. bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
  2221. /* Initialize LLC Individual/Group Promiscuous filter */
  2222. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
  2223. bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
  2224. /* Initialize LLC Group Promiscuous filter */
  2225. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
  2226. bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
  2227. /* Terminate the item code list */
  2228. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
  2229. /* Issue command to update adapter filters, then return */
  2230. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  2231. return DFX_K_FAILURE;
  2232. return DFX_K_SUCCESS;
  2233. }
  2234. /*
  2235. * ======================
  2236. * = dfx_hw_dma_cmd_req =
  2237. * ======================
  2238. *
  2239. * Overview:
  2240. * Sends PDQ DMA command to adapter firmware
  2241. *
  2242. * Returns:
  2243. * Condition code
  2244. *
  2245. * Arguments:
  2246. * bp - pointer to board information
  2247. *
  2248. * Functional Description:
  2249. * The command request and response buffers are posted to the adapter in the manner
  2250. * described in the PDQ Port Specification:
  2251. *
  2252. * 1. Command Response Buffer is posted to adapter.
  2253. * 2. Command Request Buffer is posted to adapter.
  2254. * 3. Command Request consumer index is polled until it indicates that request
  2255. * buffer has been DMA'd to adapter.
  2256. * 4. Command Response consumer index is polled until it indicates that response
  2257. * buffer has been DMA'd from adapter.
  2258. *
  2259. * This ordering ensures that a response buffer is already available for the firmware
  2260. * to use once it's done processing the request buffer.
  2261. *
  2262. * Return Codes:
  2263. * DFX_K_SUCCESS - DMA command succeeded
  2264. * DFX_K_OUTSTATE - Adapter is NOT in proper state
  2265. * DFX_K_HW_TIMEOUT - DMA command timed out
  2266. *
  2267. * Assumptions:
  2268. * Command request buffer has already been filled with desired DMA command.
  2269. *
  2270. * Side Effects:
  2271. * None
  2272. */
  2273. static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
  2274. {
  2275. int status; /* adapter status */
  2276. int timeout_cnt; /* used in for loops */
  2277. /* Make sure the adapter is in a state that we can issue the DMA command in */
  2278. status = dfx_hw_adap_state_rd(bp);
  2279. if ((status == PI_STATE_K_RESET) ||
  2280. (status == PI_STATE_K_HALTED) ||
  2281. (status == PI_STATE_K_DMA_UNAVAIL) ||
  2282. (status == PI_STATE_K_UPGRADE))
  2283. return DFX_K_OUTSTATE;
  2284. /* Put response buffer on the command response queue */
  2285. bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
  2286. ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
  2287. bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
  2288. /* Bump (and wrap) the producer index and write out to register */
  2289. bp->cmd_rsp_reg.index.prod += 1;
  2290. bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
  2291. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
  2292. /* Put request buffer on the command request queue */
  2293. bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
  2294. PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
  2295. bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
  2296. /* Bump (and wrap) the producer index and write out to register */
  2297. bp->cmd_req_reg.index.prod += 1;
  2298. bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
  2299. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
  2300. /*
  2301. * Here we wait for the command request consumer index to be equal
  2302. * to the producer, indicating that the adapter has DMAed the request.
  2303. */
  2304. for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
  2305. {
  2306. if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
  2307. break;
  2308. udelay(100); /* wait for 100 microseconds */
  2309. }
  2310. if (timeout_cnt == 0)
  2311. return DFX_K_HW_TIMEOUT;
  2312. /* Bump (and wrap) the completion index and write out to register */
  2313. bp->cmd_req_reg.index.comp += 1;
  2314. bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
  2315. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
  2316. /*
  2317. * Here we wait for the command response consumer index to be equal
  2318. * to the producer, indicating that the adapter has DMAed the response.
  2319. */
  2320. for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
  2321. {
  2322. if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
  2323. break;
  2324. udelay(100); /* wait for 100 microseconds */
  2325. }
  2326. if (timeout_cnt == 0)
  2327. return DFX_K_HW_TIMEOUT;
  2328. /* Bump (and wrap) the completion index and write out to register */
  2329. bp->cmd_rsp_reg.index.comp += 1;
  2330. bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
  2331. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
  2332. return DFX_K_SUCCESS;
  2333. }
  2334. /*
  2335. * ========================
  2336. * = dfx_hw_port_ctrl_req =
  2337. * ========================
  2338. *
  2339. * Overview:
  2340. * Sends PDQ port control command to adapter firmware
  2341. *
  2342. * Returns:
  2343. * Host data register value in host_data if ptr is not NULL
  2344. *
  2345. * Arguments:
  2346. * bp - pointer to board information
  2347. * command - port control command
  2348. * data_a - port data A register value
  2349. * data_b - port data B register value
  2350. * host_data - ptr to host data register value
  2351. *
  2352. * Functional Description:
  2353. * Send generic port control command to adapter by writing
  2354. * to various PDQ port registers, then polling for completion.
  2355. *
  2356. * Return Codes:
  2357. * DFX_K_SUCCESS - port control command succeeded
  2358. * DFX_K_HW_TIMEOUT - port control command timed out
  2359. *
  2360. * Assumptions:
  2361. * None
  2362. *
  2363. * Side Effects:
  2364. * None
  2365. */
  2366. static int dfx_hw_port_ctrl_req(
  2367. DFX_board_t *bp,
  2368. PI_UINT32 command,
  2369. PI_UINT32 data_a,
  2370. PI_UINT32 data_b,
  2371. PI_UINT32 *host_data
  2372. )
  2373. {
  2374. PI_UINT32 port_cmd; /* Port Control command register value */
  2375. int timeout_cnt; /* used in for loops */
  2376. /* Set Command Error bit in command longword */
  2377. port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
  2378. /* Issue port command to the adapter */
  2379. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
  2380. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
  2381. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
  2382. /* Now wait for command to complete */
  2383. if (command == PI_PCTRL_M_BLAST_FLASH)
  2384. timeout_cnt = 600000; /* set command timeout count to 60 seconds */
  2385. else
  2386. timeout_cnt = 20000; /* set command timeout count to 2 seconds */
  2387. for (; timeout_cnt > 0; timeout_cnt--)
  2388. {
  2389. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
  2390. if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
  2391. break;
  2392. udelay(100); /* wait for 100 microseconds */
  2393. }
  2394. if (timeout_cnt == 0)
  2395. return DFX_K_HW_TIMEOUT;
  2396. /*
  2397. * If the address of host_data is non-zero, assume caller has supplied a
  2398. * non NULL pointer, and return the contents of the HOST_DATA register in
  2399. * it.
  2400. */
  2401. if (host_data != NULL)
  2402. dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
  2403. return DFX_K_SUCCESS;
  2404. }
  2405. /*
  2406. * =====================
  2407. * = dfx_hw_adap_reset =
  2408. * =====================
  2409. *
  2410. * Overview:
  2411. * Resets adapter
  2412. *
  2413. * Returns:
  2414. * None
  2415. *
  2416. * Arguments:
  2417. * bp - pointer to board information
  2418. * type - type of reset to perform
  2419. *
  2420. * Functional Description:
  2421. * Issue soft reset to adapter by writing to PDQ Port Reset
  2422. * register. Use incoming reset type to tell adapter what
  2423. * kind of reset operation to perform.
  2424. *
  2425. * Return Codes:
  2426. * None
  2427. *
  2428. * Assumptions:
  2429. * This routine merely issues a soft reset to the adapter.
  2430. * It is expected that after this routine returns, the caller
  2431. * will appropriately poll the Port Status register for the
  2432. * adapter to enter the proper state.
  2433. *
  2434. * Side Effects:
  2435. * Internal adapter registers are cleared.
  2436. */
  2437. static void dfx_hw_adap_reset(
  2438. DFX_board_t *bp,
  2439. PI_UINT32 type
  2440. )
  2441. {
  2442. /* Set Reset type and assert reset */
  2443. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
  2444. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
  2445. /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
  2446. udelay(20);
  2447. /* Deassert reset */
  2448. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
  2449. }
  2450. /*
  2451. * ========================
  2452. * = dfx_hw_adap_state_rd =
  2453. * ========================
  2454. *
  2455. * Overview:
  2456. * Returns current adapter state
  2457. *
  2458. * Returns:
  2459. * Adapter state per PDQ Port Specification
  2460. *
  2461. * Arguments:
  2462. * bp - pointer to board information
  2463. *
  2464. * Functional Description:
  2465. * Reads PDQ Port Status register and returns adapter state.
  2466. *
  2467. * Return Codes:
  2468. * None
  2469. *
  2470. * Assumptions:
  2471. * None
  2472. *
  2473. * Side Effects:
  2474. * None
  2475. */
  2476. static int dfx_hw_adap_state_rd(DFX_board_t *bp)
  2477. {
  2478. PI_UINT32 port_status; /* Port Status register value */
  2479. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  2480. return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE;
  2481. }
  2482. /*
  2483. * =====================
  2484. * = dfx_hw_dma_uninit =
  2485. * =====================
  2486. *
  2487. * Overview:
  2488. * Brings adapter to DMA_UNAVAILABLE state
  2489. *
  2490. * Returns:
  2491. * Condition code
  2492. *
  2493. * Arguments:
  2494. * bp - pointer to board information
  2495. * type - type of reset to perform
  2496. *
  2497. * Functional Description:
  2498. * Bring adapter to DMA_UNAVAILABLE state by performing the following:
  2499. * 1. Set reset type bit in Port Data A Register then reset adapter.
  2500. * 2. Check that adapter is in DMA_UNAVAILABLE state.
  2501. *
  2502. * Return Codes:
  2503. * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
  2504. * DFX_K_HW_TIMEOUT - adapter did not reset properly
  2505. *
  2506. * Assumptions:
  2507. * None
  2508. *
  2509. * Side Effects:
  2510. * Internal adapter registers are cleared.
  2511. */
  2512. static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
  2513. {
  2514. int timeout_cnt; /* used in for loops */
  2515. /* Set reset type bit and reset adapter */
  2516. dfx_hw_adap_reset(bp, type);
  2517. /* Now wait for adapter to enter DMA_UNAVAILABLE state */
  2518. for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
  2519. {
  2520. if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
  2521. break;
  2522. udelay(100); /* wait for 100 microseconds */
  2523. }
  2524. if (timeout_cnt == 0)
  2525. return DFX_K_HW_TIMEOUT;
  2526. return DFX_K_SUCCESS;
  2527. }
  2528. /*
  2529. * Align an sk_buff to a boundary power of 2
  2530. *
  2531. */
  2532. #ifdef DYNAMIC_BUFFERS
  2533. static void my_skb_align(struct sk_buff *skb, int n)
  2534. {
  2535. unsigned long x = (unsigned long)skb->data;
  2536. unsigned long v;
  2537. v = ALIGN(x, n); /* Where we want to be */
  2538. skb_reserve(skb, v - x);
  2539. }
  2540. #endif
  2541. /*
  2542. * ================
  2543. * = dfx_rcv_init =
  2544. * ================
  2545. *
  2546. * Overview:
  2547. * Produces buffers to adapter LLC Host receive descriptor block
  2548. *
  2549. * Returns:
  2550. * None
  2551. *
  2552. * Arguments:
  2553. * bp - pointer to board information
  2554. * get_buffers - non-zero if buffers to be allocated
  2555. *
  2556. * Functional Description:
  2557. * This routine can be called during dfx_adap_init() or during an adapter
  2558. * reset. It initializes the descriptor block and produces all allocated
  2559. * LLC Host queue receive buffers.
  2560. *
  2561. * Return Codes:
  2562. * Return 0 on success or -ENOMEM if buffer allocation failed (when using
  2563. * dynamic buffer allocation). If the buffer allocation failed, the
  2564. * already allocated buffers will not be released and the caller should do
  2565. * this.
  2566. *
  2567. * Assumptions:
  2568. * The PDQ has been reset and the adapter and driver maintained Type 2
  2569. * register indices are cleared.
  2570. *
  2571. * Side Effects:
  2572. * Receive buffers are posted to the adapter LLC queue and the adapter
  2573. * is notified.
  2574. */
  2575. static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
  2576. {
  2577. int i, j; /* used in for loop */
  2578. /*
  2579. * Since each receive buffer is a single fragment of same length, initialize
  2580. * first longword in each receive descriptor for entire LLC Host descriptor
  2581. * block. Also initialize second longword in each receive descriptor with
  2582. * physical address of receive buffer. We'll always allocate receive
  2583. * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
  2584. * block and produce new receive buffers by simply updating the receive
  2585. * producer index.
  2586. *
  2587. * Assumptions:
  2588. * To support all shipping versions of PDQ, the receive buffer size
  2589. * must be mod 128 in length and the physical address must be 128 byte
  2590. * aligned. In other words, bits 0-6 of the length and address must
  2591. * be zero for the following descriptor field entries to be correct on
  2592. * all PDQ-based boards. We guaranteed both requirements during
  2593. * driver initialization when we allocated memory for the receive buffers.
  2594. */
  2595. if (get_buffers) {
  2596. #ifdef DYNAMIC_BUFFERS
  2597. for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
  2598. for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  2599. {
  2600. struct sk_buff *newskb;
  2601. dma_addr_t dma_addr;
  2602. newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE,
  2603. GFP_NOIO);
  2604. if (!newskb)
  2605. return -ENOMEM;
  2606. /*
  2607. * align to 128 bytes for compatibility with
  2608. * the old EISA boards.
  2609. */
  2610. my_skb_align(newskb, 128);
  2611. dma_addr = dma_map_single(bp->bus_dev,
  2612. newskb->data,
  2613. PI_RCV_DATA_K_SIZE_MAX,
  2614. DMA_FROM_DEVICE);
  2615. if (dma_mapping_error(bp->bus_dev, dma_addr)) {
  2616. dev_kfree_skb(newskb);
  2617. return -ENOMEM;
  2618. }
  2619. bp->descr_block_virt->rcv_data[i + j].long_0 =
  2620. (u32)(PI_RCV_DESCR_M_SOP |
  2621. ((PI_RCV_DATA_K_SIZE_MAX /
  2622. PI_ALIGN_K_RCV_DATA_BUFF) <<
  2623. PI_RCV_DESCR_V_SEG_LEN));
  2624. bp->descr_block_virt->rcv_data[i + j].long_1 =
  2625. (u32)dma_addr;
  2626. /*
  2627. * p_rcv_buff_va is only used inside the
  2628. * kernel so we put the skb pointer here.
  2629. */
  2630. bp->p_rcv_buff_va[i+j] = (char *) newskb;
  2631. }
  2632. #else
  2633. for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
  2634. for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  2635. {
  2636. bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
  2637. ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
  2638. bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
  2639. bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
  2640. }
  2641. #endif
  2642. }
  2643. /* Update receive producer and Type 2 register */
  2644. bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
  2645. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  2646. return 0;
  2647. }
  2648. /*
  2649. * =========================
  2650. * = dfx_rcv_queue_process =
  2651. * =========================
  2652. *
  2653. * Overview:
  2654. * Process received LLC frames.
  2655. *
  2656. * Returns:
  2657. * None
  2658. *
  2659. * Arguments:
  2660. * bp - pointer to board information
  2661. *
  2662. * Functional Description:
  2663. * Received LLC frames are processed until there are no more consumed frames.
  2664. * Once all frames are processed, the receive buffers are returned to the
  2665. * adapter. Note that this algorithm fixes the length of time that can be spent
  2666. * in this routine, because there are a fixed number of receive buffers to
  2667. * process and buffers are not produced until this routine exits and returns
  2668. * to the ISR.
  2669. *
  2670. * Return Codes:
  2671. * None
  2672. *
  2673. * Assumptions:
  2674. * None
  2675. *
  2676. * Side Effects:
  2677. * None
  2678. */
  2679. static void dfx_rcv_queue_process(
  2680. DFX_board_t *bp
  2681. )
  2682. {
  2683. PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
  2684. char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
  2685. u32 descr, pkt_len; /* FMC descriptor field and packet length */
  2686. struct sk_buff *skb = NULL; /* pointer to a sk_buff to hold incoming packet data */
  2687. /* Service all consumed LLC receive frames */
  2688. p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
  2689. while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
  2690. {
  2691. /* Process any errors */
  2692. dma_addr_t dma_addr;
  2693. int entry;
  2694. entry = bp->rcv_xmt_reg.index.rcv_comp;
  2695. #ifdef DYNAMIC_BUFFERS
  2696. p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
  2697. #else
  2698. p_buff = bp->p_rcv_buff_va[entry];
  2699. #endif
  2700. dma_addr = bp->descr_block_virt->rcv_data[entry].long_1;
  2701. dma_sync_single_for_cpu(bp->bus_dev,
  2702. dma_addr + RCV_BUFF_K_DESCR,
  2703. sizeof(u32),
  2704. DMA_FROM_DEVICE);
  2705. memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
  2706. if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
  2707. {
  2708. if (descr & PI_FMC_DESCR_M_RCC_CRC)
  2709. bp->rcv_crc_errors++;
  2710. else
  2711. bp->rcv_frame_status_errors++;
  2712. }
  2713. else
  2714. {
  2715. int rx_in_place = 0;
  2716. /* The frame was received without errors - verify packet length */
  2717. pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
  2718. pkt_len -= 4; /* subtract 4 byte CRC */
  2719. if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
  2720. bp->rcv_length_errors++;
  2721. else{
  2722. #ifdef DYNAMIC_BUFFERS
  2723. struct sk_buff *newskb = NULL;
  2724. if (pkt_len > SKBUFF_RX_COPYBREAK) {
  2725. dma_addr_t new_dma_addr;
  2726. newskb = netdev_alloc_skb(bp->dev,
  2727. NEW_SKB_SIZE);
  2728. if (newskb){
  2729. my_skb_align(newskb, 128);
  2730. new_dma_addr = dma_map_single(
  2731. bp->bus_dev,
  2732. newskb->data,
  2733. PI_RCV_DATA_K_SIZE_MAX,
  2734. DMA_FROM_DEVICE);
  2735. if (dma_mapping_error(
  2736. bp->bus_dev,
  2737. new_dma_addr)) {
  2738. dev_kfree_skb(newskb);
  2739. newskb = NULL;
  2740. }
  2741. }
  2742. if (newskb) {
  2743. rx_in_place = 1;
  2744. skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
  2745. dma_unmap_single(bp->bus_dev,
  2746. dma_addr,
  2747. PI_RCV_DATA_K_SIZE_MAX,
  2748. DMA_FROM_DEVICE);
  2749. skb_reserve(skb, RCV_BUFF_K_PADDING);
  2750. bp->p_rcv_buff_va[entry] = (char *)newskb;
  2751. bp->descr_block_virt->rcv_data[entry].long_1 = (u32)new_dma_addr;
  2752. }
  2753. }
  2754. if (!newskb)
  2755. #endif
  2756. /* Alloc new buffer to pass up,
  2757. * add room for PRH. */
  2758. skb = netdev_alloc_skb(bp->dev,
  2759. pkt_len + 3);
  2760. if (skb == NULL)
  2761. {
  2762. printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
  2763. bp->rcv_discards++;
  2764. break;
  2765. }
  2766. else {
  2767. if (!rx_in_place) {
  2768. /* Receive buffer allocated, pass receive packet up */
  2769. dma_sync_single_for_cpu(
  2770. bp->bus_dev,
  2771. dma_addr +
  2772. RCV_BUFF_K_PADDING,
  2773. pkt_len + 3,
  2774. DMA_FROM_DEVICE);
  2775. skb_copy_to_linear_data(skb,
  2776. p_buff + RCV_BUFF_K_PADDING,
  2777. pkt_len + 3);
  2778. }
  2779. skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
  2780. skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
  2781. skb->protocol = fddi_type_trans(skb, bp->dev);
  2782. bp->rcv_total_bytes += skb->len;
  2783. netif_rx(skb);
  2784. /* Update the rcv counters */
  2785. bp->rcv_total_frames++;
  2786. if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
  2787. bp->rcv_multicast_frames++;
  2788. }
  2789. }
  2790. }
  2791. /*
  2792. * Advance the producer (for recycling) and advance the completion
  2793. * (for servicing received frames). Note that it is okay to
  2794. * advance the producer without checking that it passes the
  2795. * completion index because they are both advanced at the same
  2796. * rate.
  2797. */
  2798. bp->rcv_xmt_reg.index.rcv_prod += 1;
  2799. bp->rcv_xmt_reg.index.rcv_comp += 1;
  2800. }
  2801. }
  2802. /*
  2803. * =====================
  2804. * = dfx_xmt_queue_pkt =
  2805. * =====================
  2806. *
  2807. * Overview:
  2808. * Queues packets for transmission
  2809. *
  2810. * Returns:
  2811. * Condition code
  2812. *
  2813. * Arguments:
  2814. * skb - pointer to sk_buff to queue for transmission
  2815. * dev - pointer to device information
  2816. *
  2817. * Functional Description:
  2818. * Here we assume that an incoming skb transmit request
  2819. * is contained in a single physically contiguous buffer
  2820. * in which the virtual address of the start of packet
  2821. * (skb->data) can be converted to a physical address
  2822. * by using pci_map_single().
  2823. *
  2824. * Since the adapter architecture requires a three byte
  2825. * packet request header to prepend the start of packet,
  2826. * we'll write the three byte field immediately prior to
  2827. * the FC byte. This assumption is valid because we've
  2828. * ensured that dev->hard_header_len includes three pad
  2829. * bytes. By posting a single fragment to the adapter,
  2830. * we'll reduce the number of descriptor fetches and
  2831. * bus traffic needed to send the request.
  2832. *
  2833. * Also, we can't free the skb until after it's been DMA'd
  2834. * out by the adapter, so we'll queue it in the driver and
  2835. * return it in dfx_xmt_done.
  2836. *
  2837. * Return Codes:
  2838. * 0 - driver queued packet, link is unavailable, or skbuff was bad
  2839. * 1 - caller should requeue the sk_buff for later transmission
  2840. *
  2841. * Assumptions:
  2842. * First and foremost, we assume the incoming skb pointer
  2843. * is NOT NULL and is pointing to a valid sk_buff structure.
  2844. *
  2845. * The outgoing packet is complete, starting with the
  2846. * frame control byte including the last byte of data,
  2847. * but NOT including the 4 byte CRC. We'll let the
  2848. * adapter hardware generate and append the CRC.
  2849. *
  2850. * The entire packet is stored in one physically
  2851. * contiguous buffer which is not cached and whose
  2852. * 32-bit physical address can be determined.
  2853. *
  2854. * It's vital that this routine is NOT reentered for the
  2855. * same board and that the OS is not in another section of
  2856. * code (eg. dfx_int_common) for the same board on a
  2857. * different thread.
  2858. *
  2859. * Side Effects:
  2860. * None
  2861. */
  2862. static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb,
  2863. struct net_device *dev)
  2864. {
  2865. DFX_board_t *bp = netdev_priv(dev);
  2866. u8 prod; /* local transmit producer index */
  2867. PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
  2868. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  2869. dma_addr_t dma_addr;
  2870. unsigned long flags;
  2871. netif_stop_queue(dev);
  2872. /*
  2873. * Verify that incoming transmit request is OK
  2874. *
  2875. * Note: The packet size check is consistent with other
  2876. * Linux device drivers, although the correct packet
  2877. * size should be verified before calling the
  2878. * transmit routine.
  2879. */
  2880. if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
  2881. {
  2882. printk("%s: Invalid packet length - %u bytes\n",
  2883. dev->name, skb->len);
  2884. bp->xmt_length_errors++; /* bump error counter */
  2885. netif_wake_queue(dev);
  2886. dev_kfree_skb(skb);
  2887. return NETDEV_TX_OK; /* return "success" */
  2888. }
  2889. /*
  2890. * See if adapter link is available, if not, free buffer
  2891. *
  2892. * Note: If the link isn't available, free buffer and return 0
  2893. * rather than tell the upper layer to requeue the packet.
  2894. * The methodology here is that by the time the link
  2895. * becomes available, the packet to be sent will be
  2896. * fairly stale. By simply dropping the packet, the
  2897. * higher layer protocols will eventually time out
  2898. * waiting for response packets which it won't receive.
  2899. */
  2900. if (bp->link_available == PI_K_FALSE)
  2901. {
  2902. if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
  2903. bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
  2904. else
  2905. {
  2906. bp->xmt_discards++; /* bump error counter */
  2907. dev_kfree_skb(skb); /* free sk_buff now */
  2908. netif_wake_queue(dev);
  2909. return NETDEV_TX_OK; /* return "success" */
  2910. }
  2911. }
  2912. /* Write the three PRH bytes immediately before the FC byte */
  2913. skb_push(skb, 3);
  2914. skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
  2915. skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
  2916. skb->data[2] = DFX_PRH2_BYTE; /* specification */
  2917. dma_addr = dma_map_single(bp->bus_dev, skb->data, skb->len,
  2918. DMA_TO_DEVICE);
  2919. if (dma_mapping_error(bp->bus_dev, dma_addr)) {
  2920. skb_pull(skb, 3);
  2921. return NETDEV_TX_BUSY;
  2922. }
  2923. spin_lock_irqsave(&bp->lock, flags);
  2924. /* Get the current producer and the next free xmt data descriptor */
  2925. prod = bp->rcv_xmt_reg.index.xmt_prod;
  2926. p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
  2927. /*
  2928. * Get pointer to auxiliary queue entry to contain information
  2929. * for this packet.
  2930. *
  2931. * Note: The current xmt producer index will become the
  2932. * current xmt completion index when we complete this
  2933. * packet later on. So, we'll get the pointer to the
  2934. * next auxiliary queue entry now before we bump the
  2935. * producer index.
  2936. */
  2937. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
  2938. /*
  2939. * Write the descriptor with buffer info and bump producer
  2940. *
  2941. * Note: Since we need to start DMA from the packet request
  2942. * header, we'll add 3 bytes to the DMA buffer length,
  2943. * and we'll determine the physical address of the
  2944. * buffer from the PRH, not skb->data.
  2945. *
  2946. * Assumptions:
  2947. * 1. Packet starts with the frame control (FC) byte
  2948. * at skb->data.
  2949. * 2. The 4-byte CRC is not appended to the buffer or
  2950. * included in the length.
  2951. * 3. Packet length (skb->len) is from FC to end of
  2952. * data, inclusive.
  2953. * 4. The packet length does not exceed the maximum
  2954. * FDDI LLC frame length of 4491 bytes.
  2955. * 5. The entire packet is contained in a physically
  2956. * contiguous, non-cached, locked memory space
  2957. * comprised of a single buffer pointed to by
  2958. * skb->data.
  2959. * 6. The physical address of the start of packet
  2960. * can be determined from the virtual address
  2961. * by using pci_map_single() and is only 32-bits
  2962. * wide.
  2963. */
  2964. p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
  2965. p_xmt_descr->long_1 = (u32)dma_addr;
  2966. /*
  2967. * Verify that descriptor is actually available
  2968. *
  2969. * Note: If descriptor isn't available, return 1 which tells
  2970. * the upper layer to requeue the packet for later
  2971. * transmission.
  2972. *
  2973. * We need to ensure that the producer never reaches the
  2974. * completion, except to indicate that the queue is empty.
  2975. */
  2976. if (prod == bp->rcv_xmt_reg.index.xmt_comp)
  2977. {
  2978. skb_pull(skb,3);
  2979. spin_unlock_irqrestore(&bp->lock, flags);
  2980. return NETDEV_TX_BUSY; /* requeue packet for later */
  2981. }
  2982. /*
  2983. * Save info for this packet for xmt done indication routine
  2984. *
  2985. * Normally, we'd save the producer index in the p_xmt_drv_descr
  2986. * structure so that we'd have it handy when we complete this
  2987. * packet later (in dfx_xmt_done). However, since the current
  2988. * transmit architecture guarantees a single fragment for the
  2989. * entire packet, we can simply bump the completion index by
  2990. * one (1) for each completed packet.
  2991. *
  2992. * Note: If this assumption changes and we're presented with
  2993. * an inconsistent number of transmit fragments for packet
  2994. * data, we'll need to modify this code to save the current
  2995. * transmit producer index.
  2996. */
  2997. p_xmt_drv_descr->p_skb = skb;
  2998. /* Update Type 2 register */
  2999. bp->rcv_xmt_reg.index.xmt_prod = prod;
  3000. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  3001. spin_unlock_irqrestore(&bp->lock, flags);
  3002. netif_wake_queue(dev);
  3003. return NETDEV_TX_OK; /* packet queued to adapter */
  3004. }
  3005. /*
  3006. * ================
  3007. * = dfx_xmt_done =
  3008. * ================
  3009. *
  3010. * Overview:
  3011. * Processes all frames that have been transmitted.
  3012. *
  3013. * Returns:
  3014. * None
  3015. *
  3016. * Arguments:
  3017. * bp - pointer to board information
  3018. *
  3019. * Functional Description:
  3020. * For all consumed transmit descriptors that have not
  3021. * yet been completed, we'll free the skb we were holding
  3022. * onto using dev_kfree_skb and bump the appropriate
  3023. * counters.
  3024. *
  3025. * Return Codes:
  3026. * None
  3027. *
  3028. * Assumptions:
  3029. * The Type 2 register is not updated in this routine. It is
  3030. * assumed that it will be updated in the ISR when dfx_xmt_done
  3031. * returns.
  3032. *
  3033. * Side Effects:
  3034. * None
  3035. */
  3036. static int dfx_xmt_done(DFX_board_t *bp)
  3037. {
  3038. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  3039. PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
  3040. u8 comp; /* local transmit completion index */
  3041. int freed = 0; /* buffers freed */
  3042. /* Service all consumed transmit frames */
  3043. p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
  3044. while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
  3045. {
  3046. /* Get pointer to the transmit driver descriptor block information */
  3047. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
  3048. /* Increment transmit counters */
  3049. bp->xmt_total_frames++;
  3050. bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
  3051. /* Return skb to operating system */
  3052. comp = bp->rcv_xmt_reg.index.xmt_comp;
  3053. dma_unmap_single(bp->bus_dev,
  3054. bp->descr_block_virt->xmt_data[comp].long_1,
  3055. p_xmt_drv_descr->p_skb->len,
  3056. DMA_TO_DEVICE);
  3057. dev_consume_skb_irq(p_xmt_drv_descr->p_skb);
  3058. /*
  3059. * Move to start of next packet by updating completion index
  3060. *
  3061. * Here we assume that a transmit packet request is always
  3062. * serviced by posting one fragment. We can therefore
  3063. * simplify the completion code by incrementing the
  3064. * completion index by one. This code will need to be
  3065. * modified if this assumption changes. See comments
  3066. * in dfx_xmt_queue_pkt for more details.
  3067. */
  3068. bp->rcv_xmt_reg.index.xmt_comp += 1;
  3069. freed++;
  3070. }
  3071. return freed;
  3072. }
  3073. /*
  3074. * =================
  3075. * = dfx_rcv_flush =
  3076. * =================
  3077. *
  3078. * Overview:
  3079. * Remove all skb's in the receive ring.
  3080. *
  3081. * Returns:
  3082. * None
  3083. *
  3084. * Arguments:
  3085. * bp - pointer to board information
  3086. *
  3087. * Functional Description:
  3088. * Free's all the dynamically allocated skb's that are
  3089. * currently attached to the device receive ring. This
  3090. * function is typically only used when the device is
  3091. * initialized or reinitialized.
  3092. *
  3093. * Return Codes:
  3094. * None
  3095. *
  3096. * Side Effects:
  3097. * None
  3098. */
  3099. #ifdef DYNAMIC_BUFFERS
  3100. static void dfx_rcv_flush( DFX_board_t *bp )
  3101. {
  3102. int i, j;
  3103. for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
  3104. for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  3105. {
  3106. struct sk_buff *skb;
  3107. skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
  3108. if (skb) {
  3109. dma_unmap_single(bp->bus_dev,
  3110. bp->descr_block_virt->rcv_data[i+j].long_1,
  3111. PI_RCV_DATA_K_SIZE_MAX,
  3112. DMA_FROM_DEVICE);
  3113. dev_kfree_skb(skb);
  3114. }
  3115. bp->p_rcv_buff_va[i+j] = NULL;
  3116. }
  3117. }
  3118. #endif /* DYNAMIC_BUFFERS */
  3119. /*
  3120. * =================
  3121. * = dfx_xmt_flush =
  3122. * =================
  3123. *
  3124. * Overview:
  3125. * Processes all frames whether they've been transmitted
  3126. * or not.
  3127. *
  3128. * Returns:
  3129. * None
  3130. *
  3131. * Arguments:
  3132. * bp - pointer to board information
  3133. *
  3134. * Functional Description:
  3135. * For all produced transmit descriptors that have not
  3136. * yet been completed, we'll free the skb we were holding
  3137. * onto using dev_kfree_skb and bump the appropriate
  3138. * counters. Of course, it's possible that some of
  3139. * these transmit requests actually did go out, but we
  3140. * won't make that distinction here. Finally, we'll
  3141. * update the consumer index to match the producer.
  3142. *
  3143. * Return Codes:
  3144. * None
  3145. *
  3146. * Assumptions:
  3147. * This routine does NOT update the Type 2 register. It
  3148. * is assumed that this routine is being called during a
  3149. * transmit flush interrupt, or a shutdown or close routine.
  3150. *
  3151. * Side Effects:
  3152. * None
  3153. */
  3154. static void dfx_xmt_flush( DFX_board_t *bp )
  3155. {
  3156. u32 prod_cons; /* rcv/xmt consumer block longword */
  3157. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  3158. u8 comp; /* local transmit completion index */
  3159. /* Flush all outstanding transmit frames */
  3160. while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
  3161. {
  3162. /* Get pointer to the transmit driver descriptor block information */
  3163. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
  3164. /* Return skb to operating system */
  3165. comp = bp->rcv_xmt_reg.index.xmt_comp;
  3166. dma_unmap_single(bp->bus_dev,
  3167. bp->descr_block_virt->xmt_data[comp].long_1,
  3168. p_xmt_drv_descr->p_skb->len,
  3169. DMA_TO_DEVICE);
  3170. dev_kfree_skb(p_xmt_drv_descr->p_skb);
  3171. /* Increment transmit error counter */
  3172. bp->xmt_discards++;
  3173. /*
  3174. * Move to start of next packet by updating completion index
  3175. *
  3176. * Here we assume that a transmit packet request is always
  3177. * serviced by posting one fragment. We can therefore
  3178. * simplify the completion code by incrementing the
  3179. * completion index by one. This code will need to be
  3180. * modified if this assumption changes. See comments
  3181. * in dfx_xmt_queue_pkt for more details.
  3182. */
  3183. bp->rcv_xmt_reg.index.xmt_comp += 1;
  3184. }
  3185. /* Update the transmit consumer index in the consumer block */
  3186. prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
  3187. prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
  3188. bp->cons_block_virt->xmt_rcv_data = prod_cons;
  3189. }
  3190. /*
  3191. * ==================
  3192. * = dfx_unregister =
  3193. * ==================
  3194. *
  3195. * Overview:
  3196. * Shuts down an FDDI controller
  3197. *
  3198. * Returns:
  3199. * Condition code
  3200. *
  3201. * Arguments:
  3202. * bdev - pointer to device information
  3203. *
  3204. * Functional Description:
  3205. *
  3206. * Return Codes:
  3207. * None
  3208. *
  3209. * Assumptions:
  3210. * It compiles so it should work :-( (PCI cards do :-)
  3211. *
  3212. * Side Effects:
  3213. * Device structures for FDDI adapters (fddi0, fddi1, etc) are
  3214. * freed.
  3215. */
  3216. static void dfx_unregister(struct device *bdev)
  3217. {
  3218. struct net_device *dev = dev_get_drvdata(bdev);
  3219. DFX_board_t *bp = netdev_priv(dev);
  3220. int dfx_bus_pci = dev_is_pci(bdev);
  3221. int dfx_bus_tc = DFX_BUS_TC(bdev);
  3222. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  3223. resource_size_t bar_start[3] = {0}; /* pointers to ports */
  3224. resource_size_t bar_len[3] = {0}; /* resource lengths */
  3225. int alloc_size; /* total buffer size used */
  3226. unregister_netdev(dev);
  3227. alloc_size = sizeof(PI_DESCR_BLOCK) +
  3228. PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
  3229. #ifndef DYNAMIC_BUFFERS
  3230. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  3231. #endif
  3232. sizeof(PI_CONSUMER_BLOCK) +
  3233. (PI_ALIGN_K_DESC_BLK - 1);
  3234. if (bp->kmalloced)
  3235. dma_free_coherent(bdev, alloc_size,
  3236. bp->kmalloced, bp->kmalloced_dma);
  3237. dfx_bus_uninit(dev);
  3238. dfx_get_bars(bdev, bar_start, bar_len);
  3239. if (bar_start[2] != 0)
  3240. release_region(bar_start[2], bar_len[2]);
  3241. if (bar_start[1] != 0)
  3242. release_region(bar_start[1], bar_len[1]);
  3243. if (dfx_use_mmio) {
  3244. iounmap(bp->base.mem);
  3245. release_mem_region(bar_start[0], bar_len[0]);
  3246. } else
  3247. release_region(bar_start[0], bar_len[0]);
  3248. if (dfx_bus_pci)
  3249. pci_disable_device(to_pci_dev(bdev));
  3250. free_netdev(dev);
  3251. }
  3252. static int __maybe_unused dfx_dev_register(struct device *);
  3253. static int __maybe_unused dfx_dev_unregister(struct device *);
  3254. #ifdef CONFIG_PCI
  3255. static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *);
  3256. static void dfx_pci_unregister(struct pci_dev *);
  3257. static const struct pci_device_id dfx_pci_table[] = {
  3258. { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) },
  3259. { }
  3260. };
  3261. MODULE_DEVICE_TABLE(pci, dfx_pci_table);
  3262. static struct pci_driver dfx_pci_driver = {
  3263. .name = "defxx",
  3264. .id_table = dfx_pci_table,
  3265. .probe = dfx_pci_register,
  3266. .remove = dfx_pci_unregister,
  3267. };
  3268. static int dfx_pci_register(struct pci_dev *pdev,
  3269. const struct pci_device_id *ent)
  3270. {
  3271. return dfx_register(&pdev->dev);
  3272. }
  3273. static void dfx_pci_unregister(struct pci_dev *pdev)
  3274. {
  3275. dfx_unregister(&pdev->dev);
  3276. }
  3277. #endif /* CONFIG_PCI */
  3278. #ifdef CONFIG_EISA
  3279. static const struct eisa_device_id dfx_eisa_table[] = {
  3280. { "DEC3001", DEFEA_PROD_ID_1 },
  3281. { "DEC3002", DEFEA_PROD_ID_2 },
  3282. { "DEC3003", DEFEA_PROD_ID_3 },
  3283. { "DEC3004", DEFEA_PROD_ID_4 },
  3284. { }
  3285. };
  3286. MODULE_DEVICE_TABLE(eisa, dfx_eisa_table);
  3287. static struct eisa_driver dfx_eisa_driver = {
  3288. .id_table = dfx_eisa_table,
  3289. .driver = {
  3290. .name = "defxx",
  3291. .bus = &eisa_bus_type,
  3292. .probe = dfx_dev_register,
  3293. .remove = dfx_dev_unregister,
  3294. },
  3295. };
  3296. #endif /* CONFIG_EISA */
  3297. #ifdef CONFIG_TC
  3298. static struct tc_device_id const dfx_tc_table[] = {
  3299. { "DEC ", "PMAF-FA " },
  3300. { "DEC ", "PMAF-FD " },
  3301. { "DEC ", "PMAF-FS " },
  3302. { "DEC ", "PMAF-FU " },
  3303. { }
  3304. };
  3305. MODULE_DEVICE_TABLE(tc, dfx_tc_table);
  3306. static struct tc_driver dfx_tc_driver = {
  3307. .id_table = dfx_tc_table,
  3308. .driver = {
  3309. .name = "defxx",
  3310. .bus = &tc_bus_type,
  3311. .probe = dfx_dev_register,
  3312. .remove = dfx_dev_unregister,
  3313. },
  3314. };
  3315. #endif /* CONFIG_TC */
  3316. static int __maybe_unused dfx_dev_register(struct device *dev)
  3317. {
  3318. int status;
  3319. status = dfx_register(dev);
  3320. if (!status)
  3321. get_device(dev);
  3322. return status;
  3323. }
  3324. static int __maybe_unused dfx_dev_unregister(struct device *dev)
  3325. {
  3326. put_device(dev);
  3327. dfx_unregister(dev);
  3328. return 0;
  3329. }
  3330. static int dfx_init(void)
  3331. {
  3332. int status;
  3333. status = pci_register_driver(&dfx_pci_driver);
  3334. if (!status)
  3335. status = eisa_driver_register(&dfx_eisa_driver);
  3336. if (!status)
  3337. status = tc_register_driver(&dfx_tc_driver);
  3338. return status;
  3339. }
  3340. static void dfx_cleanup(void)
  3341. {
  3342. tc_unregister_driver(&dfx_tc_driver);
  3343. eisa_driver_unregister(&dfx_eisa_driver);
  3344. pci_unregister_driver(&dfx_pci_driver);
  3345. }
  3346. module_init(dfx_init);
  3347. module_exit(dfx_cleanup);
  3348. MODULE_AUTHOR("Lawrence V. Stefani");
  3349. MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver "
  3350. DRV_VERSION " " DRV_RELDATE);
  3351. MODULE_LICENSE("GPL");