jedec_probe.c 57 KB

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  1. /*
  2. Common Flash Interface probe code.
  3. (C) 2000 Red Hat. GPL'd.
  4. See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
  5. for the standard this probe goes back to.
  6. Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/types.h>
  11. #include <linux/kernel.h>
  12. #include <asm/io.h>
  13. #include <asm/byteorder.h>
  14. #include <linux/errno.h>
  15. #include <linux/slab.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/map.h>
  19. #include <linux/mtd/cfi.h>
  20. #include <linux/mtd/gen_probe.h>
  21. /* AMD */
  22. #define AM29DL800BB 0x22CB
  23. #define AM29DL800BT 0x224A
  24. #define AM29F800BB 0x2258
  25. #define AM29F800BT 0x22D6
  26. #define AM29LV400BB 0x22BA
  27. #define AM29LV400BT 0x22B9
  28. #define AM29LV800BB 0x225B
  29. #define AM29LV800BT 0x22DA
  30. #define AM29LV160DT 0x22C4
  31. #define AM29LV160DB 0x2249
  32. #define AM29F017D 0x003D
  33. #define AM29F016D 0x00AD
  34. #define AM29F080 0x00D5
  35. #define AM29F040 0x00A4
  36. #define AM29LV040B 0x004F
  37. #define AM29F032B 0x0041
  38. #define AM29F002T 0x00B0
  39. #define AM29SL800DB 0x226B
  40. #define AM29SL800DT 0x22EA
  41. /* Atmel */
  42. #define AT49BV512 0x0003
  43. #define AT29LV512 0x003d
  44. #define AT49BV16X 0x00C0
  45. #define AT49BV16XT 0x00C2
  46. #define AT49BV32X 0x00C8
  47. #define AT49BV32XT 0x00C9
  48. /* Eon */
  49. #define EN29LV400AT 0x22B9
  50. #define EN29LV400AB 0x22BA
  51. #define EN29SL800BB 0x226B
  52. #define EN29SL800BT 0x22EA
  53. /* Fujitsu */
  54. #define MBM29F040C 0x00A4
  55. #define MBM29F800BA 0x2258
  56. #define MBM29LV650UE 0x22D7
  57. #define MBM29LV320TE 0x22F6
  58. #define MBM29LV320BE 0x22F9
  59. #define MBM29LV160TE 0x22C4
  60. #define MBM29LV160BE 0x2249
  61. #define MBM29LV800BA 0x225B
  62. #define MBM29LV800TA 0x22DA
  63. #define MBM29LV400TC 0x22B9
  64. #define MBM29LV400BC 0x22BA
  65. /* Hyundai */
  66. #define HY29F002T 0x00B0
  67. /* Intel */
  68. #define I28F004B3T 0x00d4
  69. #define I28F004B3B 0x00d5
  70. #define I28F400B3T 0x8894
  71. #define I28F400B3B 0x8895
  72. #define I28F008S5 0x00a6
  73. #define I28F016S5 0x00a0
  74. #define I28F008SA 0x00a2
  75. #define I28F008B3T 0x00d2
  76. #define I28F008B3B 0x00d3
  77. #define I28F800B3T 0x8892
  78. #define I28F800B3B 0x8893
  79. #define I28F016S3 0x00aa
  80. #define I28F016B3T 0x00d0
  81. #define I28F016B3B 0x00d1
  82. #define I28F160B3T 0x8890
  83. #define I28F160B3B 0x8891
  84. #define I28F320B3T 0x8896
  85. #define I28F320B3B 0x8897
  86. #define I28F640B3T 0x8898
  87. #define I28F640B3B 0x8899
  88. #define I28F640C3B 0x88CD
  89. #define I28F160F3T 0x88F3
  90. #define I28F160F3B 0x88F4
  91. #define I28F160C3T 0x88C2
  92. #define I28F160C3B 0x88C3
  93. #define I82802AB 0x00ad
  94. #define I82802AC 0x00ac
  95. /* Macronix */
  96. #define MX29LV040C 0x004F
  97. #define MX29LV160T 0x22C4
  98. #define MX29LV160B 0x2249
  99. #define MX29F040 0x00A4
  100. #define MX29F016 0x00AD
  101. #define MX29F002T 0x00B0
  102. #define MX29F004T 0x0045
  103. #define MX29F004B 0x0046
  104. /* NEC */
  105. #define UPD29F064115 0x221C
  106. /* PMC */
  107. #define PM49FL002 0x006D
  108. #define PM49FL004 0x006E
  109. #define PM49FL008 0x006A
  110. /* Sharp */
  111. #define LH28F640BF 0x00B0
  112. /* ST - www.st.com */
  113. #define M29F800AB 0x0058
  114. #define M29W800DT 0x22D7
  115. #define M29W800DB 0x225B
  116. #define M29W400DT 0x00EE
  117. #define M29W400DB 0x00EF
  118. #define M29W160DT 0x22C4
  119. #define M29W160DB 0x2249
  120. #define M29W040B 0x00E3
  121. #define M50FW040 0x002C
  122. #define M50FW080 0x002D
  123. #define M50FW016 0x002E
  124. #define M50LPW080 0x002F
  125. #define M50FLW080A 0x0080
  126. #define M50FLW080B 0x0081
  127. #define PSD4256G6V 0x00e9
  128. /* SST */
  129. #define SST29EE020 0x0010
  130. #define SST29LE020 0x0012
  131. #define SST29EE512 0x005d
  132. #define SST29LE512 0x003d
  133. #define SST39LF800 0x2781
  134. #define SST39LF160 0x2782
  135. #define SST39VF1601 0x234b
  136. #define SST39VF3201 0x235b
  137. #define SST39WF1601 0x274b
  138. #define SST39WF1602 0x274a
  139. #define SST39LF512 0x00D4
  140. #define SST39LF010 0x00D5
  141. #define SST39LF020 0x00D6
  142. #define SST39LF040 0x00D7
  143. #define SST39SF010A 0x00B5
  144. #define SST39SF020A 0x00B6
  145. #define SST39SF040 0x00B7
  146. #define SST49LF004B 0x0060
  147. #define SST49LF040B 0x0050
  148. #define SST49LF008A 0x005a
  149. #define SST49LF030A 0x001C
  150. #define SST49LF040A 0x0051
  151. #define SST49LF080A 0x005B
  152. #define SST36VF3203 0x7354
  153. /* Toshiba */
  154. #define TC58FVT160 0x00C2
  155. #define TC58FVB160 0x0043
  156. #define TC58FVT321 0x009A
  157. #define TC58FVB321 0x009C
  158. #define TC58FVT641 0x0093
  159. #define TC58FVB641 0x0095
  160. /* Winbond */
  161. #define W49V002A 0x00b0
  162. /*
  163. * Unlock address sets for AMD command sets.
  164. * Intel command sets use the MTD_UADDR_UNNECESSARY.
  165. * Each identifier, except MTD_UADDR_UNNECESSARY, and
  166. * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
  167. * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
  168. * initialization need not require initializing all of the
  169. * unlock addresses for all bit widths.
  170. */
  171. enum uaddr {
  172. MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
  173. MTD_UADDR_0x0555_0x02AA,
  174. MTD_UADDR_0x0555_0x0AAA,
  175. MTD_UADDR_0x5555_0x2AAA,
  176. MTD_UADDR_0x0AAA_0x0554,
  177. MTD_UADDR_0x0AAA_0x0555,
  178. MTD_UADDR_0xAAAA_0x5555,
  179. MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
  180. MTD_UADDR_UNNECESSARY, /* Does not require any address */
  181. };
  182. struct unlock_addr {
  183. uint32_t addr1;
  184. uint32_t addr2;
  185. };
  186. /*
  187. * I don't like the fact that the first entry in unlock_addrs[]
  188. * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
  189. * should not be used. The problem is that structures with
  190. * initializers have extra fields initialized to 0. It is _very_
  191. * desirable to have the unlock address entries for unsupported
  192. * data widths automatically initialized - that means that
  193. * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
  194. * must go unused.
  195. */
  196. static const struct unlock_addr unlock_addrs[] = {
  197. [MTD_UADDR_NOT_SUPPORTED] = {
  198. .addr1 = 0xffff,
  199. .addr2 = 0xffff
  200. },
  201. [MTD_UADDR_0x0555_0x02AA] = {
  202. .addr1 = 0x0555,
  203. .addr2 = 0x02aa
  204. },
  205. [MTD_UADDR_0x0555_0x0AAA] = {
  206. .addr1 = 0x0555,
  207. .addr2 = 0x0aaa
  208. },
  209. [MTD_UADDR_0x5555_0x2AAA] = {
  210. .addr1 = 0x5555,
  211. .addr2 = 0x2aaa
  212. },
  213. [MTD_UADDR_0x0AAA_0x0554] = {
  214. .addr1 = 0x0AAA,
  215. .addr2 = 0x0554
  216. },
  217. [MTD_UADDR_0x0AAA_0x0555] = {
  218. .addr1 = 0x0AAA,
  219. .addr2 = 0x0555
  220. },
  221. [MTD_UADDR_0xAAAA_0x5555] = {
  222. .addr1 = 0xaaaa,
  223. .addr2 = 0x5555
  224. },
  225. [MTD_UADDR_DONT_CARE] = {
  226. .addr1 = 0x0000, /* Doesn't matter which address */
  227. .addr2 = 0x0000 /* is used - must be last entry */
  228. },
  229. [MTD_UADDR_UNNECESSARY] = {
  230. .addr1 = 0x0000,
  231. .addr2 = 0x0000
  232. }
  233. };
  234. struct amd_flash_info {
  235. const char *name;
  236. const uint16_t mfr_id;
  237. const uint16_t dev_id;
  238. const uint8_t dev_size;
  239. const uint8_t nr_regions;
  240. const uint16_t cmd_set;
  241. const uint32_t regions[6];
  242. const uint8_t devtypes; /* Bitmask for x8, x16 etc. */
  243. const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */
  244. };
  245. #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
  246. #define SIZE_64KiB 16
  247. #define SIZE_128KiB 17
  248. #define SIZE_256KiB 18
  249. #define SIZE_512KiB 19
  250. #define SIZE_1MiB 20
  251. #define SIZE_2MiB 21
  252. #define SIZE_4MiB 22
  253. #define SIZE_8MiB 23
  254. /*
  255. * Please keep this list ordered by manufacturer!
  256. * Fortunately, the list isn't searched often and so a
  257. * slow, linear search isn't so bad.
  258. */
  259. static const struct amd_flash_info jedec_table[] = {
  260. {
  261. .mfr_id = CFI_MFR_AMD,
  262. .dev_id = AM29F032B,
  263. .name = "AMD AM29F032B",
  264. .uaddr = MTD_UADDR_0x0555_0x02AA,
  265. .devtypes = CFI_DEVICETYPE_X8,
  266. .dev_size = SIZE_4MiB,
  267. .cmd_set = P_ID_AMD_STD,
  268. .nr_regions = 1,
  269. .regions = {
  270. ERASEINFO(0x10000,64)
  271. }
  272. }, {
  273. .mfr_id = CFI_MFR_AMD,
  274. .dev_id = AM29LV160DT,
  275. .name = "AMD AM29LV160DT",
  276. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  277. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  278. .dev_size = SIZE_2MiB,
  279. .cmd_set = P_ID_AMD_STD,
  280. .nr_regions = 4,
  281. .regions = {
  282. ERASEINFO(0x10000,31),
  283. ERASEINFO(0x08000,1),
  284. ERASEINFO(0x02000,2),
  285. ERASEINFO(0x04000,1)
  286. }
  287. }, {
  288. .mfr_id = CFI_MFR_AMD,
  289. .dev_id = AM29LV160DB,
  290. .name = "AMD AM29LV160DB",
  291. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  292. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  293. .dev_size = SIZE_2MiB,
  294. .cmd_set = P_ID_AMD_STD,
  295. .nr_regions = 4,
  296. .regions = {
  297. ERASEINFO(0x04000,1),
  298. ERASEINFO(0x02000,2),
  299. ERASEINFO(0x08000,1),
  300. ERASEINFO(0x10000,31)
  301. }
  302. }, {
  303. .mfr_id = CFI_MFR_AMD,
  304. .dev_id = AM29LV400BB,
  305. .name = "AMD AM29LV400BB",
  306. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  307. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  308. .dev_size = SIZE_512KiB,
  309. .cmd_set = P_ID_AMD_STD,
  310. .nr_regions = 4,
  311. .regions = {
  312. ERASEINFO(0x04000,1),
  313. ERASEINFO(0x02000,2),
  314. ERASEINFO(0x08000,1),
  315. ERASEINFO(0x10000,7)
  316. }
  317. }, {
  318. .mfr_id = CFI_MFR_AMD,
  319. .dev_id = AM29LV400BT,
  320. .name = "AMD AM29LV400BT",
  321. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  322. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  323. .dev_size = SIZE_512KiB,
  324. .cmd_set = P_ID_AMD_STD,
  325. .nr_regions = 4,
  326. .regions = {
  327. ERASEINFO(0x10000,7),
  328. ERASEINFO(0x08000,1),
  329. ERASEINFO(0x02000,2),
  330. ERASEINFO(0x04000,1)
  331. }
  332. }, {
  333. .mfr_id = CFI_MFR_AMD,
  334. .dev_id = AM29LV800BB,
  335. .name = "AMD AM29LV800BB",
  336. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  337. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  338. .dev_size = SIZE_1MiB,
  339. .cmd_set = P_ID_AMD_STD,
  340. .nr_regions = 4,
  341. .regions = {
  342. ERASEINFO(0x04000,1),
  343. ERASEINFO(0x02000,2),
  344. ERASEINFO(0x08000,1),
  345. ERASEINFO(0x10000,15),
  346. }
  347. }, {
  348. /* add DL */
  349. .mfr_id = CFI_MFR_AMD,
  350. .dev_id = AM29DL800BB,
  351. .name = "AMD AM29DL800BB",
  352. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  353. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  354. .dev_size = SIZE_1MiB,
  355. .cmd_set = P_ID_AMD_STD,
  356. .nr_regions = 6,
  357. .regions = {
  358. ERASEINFO(0x04000,1),
  359. ERASEINFO(0x08000,1),
  360. ERASEINFO(0x02000,4),
  361. ERASEINFO(0x08000,1),
  362. ERASEINFO(0x04000,1),
  363. ERASEINFO(0x10000,14)
  364. }
  365. }, {
  366. .mfr_id = CFI_MFR_AMD,
  367. .dev_id = AM29DL800BT,
  368. .name = "AMD AM29DL800BT",
  369. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  370. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  371. .dev_size = SIZE_1MiB,
  372. .cmd_set = P_ID_AMD_STD,
  373. .nr_regions = 6,
  374. .regions = {
  375. ERASEINFO(0x10000,14),
  376. ERASEINFO(0x04000,1),
  377. ERASEINFO(0x08000,1),
  378. ERASEINFO(0x02000,4),
  379. ERASEINFO(0x08000,1),
  380. ERASEINFO(0x04000,1)
  381. }
  382. }, {
  383. .mfr_id = CFI_MFR_AMD,
  384. .dev_id = AM29F800BB,
  385. .name = "AMD AM29F800BB",
  386. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  387. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  388. .dev_size = SIZE_1MiB,
  389. .cmd_set = P_ID_AMD_STD,
  390. .nr_regions = 4,
  391. .regions = {
  392. ERASEINFO(0x04000,1),
  393. ERASEINFO(0x02000,2),
  394. ERASEINFO(0x08000,1),
  395. ERASEINFO(0x10000,15),
  396. }
  397. }, {
  398. .mfr_id = CFI_MFR_AMD,
  399. .dev_id = AM29LV800BT,
  400. .name = "AMD AM29LV800BT",
  401. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  402. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  403. .dev_size = SIZE_1MiB,
  404. .cmd_set = P_ID_AMD_STD,
  405. .nr_regions = 4,
  406. .regions = {
  407. ERASEINFO(0x10000,15),
  408. ERASEINFO(0x08000,1),
  409. ERASEINFO(0x02000,2),
  410. ERASEINFO(0x04000,1)
  411. }
  412. }, {
  413. .mfr_id = CFI_MFR_AMD,
  414. .dev_id = AM29F800BT,
  415. .name = "AMD AM29F800BT",
  416. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  417. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  418. .dev_size = SIZE_1MiB,
  419. .cmd_set = P_ID_AMD_STD,
  420. .nr_regions = 4,
  421. .regions = {
  422. ERASEINFO(0x10000,15),
  423. ERASEINFO(0x08000,1),
  424. ERASEINFO(0x02000,2),
  425. ERASEINFO(0x04000,1)
  426. }
  427. }, {
  428. .mfr_id = CFI_MFR_AMD,
  429. .dev_id = AM29F017D,
  430. .name = "AMD AM29F017D",
  431. .devtypes = CFI_DEVICETYPE_X8,
  432. .uaddr = MTD_UADDR_DONT_CARE,
  433. .dev_size = SIZE_2MiB,
  434. .cmd_set = P_ID_AMD_STD,
  435. .nr_regions = 1,
  436. .regions = {
  437. ERASEINFO(0x10000,32),
  438. }
  439. }, {
  440. .mfr_id = CFI_MFR_AMD,
  441. .dev_id = AM29F016D,
  442. .name = "AMD AM29F016D",
  443. .devtypes = CFI_DEVICETYPE_X8,
  444. .uaddr = MTD_UADDR_0x0555_0x02AA,
  445. .dev_size = SIZE_2MiB,
  446. .cmd_set = P_ID_AMD_STD,
  447. .nr_regions = 1,
  448. .regions = {
  449. ERASEINFO(0x10000,32),
  450. }
  451. }, {
  452. .mfr_id = CFI_MFR_AMD,
  453. .dev_id = AM29F080,
  454. .name = "AMD AM29F080",
  455. .devtypes = CFI_DEVICETYPE_X8,
  456. .uaddr = MTD_UADDR_0x0555_0x02AA,
  457. .dev_size = SIZE_1MiB,
  458. .cmd_set = P_ID_AMD_STD,
  459. .nr_regions = 1,
  460. .regions = {
  461. ERASEINFO(0x10000,16),
  462. }
  463. }, {
  464. .mfr_id = CFI_MFR_AMD,
  465. .dev_id = AM29F040,
  466. .name = "AMD AM29F040",
  467. .devtypes = CFI_DEVICETYPE_X8,
  468. .uaddr = MTD_UADDR_0x0555_0x02AA,
  469. .dev_size = SIZE_512KiB,
  470. .cmd_set = P_ID_AMD_STD,
  471. .nr_regions = 1,
  472. .regions = {
  473. ERASEINFO(0x10000,8),
  474. }
  475. }, {
  476. .mfr_id = CFI_MFR_AMD,
  477. .dev_id = AM29LV040B,
  478. .name = "AMD AM29LV040B",
  479. .devtypes = CFI_DEVICETYPE_X8,
  480. .uaddr = MTD_UADDR_0x0555_0x02AA,
  481. .dev_size = SIZE_512KiB,
  482. .cmd_set = P_ID_AMD_STD,
  483. .nr_regions = 1,
  484. .regions = {
  485. ERASEINFO(0x10000,8),
  486. }
  487. }, {
  488. .mfr_id = CFI_MFR_AMD,
  489. .dev_id = AM29F002T,
  490. .name = "AMD AM29F002T",
  491. .devtypes = CFI_DEVICETYPE_X8,
  492. .uaddr = MTD_UADDR_0x0555_0x02AA,
  493. .dev_size = SIZE_256KiB,
  494. .cmd_set = P_ID_AMD_STD,
  495. .nr_regions = 4,
  496. .regions = {
  497. ERASEINFO(0x10000,3),
  498. ERASEINFO(0x08000,1),
  499. ERASEINFO(0x02000,2),
  500. ERASEINFO(0x04000,1),
  501. }
  502. }, {
  503. .mfr_id = CFI_MFR_AMD,
  504. .dev_id = AM29SL800DT,
  505. .name = "AMD AM29SL800DT",
  506. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  507. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  508. .dev_size = SIZE_1MiB,
  509. .cmd_set = P_ID_AMD_STD,
  510. .nr_regions = 4,
  511. .regions = {
  512. ERASEINFO(0x10000,15),
  513. ERASEINFO(0x08000,1),
  514. ERASEINFO(0x02000,2),
  515. ERASEINFO(0x04000,1),
  516. }
  517. }, {
  518. .mfr_id = CFI_MFR_AMD,
  519. .dev_id = AM29SL800DB,
  520. .name = "AMD AM29SL800DB",
  521. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  522. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  523. .dev_size = SIZE_1MiB,
  524. .cmd_set = P_ID_AMD_STD,
  525. .nr_regions = 4,
  526. .regions = {
  527. ERASEINFO(0x04000,1),
  528. ERASEINFO(0x02000,2),
  529. ERASEINFO(0x08000,1),
  530. ERASEINFO(0x10000,15),
  531. }
  532. }, {
  533. .mfr_id = CFI_MFR_ATMEL,
  534. .dev_id = AT49BV512,
  535. .name = "Atmel AT49BV512",
  536. .devtypes = CFI_DEVICETYPE_X8,
  537. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  538. .dev_size = SIZE_64KiB,
  539. .cmd_set = P_ID_AMD_STD,
  540. .nr_regions = 1,
  541. .regions = {
  542. ERASEINFO(0x10000,1)
  543. }
  544. }, {
  545. .mfr_id = CFI_MFR_ATMEL,
  546. .dev_id = AT29LV512,
  547. .name = "Atmel AT29LV512",
  548. .devtypes = CFI_DEVICETYPE_X8,
  549. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  550. .dev_size = SIZE_64KiB,
  551. .cmd_set = P_ID_AMD_STD,
  552. .nr_regions = 1,
  553. .regions = {
  554. ERASEINFO(0x80,256),
  555. ERASEINFO(0x80,256)
  556. }
  557. }, {
  558. .mfr_id = CFI_MFR_ATMEL,
  559. .dev_id = AT49BV16X,
  560. .name = "Atmel AT49BV16X",
  561. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  562. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  563. .dev_size = SIZE_2MiB,
  564. .cmd_set = P_ID_AMD_STD,
  565. .nr_regions = 2,
  566. .regions = {
  567. ERASEINFO(0x02000,8),
  568. ERASEINFO(0x10000,31)
  569. }
  570. }, {
  571. .mfr_id = CFI_MFR_ATMEL,
  572. .dev_id = AT49BV16XT,
  573. .name = "Atmel AT49BV16XT",
  574. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  575. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  576. .dev_size = SIZE_2MiB,
  577. .cmd_set = P_ID_AMD_STD,
  578. .nr_regions = 2,
  579. .regions = {
  580. ERASEINFO(0x10000,31),
  581. ERASEINFO(0x02000,8)
  582. }
  583. }, {
  584. .mfr_id = CFI_MFR_ATMEL,
  585. .dev_id = AT49BV32X,
  586. .name = "Atmel AT49BV32X",
  587. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  588. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  589. .dev_size = SIZE_4MiB,
  590. .cmd_set = P_ID_AMD_STD,
  591. .nr_regions = 2,
  592. .regions = {
  593. ERASEINFO(0x02000,8),
  594. ERASEINFO(0x10000,63)
  595. }
  596. }, {
  597. .mfr_id = CFI_MFR_ATMEL,
  598. .dev_id = AT49BV32XT,
  599. .name = "Atmel AT49BV32XT",
  600. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  601. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  602. .dev_size = SIZE_4MiB,
  603. .cmd_set = P_ID_AMD_STD,
  604. .nr_regions = 2,
  605. .regions = {
  606. ERASEINFO(0x10000,63),
  607. ERASEINFO(0x02000,8)
  608. }
  609. }, {
  610. .mfr_id = CFI_MFR_EON,
  611. .dev_id = EN29LV400AT,
  612. .name = "Eon EN29LV400AT",
  613. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  614. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  615. .dev_size = SIZE_512KiB,
  616. .cmd_set = P_ID_AMD_STD,
  617. .nr_regions = 4,
  618. .regions = {
  619. ERASEINFO(0x10000,7),
  620. ERASEINFO(0x08000,1),
  621. ERASEINFO(0x02000,2),
  622. ERASEINFO(0x04000,1),
  623. }
  624. }, {
  625. .mfr_id = CFI_MFR_EON,
  626. .dev_id = EN29LV400AB,
  627. .name = "Eon EN29LV400AB",
  628. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  629. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  630. .dev_size = SIZE_512KiB,
  631. .cmd_set = P_ID_AMD_STD,
  632. .nr_regions = 4,
  633. .regions = {
  634. ERASEINFO(0x04000,1),
  635. ERASEINFO(0x02000,2),
  636. ERASEINFO(0x08000,1),
  637. ERASEINFO(0x10000,7),
  638. }
  639. }, {
  640. .mfr_id = CFI_MFR_EON,
  641. .dev_id = EN29SL800BT,
  642. .name = "Eon EN29SL800BT",
  643. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  644. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  645. .dev_size = SIZE_1MiB,
  646. .cmd_set = P_ID_AMD_STD,
  647. .nr_regions = 4,
  648. .regions = {
  649. ERASEINFO(0x10000,15),
  650. ERASEINFO(0x08000,1),
  651. ERASEINFO(0x02000,2),
  652. ERASEINFO(0x04000,1),
  653. }
  654. }, {
  655. .mfr_id = CFI_MFR_EON,
  656. .dev_id = EN29SL800BB,
  657. .name = "Eon EN29SL800BB",
  658. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  659. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  660. .dev_size = SIZE_1MiB,
  661. .cmd_set = P_ID_AMD_STD,
  662. .nr_regions = 4,
  663. .regions = {
  664. ERASEINFO(0x04000,1),
  665. ERASEINFO(0x02000,2),
  666. ERASEINFO(0x08000,1),
  667. ERASEINFO(0x10000,15),
  668. }
  669. }, {
  670. .mfr_id = CFI_MFR_FUJITSU,
  671. .dev_id = MBM29F040C,
  672. .name = "Fujitsu MBM29F040C",
  673. .devtypes = CFI_DEVICETYPE_X8,
  674. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  675. .dev_size = SIZE_512KiB,
  676. .cmd_set = P_ID_AMD_STD,
  677. .nr_regions = 1,
  678. .regions = {
  679. ERASEINFO(0x10000,8)
  680. }
  681. }, {
  682. .mfr_id = CFI_MFR_FUJITSU,
  683. .dev_id = MBM29F800BA,
  684. .name = "Fujitsu MBM29F800BA",
  685. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  686. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  687. .dev_size = SIZE_1MiB,
  688. .cmd_set = P_ID_AMD_STD,
  689. .nr_regions = 4,
  690. .regions = {
  691. ERASEINFO(0x04000,1),
  692. ERASEINFO(0x02000,2),
  693. ERASEINFO(0x08000,1),
  694. ERASEINFO(0x10000,15),
  695. }
  696. }, {
  697. .mfr_id = CFI_MFR_FUJITSU,
  698. .dev_id = MBM29LV650UE,
  699. .name = "Fujitsu MBM29LV650UE",
  700. .devtypes = CFI_DEVICETYPE_X8,
  701. .uaddr = MTD_UADDR_DONT_CARE,
  702. .dev_size = SIZE_8MiB,
  703. .cmd_set = P_ID_AMD_STD,
  704. .nr_regions = 1,
  705. .regions = {
  706. ERASEINFO(0x10000,128)
  707. }
  708. }, {
  709. .mfr_id = CFI_MFR_FUJITSU,
  710. .dev_id = MBM29LV320TE,
  711. .name = "Fujitsu MBM29LV320TE",
  712. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  713. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  714. .dev_size = SIZE_4MiB,
  715. .cmd_set = P_ID_AMD_STD,
  716. .nr_regions = 2,
  717. .regions = {
  718. ERASEINFO(0x10000,63),
  719. ERASEINFO(0x02000,8)
  720. }
  721. }, {
  722. .mfr_id = CFI_MFR_FUJITSU,
  723. .dev_id = MBM29LV320BE,
  724. .name = "Fujitsu MBM29LV320BE",
  725. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  726. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  727. .dev_size = SIZE_4MiB,
  728. .cmd_set = P_ID_AMD_STD,
  729. .nr_regions = 2,
  730. .regions = {
  731. ERASEINFO(0x02000,8),
  732. ERASEINFO(0x10000,63)
  733. }
  734. }, {
  735. .mfr_id = CFI_MFR_FUJITSU,
  736. .dev_id = MBM29LV160TE,
  737. .name = "Fujitsu MBM29LV160TE",
  738. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  739. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  740. .dev_size = SIZE_2MiB,
  741. .cmd_set = P_ID_AMD_STD,
  742. .nr_regions = 4,
  743. .regions = {
  744. ERASEINFO(0x10000,31),
  745. ERASEINFO(0x08000,1),
  746. ERASEINFO(0x02000,2),
  747. ERASEINFO(0x04000,1)
  748. }
  749. }, {
  750. .mfr_id = CFI_MFR_FUJITSU,
  751. .dev_id = MBM29LV160BE,
  752. .name = "Fujitsu MBM29LV160BE",
  753. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  754. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  755. .dev_size = SIZE_2MiB,
  756. .cmd_set = P_ID_AMD_STD,
  757. .nr_regions = 4,
  758. .regions = {
  759. ERASEINFO(0x04000,1),
  760. ERASEINFO(0x02000,2),
  761. ERASEINFO(0x08000,1),
  762. ERASEINFO(0x10000,31)
  763. }
  764. }, {
  765. .mfr_id = CFI_MFR_FUJITSU,
  766. .dev_id = MBM29LV800BA,
  767. .name = "Fujitsu MBM29LV800BA",
  768. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  769. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  770. .dev_size = SIZE_1MiB,
  771. .cmd_set = P_ID_AMD_STD,
  772. .nr_regions = 4,
  773. .regions = {
  774. ERASEINFO(0x04000,1),
  775. ERASEINFO(0x02000,2),
  776. ERASEINFO(0x08000,1),
  777. ERASEINFO(0x10000,15)
  778. }
  779. }, {
  780. .mfr_id = CFI_MFR_FUJITSU,
  781. .dev_id = MBM29LV800TA,
  782. .name = "Fujitsu MBM29LV800TA",
  783. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  784. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  785. .dev_size = SIZE_1MiB,
  786. .cmd_set = P_ID_AMD_STD,
  787. .nr_regions = 4,
  788. .regions = {
  789. ERASEINFO(0x10000,15),
  790. ERASEINFO(0x08000,1),
  791. ERASEINFO(0x02000,2),
  792. ERASEINFO(0x04000,1)
  793. }
  794. }, {
  795. .mfr_id = CFI_MFR_FUJITSU,
  796. .dev_id = MBM29LV400BC,
  797. .name = "Fujitsu MBM29LV400BC",
  798. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  799. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  800. .dev_size = SIZE_512KiB,
  801. .cmd_set = P_ID_AMD_STD,
  802. .nr_regions = 4,
  803. .regions = {
  804. ERASEINFO(0x04000,1),
  805. ERASEINFO(0x02000,2),
  806. ERASEINFO(0x08000,1),
  807. ERASEINFO(0x10000,7)
  808. }
  809. }, {
  810. .mfr_id = CFI_MFR_FUJITSU,
  811. .dev_id = MBM29LV400TC,
  812. .name = "Fujitsu MBM29LV400TC",
  813. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  814. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  815. .dev_size = SIZE_512KiB,
  816. .cmd_set = P_ID_AMD_STD,
  817. .nr_regions = 4,
  818. .regions = {
  819. ERASEINFO(0x10000,7),
  820. ERASEINFO(0x08000,1),
  821. ERASEINFO(0x02000,2),
  822. ERASEINFO(0x04000,1)
  823. }
  824. }, {
  825. .mfr_id = CFI_MFR_HYUNDAI,
  826. .dev_id = HY29F002T,
  827. .name = "Hyundai HY29F002T",
  828. .devtypes = CFI_DEVICETYPE_X8,
  829. .uaddr = MTD_UADDR_0x0555_0x02AA,
  830. .dev_size = SIZE_256KiB,
  831. .cmd_set = P_ID_AMD_STD,
  832. .nr_regions = 4,
  833. .regions = {
  834. ERASEINFO(0x10000,3),
  835. ERASEINFO(0x08000,1),
  836. ERASEINFO(0x02000,2),
  837. ERASEINFO(0x04000,1),
  838. }
  839. }, {
  840. .mfr_id = CFI_MFR_INTEL,
  841. .dev_id = I28F004B3B,
  842. .name = "Intel 28F004B3B",
  843. .devtypes = CFI_DEVICETYPE_X8,
  844. .uaddr = MTD_UADDR_UNNECESSARY,
  845. .dev_size = SIZE_512KiB,
  846. .cmd_set = P_ID_INTEL_STD,
  847. .nr_regions = 2,
  848. .regions = {
  849. ERASEINFO(0x02000, 8),
  850. ERASEINFO(0x10000, 7),
  851. }
  852. }, {
  853. .mfr_id = CFI_MFR_INTEL,
  854. .dev_id = I28F004B3T,
  855. .name = "Intel 28F004B3T",
  856. .devtypes = CFI_DEVICETYPE_X8,
  857. .uaddr = MTD_UADDR_UNNECESSARY,
  858. .dev_size = SIZE_512KiB,
  859. .cmd_set = P_ID_INTEL_STD,
  860. .nr_regions = 2,
  861. .regions = {
  862. ERASEINFO(0x10000, 7),
  863. ERASEINFO(0x02000, 8),
  864. }
  865. }, {
  866. .mfr_id = CFI_MFR_INTEL,
  867. .dev_id = I28F400B3B,
  868. .name = "Intel 28F400B3B",
  869. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  870. .uaddr = MTD_UADDR_UNNECESSARY,
  871. .dev_size = SIZE_512KiB,
  872. .cmd_set = P_ID_INTEL_STD,
  873. .nr_regions = 2,
  874. .regions = {
  875. ERASEINFO(0x02000, 8),
  876. ERASEINFO(0x10000, 7),
  877. }
  878. }, {
  879. .mfr_id = CFI_MFR_INTEL,
  880. .dev_id = I28F400B3T,
  881. .name = "Intel 28F400B3T",
  882. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  883. .uaddr = MTD_UADDR_UNNECESSARY,
  884. .dev_size = SIZE_512KiB,
  885. .cmd_set = P_ID_INTEL_STD,
  886. .nr_regions = 2,
  887. .regions = {
  888. ERASEINFO(0x10000, 7),
  889. ERASEINFO(0x02000, 8),
  890. }
  891. }, {
  892. .mfr_id = CFI_MFR_INTEL,
  893. .dev_id = I28F008B3B,
  894. .name = "Intel 28F008B3B",
  895. .devtypes = CFI_DEVICETYPE_X8,
  896. .uaddr = MTD_UADDR_UNNECESSARY,
  897. .dev_size = SIZE_1MiB,
  898. .cmd_set = P_ID_INTEL_STD,
  899. .nr_regions = 2,
  900. .regions = {
  901. ERASEINFO(0x02000, 8),
  902. ERASEINFO(0x10000, 15),
  903. }
  904. }, {
  905. .mfr_id = CFI_MFR_INTEL,
  906. .dev_id = I28F008B3T,
  907. .name = "Intel 28F008B3T",
  908. .devtypes = CFI_DEVICETYPE_X8,
  909. .uaddr = MTD_UADDR_UNNECESSARY,
  910. .dev_size = SIZE_1MiB,
  911. .cmd_set = P_ID_INTEL_STD,
  912. .nr_regions = 2,
  913. .regions = {
  914. ERASEINFO(0x10000, 15),
  915. ERASEINFO(0x02000, 8),
  916. }
  917. }, {
  918. .mfr_id = CFI_MFR_INTEL,
  919. .dev_id = I28F008S5,
  920. .name = "Intel 28F008S5",
  921. .devtypes = CFI_DEVICETYPE_X8,
  922. .uaddr = MTD_UADDR_UNNECESSARY,
  923. .dev_size = SIZE_1MiB,
  924. .cmd_set = P_ID_INTEL_EXT,
  925. .nr_regions = 1,
  926. .regions = {
  927. ERASEINFO(0x10000,16),
  928. }
  929. }, {
  930. .mfr_id = CFI_MFR_INTEL,
  931. .dev_id = I28F016S5,
  932. .name = "Intel 28F016S5",
  933. .devtypes = CFI_DEVICETYPE_X8,
  934. .uaddr = MTD_UADDR_UNNECESSARY,
  935. .dev_size = SIZE_2MiB,
  936. .cmd_set = P_ID_INTEL_EXT,
  937. .nr_regions = 1,
  938. .regions = {
  939. ERASEINFO(0x10000,32),
  940. }
  941. }, {
  942. .mfr_id = CFI_MFR_INTEL,
  943. .dev_id = I28F008SA,
  944. .name = "Intel 28F008SA",
  945. .devtypes = CFI_DEVICETYPE_X8,
  946. .uaddr = MTD_UADDR_UNNECESSARY,
  947. .dev_size = SIZE_1MiB,
  948. .cmd_set = P_ID_INTEL_STD,
  949. .nr_regions = 1,
  950. .regions = {
  951. ERASEINFO(0x10000, 16),
  952. }
  953. }, {
  954. .mfr_id = CFI_MFR_INTEL,
  955. .dev_id = I28F800B3B,
  956. .name = "Intel 28F800B3B",
  957. .devtypes = CFI_DEVICETYPE_X16,
  958. .uaddr = MTD_UADDR_UNNECESSARY,
  959. .dev_size = SIZE_1MiB,
  960. .cmd_set = P_ID_INTEL_STD,
  961. .nr_regions = 2,
  962. .regions = {
  963. ERASEINFO(0x02000, 8),
  964. ERASEINFO(0x10000, 15),
  965. }
  966. }, {
  967. .mfr_id = CFI_MFR_INTEL,
  968. .dev_id = I28F800B3T,
  969. .name = "Intel 28F800B3T",
  970. .devtypes = CFI_DEVICETYPE_X16,
  971. .uaddr = MTD_UADDR_UNNECESSARY,
  972. .dev_size = SIZE_1MiB,
  973. .cmd_set = P_ID_INTEL_STD,
  974. .nr_regions = 2,
  975. .regions = {
  976. ERASEINFO(0x10000, 15),
  977. ERASEINFO(0x02000, 8),
  978. }
  979. }, {
  980. .mfr_id = CFI_MFR_INTEL,
  981. .dev_id = I28F016B3B,
  982. .name = "Intel 28F016B3B",
  983. .devtypes = CFI_DEVICETYPE_X8,
  984. .uaddr = MTD_UADDR_UNNECESSARY,
  985. .dev_size = SIZE_2MiB,
  986. .cmd_set = P_ID_INTEL_STD,
  987. .nr_regions = 2,
  988. .regions = {
  989. ERASEINFO(0x02000, 8),
  990. ERASEINFO(0x10000, 31),
  991. }
  992. }, {
  993. .mfr_id = CFI_MFR_INTEL,
  994. .dev_id = I28F016S3,
  995. .name = "Intel I28F016S3",
  996. .devtypes = CFI_DEVICETYPE_X8,
  997. .uaddr = MTD_UADDR_UNNECESSARY,
  998. .dev_size = SIZE_2MiB,
  999. .cmd_set = P_ID_INTEL_STD,
  1000. .nr_regions = 1,
  1001. .regions = {
  1002. ERASEINFO(0x10000, 32),
  1003. }
  1004. }, {
  1005. .mfr_id = CFI_MFR_INTEL,
  1006. .dev_id = I28F016B3T,
  1007. .name = "Intel 28F016B3T",
  1008. .devtypes = CFI_DEVICETYPE_X8,
  1009. .uaddr = MTD_UADDR_UNNECESSARY,
  1010. .dev_size = SIZE_2MiB,
  1011. .cmd_set = P_ID_INTEL_STD,
  1012. .nr_regions = 2,
  1013. .regions = {
  1014. ERASEINFO(0x10000, 31),
  1015. ERASEINFO(0x02000, 8),
  1016. }
  1017. }, {
  1018. .mfr_id = CFI_MFR_INTEL,
  1019. .dev_id = I28F160B3B,
  1020. .name = "Intel 28F160B3B",
  1021. .devtypes = CFI_DEVICETYPE_X16,
  1022. .uaddr = MTD_UADDR_UNNECESSARY,
  1023. .dev_size = SIZE_2MiB,
  1024. .cmd_set = P_ID_INTEL_STD,
  1025. .nr_regions = 2,
  1026. .regions = {
  1027. ERASEINFO(0x02000, 8),
  1028. ERASEINFO(0x10000, 31),
  1029. }
  1030. }, {
  1031. .mfr_id = CFI_MFR_INTEL,
  1032. .dev_id = I28F160B3T,
  1033. .name = "Intel 28F160B3T",
  1034. .devtypes = CFI_DEVICETYPE_X16,
  1035. .uaddr = MTD_UADDR_UNNECESSARY,
  1036. .dev_size = SIZE_2MiB,
  1037. .cmd_set = P_ID_INTEL_STD,
  1038. .nr_regions = 2,
  1039. .regions = {
  1040. ERASEINFO(0x10000, 31),
  1041. ERASEINFO(0x02000, 8),
  1042. }
  1043. }, {
  1044. .mfr_id = CFI_MFR_INTEL,
  1045. .dev_id = I28F320B3B,
  1046. .name = "Intel 28F320B3B",
  1047. .devtypes = CFI_DEVICETYPE_X16,
  1048. .uaddr = MTD_UADDR_UNNECESSARY,
  1049. .dev_size = SIZE_4MiB,
  1050. .cmd_set = P_ID_INTEL_STD,
  1051. .nr_regions = 2,
  1052. .regions = {
  1053. ERASEINFO(0x02000, 8),
  1054. ERASEINFO(0x10000, 63),
  1055. }
  1056. }, {
  1057. .mfr_id = CFI_MFR_INTEL,
  1058. .dev_id = I28F320B3T,
  1059. .name = "Intel 28F320B3T",
  1060. .devtypes = CFI_DEVICETYPE_X16,
  1061. .uaddr = MTD_UADDR_UNNECESSARY,
  1062. .dev_size = SIZE_4MiB,
  1063. .cmd_set = P_ID_INTEL_STD,
  1064. .nr_regions = 2,
  1065. .regions = {
  1066. ERASEINFO(0x10000, 63),
  1067. ERASEINFO(0x02000, 8),
  1068. }
  1069. }, {
  1070. .mfr_id = CFI_MFR_INTEL,
  1071. .dev_id = I28F640B3B,
  1072. .name = "Intel 28F640B3B",
  1073. .devtypes = CFI_DEVICETYPE_X16,
  1074. .uaddr = MTD_UADDR_UNNECESSARY,
  1075. .dev_size = SIZE_8MiB,
  1076. .cmd_set = P_ID_INTEL_STD,
  1077. .nr_regions = 2,
  1078. .regions = {
  1079. ERASEINFO(0x02000, 8),
  1080. ERASEINFO(0x10000, 127),
  1081. }
  1082. }, {
  1083. .mfr_id = CFI_MFR_INTEL,
  1084. .dev_id = I28F640B3T,
  1085. .name = "Intel 28F640B3T",
  1086. .devtypes = CFI_DEVICETYPE_X16,
  1087. .uaddr = MTD_UADDR_UNNECESSARY,
  1088. .dev_size = SIZE_8MiB,
  1089. .cmd_set = P_ID_INTEL_STD,
  1090. .nr_regions = 2,
  1091. .regions = {
  1092. ERASEINFO(0x10000, 127),
  1093. ERASEINFO(0x02000, 8),
  1094. }
  1095. }, {
  1096. .mfr_id = CFI_MFR_INTEL,
  1097. .dev_id = I28F640C3B,
  1098. .name = "Intel 28F640C3B",
  1099. .devtypes = CFI_DEVICETYPE_X16,
  1100. .uaddr = MTD_UADDR_UNNECESSARY,
  1101. .dev_size = SIZE_8MiB,
  1102. .cmd_set = P_ID_INTEL_STD,
  1103. .nr_regions = 2,
  1104. .regions = {
  1105. ERASEINFO(0x02000, 8),
  1106. ERASEINFO(0x10000, 127),
  1107. }
  1108. }, {
  1109. .mfr_id = CFI_MFR_INTEL,
  1110. .dev_id = I82802AB,
  1111. .name = "Intel 82802AB",
  1112. .devtypes = CFI_DEVICETYPE_X8,
  1113. .uaddr = MTD_UADDR_UNNECESSARY,
  1114. .dev_size = SIZE_512KiB,
  1115. .cmd_set = P_ID_INTEL_EXT,
  1116. .nr_regions = 1,
  1117. .regions = {
  1118. ERASEINFO(0x10000,8),
  1119. }
  1120. }, {
  1121. .mfr_id = CFI_MFR_INTEL,
  1122. .dev_id = I82802AC,
  1123. .name = "Intel 82802AC",
  1124. .devtypes = CFI_DEVICETYPE_X8,
  1125. .uaddr = MTD_UADDR_UNNECESSARY,
  1126. .dev_size = SIZE_1MiB,
  1127. .cmd_set = P_ID_INTEL_EXT,
  1128. .nr_regions = 1,
  1129. .regions = {
  1130. ERASEINFO(0x10000,16),
  1131. }
  1132. }, {
  1133. .mfr_id = CFI_MFR_MACRONIX,
  1134. .dev_id = MX29LV040C,
  1135. .name = "Macronix MX29LV040C",
  1136. .devtypes = CFI_DEVICETYPE_X8,
  1137. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1138. .dev_size = SIZE_512KiB,
  1139. .cmd_set = P_ID_AMD_STD,
  1140. .nr_regions = 1,
  1141. .regions = {
  1142. ERASEINFO(0x10000,8),
  1143. }
  1144. }, {
  1145. .mfr_id = CFI_MFR_MACRONIX,
  1146. .dev_id = MX29LV160T,
  1147. .name = "MXIC MX29LV160T",
  1148. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1149. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1150. .dev_size = SIZE_2MiB,
  1151. .cmd_set = P_ID_AMD_STD,
  1152. .nr_regions = 4,
  1153. .regions = {
  1154. ERASEINFO(0x10000,31),
  1155. ERASEINFO(0x08000,1),
  1156. ERASEINFO(0x02000,2),
  1157. ERASEINFO(0x04000,1)
  1158. }
  1159. }, {
  1160. .mfr_id = CFI_MFR_NEC,
  1161. .dev_id = UPD29F064115,
  1162. .name = "NEC uPD29F064115",
  1163. .devtypes = CFI_DEVICETYPE_X16,
  1164. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1165. .dev_size = SIZE_8MiB,
  1166. .cmd_set = P_ID_AMD_STD,
  1167. .nr_regions = 3,
  1168. .regions = {
  1169. ERASEINFO(0x2000,8),
  1170. ERASEINFO(0x10000,126),
  1171. ERASEINFO(0x2000,8),
  1172. }
  1173. }, {
  1174. .mfr_id = CFI_MFR_MACRONIX,
  1175. .dev_id = MX29LV160B,
  1176. .name = "MXIC MX29LV160B",
  1177. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1178. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1179. .dev_size = SIZE_2MiB,
  1180. .cmd_set = P_ID_AMD_STD,
  1181. .nr_regions = 4,
  1182. .regions = {
  1183. ERASEINFO(0x04000,1),
  1184. ERASEINFO(0x02000,2),
  1185. ERASEINFO(0x08000,1),
  1186. ERASEINFO(0x10000,31)
  1187. }
  1188. }, {
  1189. .mfr_id = CFI_MFR_MACRONIX,
  1190. .dev_id = MX29F040,
  1191. .name = "Macronix MX29F040",
  1192. .devtypes = CFI_DEVICETYPE_X8,
  1193. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1194. .dev_size = SIZE_512KiB,
  1195. .cmd_set = P_ID_AMD_STD,
  1196. .nr_regions = 1,
  1197. .regions = {
  1198. ERASEINFO(0x10000,8),
  1199. }
  1200. }, {
  1201. .mfr_id = CFI_MFR_MACRONIX,
  1202. .dev_id = MX29F016,
  1203. .name = "Macronix MX29F016",
  1204. .devtypes = CFI_DEVICETYPE_X8,
  1205. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1206. .dev_size = SIZE_2MiB,
  1207. .cmd_set = P_ID_AMD_STD,
  1208. .nr_regions = 1,
  1209. .regions = {
  1210. ERASEINFO(0x10000,32),
  1211. }
  1212. }, {
  1213. .mfr_id = CFI_MFR_MACRONIX,
  1214. .dev_id = MX29F004T,
  1215. .name = "Macronix MX29F004T",
  1216. .devtypes = CFI_DEVICETYPE_X8,
  1217. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1218. .dev_size = SIZE_512KiB,
  1219. .cmd_set = P_ID_AMD_STD,
  1220. .nr_regions = 4,
  1221. .regions = {
  1222. ERASEINFO(0x10000,7),
  1223. ERASEINFO(0x08000,1),
  1224. ERASEINFO(0x02000,2),
  1225. ERASEINFO(0x04000,1),
  1226. }
  1227. }, {
  1228. .mfr_id = CFI_MFR_MACRONIX,
  1229. .dev_id = MX29F004B,
  1230. .name = "Macronix MX29F004B",
  1231. .devtypes = CFI_DEVICETYPE_X8,
  1232. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1233. .dev_size = SIZE_512KiB,
  1234. .cmd_set = P_ID_AMD_STD,
  1235. .nr_regions = 4,
  1236. .regions = {
  1237. ERASEINFO(0x04000,1),
  1238. ERASEINFO(0x02000,2),
  1239. ERASEINFO(0x08000,1),
  1240. ERASEINFO(0x10000,7),
  1241. }
  1242. }, {
  1243. .mfr_id = CFI_MFR_MACRONIX,
  1244. .dev_id = MX29F002T,
  1245. .name = "Macronix MX29F002T",
  1246. .devtypes = CFI_DEVICETYPE_X8,
  1247. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1248. .dev_size = SIZE_256KiB,
  1249. .cmd_set = P_ID_AMD_STD,
  1250. .nr_regions = 4,
  1251. .regions = {
  1252. ERASEINFO(0x10000,3),
  1253. ERASEINFO(0x08000,1),
  1254. ERASEINFO(0x02000,2),
  1255. ERASEINFO(0x04000,1),
  1256. }
  1257. }, {
  1258. .mfr_id = CFI_MFR_PMC,
  1259. .dev_id = PM49FL002,
  1260. .name = "PMC Pm49FL002",
  1261. .devtypes = CFI_DEVICETYPE_X8,
  1262. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1263. .dev_size = SIZE_256KiB,
  1264. .cmd_set = P_ID_AMD_STD,
  1265. .nr_regions = 1,
  1266. .regions = {
  1267. ERASEINFO( 0x01000, 64 )
  1268. }
  1269. }, {
  1270. .mfr_id = CFI_MFR_PMC,
  1271. .dev_id = PM49FL004,
  1272. .name = "PMC Pm49FL004",
  1273. .devtypes = CFI_DEVICETYPE_X8,
  1274. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1275. .dev_size = SIZE_512KiB,
  1276. .cmd_set = P_ID_AMD_STD,
  1277. .nr_regions = 1,
  1278. .regions = {
  1279. ERASEINFO( 0x01000, 128 )
  1280. }
  1281. }, {
  1282. .mfr_id = CFI_MFR_PMC,
  1283. .dev_id = PM49FL008,
  1284. .name = "PMC Pm49FL008",
  1285. .devtypes = CFI_DEVICETYPE_X8,
  1286. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1287. .dev_size = SIZE_1MiB,
  1288. .cmd_set = P_ID_AMD_STD,
  1289. .nr_regions = 1,
  1290. .regions = {
  1291. ERASEINFO( 0x01000, 256 )
  1292. }
  1293. }, {
  1294. .mfr_id = CFI_MFR_SHARP,
  1295. .dev_id = LH28F640BF,
  1296. .name = "LH28F640BF",
  1297. .devtypes = CFI_DEVICETYPE_X16,
  1298. .uaddr = MTD_UADDR_UNNECESSARY,
  1299. .dev_size = SIZE_8MiB,
  1300. .cmd_set = P_ID_INTEL_EXT,
  1301. .nr_regions = 2,
  1302. .regions = {
  1303. ERASEINFO(0x10000, 127),
  1304. ERASEINFO(0x02000, 8),
  1305. }
  1306. }, {
  1307. .mfr_id = CFI_MFR_SST,
  1308. .dev_id = SST39LF512,
  1309. .name = "SST 39LF512",
  1310. .devtypes = CFI_DEVICETYPE_X8,
  1311. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1312. .dev_size = SIZE_64KiB,
  1313. .cmd_set = P_ID_AMD_STD,
  1314. .nr_regions = 1,
  1315. .regions = {
  1316. ERASEINFO(0x01000,16),
  1317. }
  1318. }, {
  1319. .mfr_id = CFI_MFR_SST,
  1320. .dev_id = SST39LF010,
  1321. .name = "SST 39LF010",
  1322. .devtypes = CFI_DEVICETYPE_X8,
  1323. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1324. .dev_size = SIZE_128KiB,
  1325. .cmd_set = P_ID_AMD_STD,
  1326. .nr_regions = 1,
  1327. .regions = {
  1328. ERASEINFO(0x01000,32),
  1329. }
  1330. }, {
  1331. .mfr_id = CFI_MFR_SST,
  1332. .dev_id = SST29EE020,
  1333. .name = "SST 29EE020",
  1334. .devtypes = CFI_DEVICETYPE_X8,
  1335. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1336. .dev_size = SIZE_256KiB,
  1337. .cmd_set = P_ID_SST_PAGE,
  1338. .nr_regions = 1,
  1339. .regions = {ERASEINFO(0x01000,64),
  1340. }
  1341. }, {
  1342. .mfr_id = CFI_MFR_SST,
  1343. .dev_id = SST29LE020,
  1344. .name = "SST 29LE020",
  1345. .devtypes = CFI_DEVICETYPE_X8,
  1346. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1347. .dev_size = SIZE_256KiB,
  1348. .cmd_set = P_ID_SST_PAGE,
  1349. .nr_regions = 1,
  1350. .regions = {ERASEINFO(0x01000,64),
  1351. }
  1352. }, {
  1353. .mfr_id = CFI_MFR_SST,
  1354. .dev_id = SST39LF020,
  1355. .name = "SST 39LF020",
  1356. .devtypes = CFI_DEVICETYPE_X8,
  1357. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1358. .dev_size = SIZE_256KiB,
  1359. .cmd_set = P_ID_AMD_STD,
  1360. .nr_regions = 1,
  1361. .regions = {
  1362. ERASEINFO(0x01000,64),
  1363. }
  1364. }, {
  1365. .mfr_id = CFI_MFR_SST,
  1366. .dev_id = SST39LF040,
  1367. .name = "SST 39LF040",
  1368. .devtypes = CFI_DEVICETYPE_X8,
  1369. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1370. .dev_size = SIZE_512KiB,
  1371. .cmd_set = P_ID_AMD_STD,
  1372. .nr_regions = 1,
  1373. .regions = {
  1374. ERASEINFO(0x01000,128),
  1375. }
  1376. }, {
  1377. .mfr_id = CFI_MFR_SST,
  1378. .dev_id = SST39SF010A,
  1379. .name = "SST 39SF010A",
  1380. .devtypes = CFI_DEVICETYPE_X8,
  1381. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1382. .dev_size = SIZE_128KiB,
  1383. .cmd_set = P_ID_AMD_STD,
  1384. .nr_regions = 1,
  1385. .regions = {
  1386. ERASEINFO(0x01000,32),
  1387. }
  1388. }, {
  1389. .mfr_id = CFI_MFR_SST,
  1390. .dev_id = SST39SF020A,
  1391. .name = "SST 39SF020A",
  1392. .devtypes = CFI_DEVICETYPE_X8,
  1393. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1394. .dev_size = SIZE_256KiB,
  1395. .cmd_set = P_ID_AMD_STD,
  1396. .nr_regions = 1,
  1397. .regions = {
  1398. ERASEINFO(0x01000,64),
  1399. }
  1400. }, {
  1401. .mfr_id = CFI_MFR_SST,
  1402. .dev_id = SST39SF040,
  1403. .name = "SST 39SF040",
  1404. .devtypes = CFI_DEVICETYPE_X8,
  1405. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1406. .dev_size = SIZE_512KiB,
  1407. .cmd_set = P_ID_AMD_STD,
  1408. .nr_regions = 1,
  1409. .regions = {
  1410. ERASEINFO(0x01000,128),
  1411. }
  1412. }, {
  1413. .mfr_id = CFI_MFR_SST,
  1414. .dev_id = SST49LF040B,
  1415. .name = "SST 49LF040B",
  1416. .devtypes = CFI_DEVICETYPE_X8,
  1417. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1418. .dev_size = SIZE_512KiB,
  1419. .cmd_set = P_ID_AMD_STD,
  1420. .nr_regions = 1,
  1421. .regions = {
  1422. ERASEINFO(0x01000,128),
  1423. }
  1424. }, {
  1425. .mfr_id = CFI_MFR_SST,
  1426. .dev_id = SST49LF004B,
  1427. .name = "SST 49LF004B",
  1428. .devtypes = CFI_DEVICETYPE_X8,
  1429. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1430. .dev_size = SIZE_512KiB,
  1431. .cmd_set = P_ID_AMD_STD,
  1432. .nr_regions = 1,
  1433. .regions = {
  1434. ERASEINFO(0x01000,128),
  1435. }
  1436. }, {
  1437. .mfr_id = CFI_MFR_SST,
  1438. .dev_id = SST49LF008A,
  1439. .name = "SST 49LF008A",
  1440. .devtypes = CFI_DEVICETYPE_X8,
  1441. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1442. .dev_size = SIZE_1MiB,
  1443. .cmd_set = P_ID_AMD_STD,
  1444. .nr_regions = 1,
  1445. .regions = {
  1446. ERASEINFO(0x01000,256),
  1447. }
  1448. }, {
  1449. .mfr_id = CFI_MFR_SST,
  1450. .dev_id = SST49LF030A,
  1451. .name = "SST 49LF030A",
  1452. .devtypes = CFI_DEVICETYPE_X8,
  1453. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1454. .dev_size = SIZE_512KiB,
  1455. .cmd_set = P_ID_AMD_STD,
  1456. .nr_regions = 1,
  1457. .regions = {
  1458. ERASEINFO(0x01000,96),
  1459. }
  1460. }, {
  1461. .mfr_id = CFI_MFR_SST,
  1462. .dev_id = SST49LF040A,
  1463. .name = "SST 49LF040A",
  1464. .devtypes = CFI_DEVICETYPE_X8,
  1465. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1466. .dev_size = SIZE_512KiB,
  1467. .cmd_set = P_ID_AMD_STD,
  1468. .nr_regions = 1,
  1469. .regions = {
  1470. ERASEINFO(0x01000,128),
  1471. }
  1472. }, {
  1473. .mfr_id = CFI_MFR_SST,
  1474. .dev_id = SST49LF080A,
  1475. .name = "SST 49LF080A",
  1476. .devtypes = CFI_DEVICETYPE_X8,
  1477. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1478. .dev_size = SIZE_1MiB,
  1479. .cmd_set = P_ID_AMD_STD,
  1480. .nr_regions = 1,
  1481. .regions = {
  1482. ERASEINFO(0x01000,256),
  1483. }
  1484. }, {
  1485. .mfr_id = CFI_MFR_SST, /* should be CFI */
  1486. .dev_id = SST39LF160,
  1487. .name = "SST 39LF160",
  1488. .devtypes = CFI_DEVICETYPE_X16,
  1489. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1490. .dev_size = SIZE_2MiB,
  1491. .cmd_set = P_ID_AMD_STD,
  1492. .nr_regions = 2,
  1493. .regions = {
  1494. ERASEINFO(0x1000,256),
  1495. ERASEINFO(0x1000,256)
  1496. }
  1497. }, {
  1498. .mfr_id = CFI_MFR_SST, /* should be CFI */
  1499. .dev_id = SST39VF1601,
  1500. .name = "SST 39VF1601",
  1501. .devtypes = CFI_DEVICETYPE_X16,
  1502. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1503. .dev_size = SIZE_2MiB,
  1504. .cmd_set = P_ID_AMD_STD,
  1505. .nr_regions = 2,
  1506. .regions = {
  1507. ERASEINFO(0x1000,256),
  1508. ERASEINFO(0x1000,256)
  1509. }
  1510. }, {
  1511. /* CFI is broken: reports AMD_STD, but needs custom uaddr */
  1512. .mfr_id = CFI_MFR_SST,
  1513. .dev_id = SST39WF1601,
  1514. .name = "SST 39WF1601",
  1515. .devtypes = CFI_DEVICETYPE_X16,
  1516. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1517. .dev_size = SIZE_2MiB,
  1518. .cmd_set = P_ID_AMD_STD,
  1519. .nr_regions = 2,
  1520. .regions = {
  1521. ERASEINFO(0x1000,256),
  1522. ERASEINFO(0x1000,256)
  1523. }
  1524. }, {
  1525. /* CFI is broken: reports AMD_STD, but needs custom uaddr */
  1526. .mfr_id = CFI_MFR_SST,
  1527. .dev_id = SST39WF1602,
  1528. .name = "SST 39WF1602",
  1529. .devtypes = CFI_DEVICETYPE_X16,
  1530. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1531. .dev_size = SIZE_2MiB,
  1532. .cmd_set = P_ID_AMD_STD,
  1533. .nr_regions = 2,
  1534. .regions = {
  1535. ERASEINFO(0x1000,256),
  1536. ERASEINFO(0x1000,256)
  1537. }
  1538. }, {
  1539. .mfr_id = CFI_MFR_SST, /* should be CFI */
  1540. .dev_id = SST39VF3201,
  1541. .name = "SST 39VF3201",
  1542. .devtypes = CFI_DEVICETYPE_X16,
  1543. .uaddr = MTD_UADDR_0xAAAA_0x5555,
  1544. .dev_size = SIZE_4MiB,
  1545. .cmd_set = P_ID_AMD_STD,
  1546. .nr_regions = 4,
  1547. .regions = {
  1548. ERASEINFO(0x1000,256),
  1549. ERASEINFO(0x1000,256),
  1550. ERASEINFO(0x1000,256),
  1551. ERASEINFO(0x1000,256)
  1552. }
  1553. }, {
  1554. .mfr_id = CFI_MFR_SST,
  1555. .dev_id = SST36VF3203,
  1556. .name = "SST 36VF3203",
  1557. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1558. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1559. .dev_size = SIZE_4MiB,
  1560. .cmd_set = P_ID_AMD_STD,
  1561. .nr_regions = 1,
  1562. .regions = {
  1563. ERASEINFO(0x10000,64),
  1564. }
  1565. }, {
  1566. .mfr_id = CFI_MFR_ST,
  1567. .dev_id = M29F800AB,
  1568. .name = "ST M29F800AB",
  1569. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1570. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1571. .dev_size = SIZE_1MiB,
  1572. .cmd_set = P_ID_AMD_STD,
  1573. .nr_regions = 4,
  1574. .regions = {
  1575. ERASEINFO(0x04000,1),
  1576. ERASEINFO(0x02000,2),
  1577. ERASEINFO(0x08000,1),
  1578. ERASEINFO(0x10000,15),
  1579. }
  1580. }, {
  1581. .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */
  1582. .dev_id = M29W800DT,
  1583. .name = "ST M29W800DT",
  1584. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1585. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1586. .dev_size = SIZE_1MiB,
  1587. .cmd_set = P_ID_AMD_STD,
  1588. .nr_regions = 4,
  1589. .regions = {
  1590. ERASEINFO(0x10000,15),
  1591. ERASEINFO(0x08000,1),
  1592. ERASEINFO(0x02000,2),
  1593. ERASEINFO(0x04000,1)
  1594. }
  1595. }, {
  1596. .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */
  1597. .dev_id = M29W800DB,
  1598. .name = "ST M29W800DB",
  1599. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1600. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1601. .dev_size = SIZE_1MiB,
  1602. .cmd_set = P_ID_AMD_STD,
  1603. .nr_regions = 4,
  1604. .regions = {
  1605. ERASEINFO(0x04000,1),
  1606. ERASEINFO(0x02000,2),
  1607. ERASEINFO(0x08000,1),
  1608. ERASEINFO(0x10000,15)
  1609. }
  1610. }, {
  1611. .mfr_id = CFI_MFR_ST,
  1612. .dev_id = M29W400DT,
  1613. .name = "ST M29W400DT",
  1614. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1615. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1616. .dev_size = SIZE_512KiB,
  1617. .cmd_set = P_ID_AMD_STD,
  1618. .nr_regions = 4,
  1619. .regions = {
  1620. ERASEINFO(0x04000,7),
  1621. ERASEINFO(0x02000,1),
  1622. ERASEINFO(0x08000,2),
  1623. ERASEINFO(0x10000,1)
  1624. }
  1625. }, {
  1626. .mfr_id = CFI_MFR_ST,
  1627. .dev_id = M29W400DB,
  1628. .name = "ST M29W400DB",
  1629. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1630. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1631. .dev_size = SIZE_512KiB,
  1632. .cmd_set = P_ID_AMD_STD,
  1633. .nr_regions = 4,
  1634. .regions = {
  1635. ERASEINFO(0x04000,1),
  1636. ERASEINFO(0x02000,2),
  1637. ERASEINFO(0x08000,1),
  1638. ERASEINFO(0x10000,7)
  1639. }
  1640. }, {
  1641. .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */
  1642. .dev_id = M29W160DT,
  1643. .name = "ST M29W160DT",
  1644. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1645. .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
  1646. .dev_size = SIZE_2MiB,
  1647. .cmd_set = P_ID_AMD_STD,
  1648. .nr_regions = 4,
  1649. .regions = {
  1650. ERASEINFO(0x10000,31),
  1651. ERASEINFO(0x08000,1),
  1652. ERASEINFO(0x02000,2),
  1653. ERASEINFO(0x04000,1)
  1654. }
  1655. }, {
  1656. .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */
  1657. .dev_id = M29W160DB,
  1658. .name = "ST M29W160DB",
  1659. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1660. .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
  1661. .dev_size = SIZE_2MiB,
  1662. .cmd_set = P_ID_AMD_STD,
  1663. .nr_regions = 4,
  1664. .regions = {
  1665. ERASEINFO(0x04000,1),
  1666. ERASEINFO(0x02000,2),
  1667. ERASEINFO(0x08000,1),
  1668. ERASEINFO(0x10000,31)
  1669. }
  1670. }, {
  1671. .mfr_id = CFI_MFR_ST,
  1672. .dev_id = M29W040B,
  1673. .name = "ST M29W040B",
  1674. .devtypes = CFI_DEVICETYPE_X8,
  1675. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1676. .dev_size = SIZE_512KiB,
  1677. .cmd_set = P_ID_AMD_STD,
  1678. .nr_regions = 1,
  1679. .regions = {
  1680. ERASEINFO(0x10000,8),
  1681. }
  1682. }, {
  1683. .mfr_id = CFI_MFR_ST,
  1684. .dev_id = M50FW040,
  1685. .name = "ST M50FW040",
  1686. .devtypes = CFI_DEVICETYPE_X8,
  1687. .uaddr = MTD_UADDR_UNNECESSARY,
  1688. .dev_size = SIZE_512KiB,
  1689. .cmd_set = P_ID_INTEL_EXT,
  1690. .nr_regions = 1,
  1691. .regions = {
  1692. ERASEINFO(0x10000,8),
  1693. }
  1694. }, {
  1695. .mfr_id = CFI_MFR_ST,
  1696. .dev_id = M50FW080,
  1697. .name = "ST M50FW080",
  1698. .devtypes = CFI_DEVICETYPE_X8,
  1699. .uaddr = MTD_UADDR_UNNECESSARY,
  1700. .dev_size = SIZE_1MiB,
  1701. .cmd_set = P_ID_INTEL_EXT,
  1702. .nr_regions = 1,
  1703. .regions = {
  1704. ERASEINFO(0x10000,16),
  1705. }
  1706. }, {
  1707. .mfr_id = CFI_MFR_ST,
  1708. .dev_id = M50FW016,
  1709. .name = "ST M50FW016",
  1710. .devtypes = CFI_DEVICETYPE_X8,
  1711. .uaddr = MTD_UADDR_UNNECESSARY,
  1712. .dev_size = SIZE_2MiB,
  1713. .cmd_set = P_ID_INTEL_EXT,
  1714. .nr_regions = 1,
  1715. .regions = {
  1716. ERASEINFO(0x10000,32),
  1717. }
  1718. }, {
  1719. .mfr_id = CFI_MFR_ST,
  1720. .dev_id = M50LPW080,
  1721. .name = "ST M50LPW080",
  1722. .devtypes = CFI_DEVICETYPE_X8,
  1723. .uaddr = MTD_UADDR_UNNECESSARY,
  1724. .dev_size = SIZE_1MiB,
  1725. .cmd_set = P_ID_INTEL_EXT,
  1726. .nr_regions = 1,
  1727. .regions = {
  1728. ERASEINFO(0x10000,16),
  1729. },
  1730. }, {
  1731. .mfr_id = CFI_MFR_ST,
  1732. .dev_id = M50FLW080A,
  1733. .name = "ST M50FLW080A",
  1734. .devtypes = CFI_DEVICETYPE_X8,
  1735. .uaddr = MTD_UADDR_UNNECESSARY,
  1736. .dev_size = SIZE_1MiB,
  1737. .cmd_set = P_ID_INTEL_EXT,
  1738. .nr_regions = 4,
  1739. .regions = {
  1740. ERASEINFO(0x1000,16),
  1741. ERASEINFO(0x10000,13),
  1742. ERASEINFO(0x1000,16),
  1743. ERASEINFO(0x1000,16),
  1744. }
  1745. }, {
  1746. .mfr_id = CFI_MFR_ST,
  1747. .dev_id = M50FLW080B,
  1748. .name = "ST M50FLW080B",
  1749. .devtypes = CFI_DEVICETYPE_X8,
  1750. .uaddr = MTD_UADDR_UNNECESSARY,
  1751. .dev_size = SIZE_1MiB,
  1752. .cmd_set = P_ID_INTEL_EXT,
  1753. .nr_regions = 4,
  1754. .regions = {
  1755. ERASEINFO(0x1000,16),
  1756. ERASEINFO(0x1000,16),
  1757. ERASEINFO(0x10000,13),
  1758. ERASEINFO(0x1000,16),
  1759. }
  1760. }, {
  1761. .mfr_id = 0xff00 | CFI_MFR_ST,
  1762. .dev_id = 0xff00 | PSD4256G6V,
  1763. .name = "ST PSD4256G6V",
  1764. .devtypes = CFI_DEVICETYPE_X16,
  1765. .uaddr = MTD_UADDR_0x0AAA_0x0554,
  1766. .dev_size = SIZE_1MiB,
  1767. .cmd_set = P_ID_AMD_STD,
  1768. .nr_regions = 1,
  1769. .regions = {
  1770. ERASEINFO(0x10000,16),
  1771. }
  1772. }, {
  1773. .mfr_id = CFI_MFR_TOSHIBA,
  1774. .dev_id = TC58FVT160,
  1775. .name = "Toshiba TC58FVT160",
  1776. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1777. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1778. .dev_size = SIZE_2MiB,
  1779. .cmd_set = P_ID_AMD_STD,
  1780. .nr_regions = 4,
  1781. .regions = {
  1782. ERASEINFO(0x10000,31),
  1783. ERASEINFO(0x08000,1),
  1784. ERASEINFO(0x02000,2),
  1785. ERASEINFO(0x04000,1)
  1786. }
  1787. }, {
  1788. .mfr_id = CFI_MFR_TOSHIBA,
  1789. .dev_id = TC58FVB160,
  1790. .name = "Toshiba TC58FVB160",
  1791. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1792. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1793. .dev_size = SIZE_2MiB,
  1794. .cmd_set = P_ID_AMD_STD,
  1795. .nr_regions = 4,
  1796. .regions = {
  1797. ERASEINFO(0x04000,1),
  1798. ERASEINFO(0x02000,2),
  1799. ERASEINFO(0x08000,1),
  1800. ERASEINFO(0x10000,31)
  1801. }
  1802. }, {
  1803. .mfr_id = CFI_MFR_TOSHIBA,
  1804. .dev_id = TC58FVB321,
  1805. .name = "Toshiba TC58FVB321",
  1806. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1807. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1808. .dev_size = SIZE_4MiB,
  1809. .cmd_set = P_ID_AMD_STD,
  1810. .nr_regions = 2,
  1811. .regions = {
  1812. ERASEINFO(0x02000,8),
  1813. ERASEINFO(0x10000,63)
  1814. }
  1815. }, {
  1816. .mfr_id = CFI_MFR_TOSHIBA,
  1817. .dev_id = TC58FVT321,
  1818. .name = "Toshiba TC58FVT321",
  1819. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1820. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1821. .dev_size = SIZE_4MiB,
  1822. .cmd_set = P_ID_AMD_STD,
  1823. .nr_regions = 2,
  1824. .regions = {
  1825. ERASEINFO(0x10000,63),
  1826. ERASEINFO(0x02000,8)
  1827. }
  1828. }, {
  1829. .mfr_id = CFI_MFR_TOSHIBA,
  1830. .dev_id = TC58FVB641,
  1831. .name = "Toshiba TC58FVB641",
  1832. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1833. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1834. .dev_size = SIZE_8MiB,
  1835. .cmd_set = P_ID_AMD_STD,
  1836. .nr_regions = 2,
  1837. .regions = {
  1838. ERASEINFO(0x02000,8),
  1839. ERASEINFO(0x10000,127)
  1840. }
  1841. }, {
  1842. .mfr_id = CFI_MFR_TOSHIBA,
  1843. .dev_id = TC58FVT641,
  1844. .name = "Toshiba TC58FVT641",
  1845. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1846. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1847. .dev_size = SIZE_8MiB,
  1848. .cmd_set = P_ID_AMD_STD,
  1849. .nr_regions = 2,
  1850. .regions = {
  1851. ERASEINFO(0x10000,127),
  1852. ERASEINFO(0x02000,8)
  1853. }
  1854. }, {
  1855. .mfr_id = CFI_MFR_WINBOND,
  1856. .dev_id = W49V002A,
  1857. .name = "Winbond W49V002A",
  1858. .devtypes = CFI_DEVICETYPE_X8,
  1859. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1860. .dev_size = SIZE_256KiB,
  1861. .cmd_set = P_ID_AMD_STD,
  1862. .nr_regions = 4,
  1863. .regions = {
  1864. ERASEINFO(0x10000, 3),
  1865. ERASEINFO(0x08000, 1),
  1866. ERASEINFO(0x02000, 2),
  1867. ERASEINFO(0x04000, 1),
  1868. }
  1869. }
  1870. };
  1871. static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
  1872. struct cfi_private *cfi)
  1873. {
  1874. map_word result;
  1875. unsigned long mask;
  1876. int bank = 0;
  1877. /* According to JEDEC "Standard Manufacturer's Identification Code"
  1878. * (http://www.jedec.org/download/search/jep106W.pdf)
  1879. * several first banks can contain 0x7f instead of actual ID
  1880. */
  1881. do {
  1882. uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi);
  1883. mask = (1 << (cfi->device_type * 8)) - 1;
  1884. if (ofs >= map->size)
  1885. return 0;
  1886. result = map_read(map, base + ofs);
  1887. bank++;
  1888. } while ((result.x[0] & mask) == CFI_MFR_CONTINUATION);
  1889. return result.x[0] & mask;
  1890. }
  1891. static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
  1892. struct cfi_private *cfi)
  1893. {
  1894. map_word result;
  1895. unsigned long mask;
  1896. u32 ofs = cfi_build_cmd_addr(1, map, cfi);
  1897. mask = (1 << (cfi->device_type * 8)) -1;
  1898. result = map_read(map, base + ofs);
  1899. return result.x[0] & mask;
  1900. }
  1901. static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
  1902. {
  1903. /* Reset */
  1904. /* after checking the datasheets for SST, MACRONIX and ATMEL
  1905. * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
  1906. * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
  1907. * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
  1908. * as they will ignore the writes and don't care what address
  1909. * the F0 is written to */
  1910. if (cfi->addr_unlock1) {
  1911. pr_debug( "reset unlock called %x %x \n",
  1912. cfi->addr_unlock1,cfi->addr_unlock2);
  1913. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1914. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  1915. }
  1916. cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1917. /* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
  1918. * so ensure we're in read mode. Send both the Intel and the AMD command
  1919. * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
  1920. * this should be safe.
  1921. */
  1922. cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
  1923. /* FIXME - should have reset delay before continuing */
  1924. }
  1925. static int cfi_jedec_setup(struct map_info *map, struct cfi_private *cfi, int index)
  1926. {
  1927. int i,num_erase_regions;
  1928. uint8_t uaddr;
  1929. if (!(jedec_table[index].devtypes & cfi->device_type)) {
  1930. pr_debug("Rejecting potential %s with incompatible %d-bit device type\n",
  1931. jedec_table[index].name, 4 * (1<<cfi->device_type));
  1932. return 0;
  1933. }
  1934. printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
  1935. num_erase_regions = jedec_table[index].nr_regions;
  1936. cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
  1937. if (!cfi->cfiq) {
  1938. //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
  1939. return 0;
  1940. }
  1941. memset(cfi->cfiq, 0, sizeof(struct cfi_ident));
  1942. cfi->cfiq->P_ID = jedec_table[index].cmd_set;
  1943. cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
  1944. cfi->cfiq->DevSize = jedec_table[index].dev_size;
  1945. cfi->cfi_mode = CFI_MODE_JEDEC;
  1946. cfi->sector_erase_cmd = CMD(0x30);
  1947. for (i=0; i<num_erase_regions; i++){
  1948. cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
  1949. }
  1950. cfi->cmdset_priv = NULL;
  1951. /* This may be redundant for some cases, but it doesn't hurt */
  1952. cfi->mfr = jedec_table[index].mfr_id;
  1953. cfi->id = jedec_table[index].dev_id;
  1954. uaddr = jedec_table[index].uaddr;
  1955. /* The table has unlock addresses in _bytes_, and we try not to let
  1956. our brains explode when we see the datasheets talking about address
  1957. lines numbered from A-1 to A18. The CFI table has unlock addresses
  1958. in device-words according to the mode the device is connected in */
  1959. cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / cfi->device_type;
  1960. cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / cfi->device_type;
  1961. return 1; /* ok */
  1962. }
  1963. /*
  1964. * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing
  1965. * the mapped address, unlock addresses, and proper chip ID. This function
  1966. * attempts to minimize errors. It is doubtfull that this probe will ever
  1967. * be perfect - consequently there should be some module parameters that
  1968. * could be manually specified to force the chip info.
  1969. */
  1970. static inline int jedec_match( uint32_t base,
  1971. struct map_info *map,
  1972. struct cfi_private *cfi,
  1973. const struct amd_flash_info *finfo )
  1974. {
  1975. int rc = 0; /* failure until all tests pass */
  1976. u32 mfr, id;
  1977. uint8_t uaddr;
  1978. /*
  1979. * The IDs must match. For X16 and X32 devices operating in
  1980. * a lower width ( X8 or X16 ), the device ID's are usually just
  1981. * the lower byte(s) of the larger device ID for wider mode. If
  1982. * a part is found that doesn't fit this assumption (device id for
  1983. * smaller width mode is completely unrealated to full-width mode)
  1984. * then the jedec_table[] will have to be augmented with the IDs
  1985. * for different widths.
  1986. */
  1987. switch (cfi->device_type) {
  1988. case CFI_DEVICETYPE_X8:
  1989. mfr = (uint8_t)finfo->mfr_id;
  1990. id = (uint8_t)finfo->dev_id;
  1991. /* bjd: it seems that if we do this, we can end up
  1992. * detecting 16bit flashes as an 8bit device, even though
  1993. * there aren't.
  1994. */
  1995. if (finfo->dev_id > 0xff) {
  1996. pr_debug("%s(): ID is not 8bit\n",
  1997. __func__);
  1998. goto match_done;
  1999. }
  2000. break;
  2001. case CFI_DEVICETYPE_X16:
  2002. mfr = (uint16_t)finfo->mfr_id;
  2003. id = (uint16_t)finfo->dev_id;
  2004. break;
  2005. case CFI_DEVICETYPE_X32:
  2006. mfr = (uint16_t)finfo->mfr_id;
  2007. id = (uint32_t)finfo->dev_id;
  2008. break;
  2009. default:
  2010. printk(KERN_WARNING
  2011. "MTD %s(): Unsupported device type %d\n",
  2012. __func__, cfi->device_type);
  2013. goto match_done;
  2014. }
  2015. if ( cfi->mfr != mfr || cfi->id != id ) {
  2016. goto match_done;
  2017. }
  2018. /* the part size must fit in the memory window */
  2019. pr_debug("MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
  2020. __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
  2021. if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
  2022. pr_debug("MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
  2023. __func__, finfo->mfr_id, finfo->dev_id,
  2024. 1 << finfo->dev_size );
  2025. goto match_done;
  2026. }
  2027. if (! (finfo->devtypes & cfi->device_type))
  2028. goto match_done;
  2029. uaddr = finfo->uaddr;
  2030. pr_debug("MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
  2031. __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
  2032. if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
  2033. && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
  2034. unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
  2035. pr_debug("MTD %s(): 0x%.4x 0x%.4x did not match\n",
  2036. __func__,
  2037. unlock_addrs[uaddr].addr1,
  2038. unlock_addrs[uaddr].addr2);
  2039. goto match_done;
  2040. }
  2041. /*
  2042. * Make sure the ID's disappear when the device is taken out of
  2043. * ID mode. The only time this should fail when it should succeed
  2044. * is when the ID's are written as data to the same
  2045. * addresses. For this rare and unfortunate case the chip
  2046. * cannot be probed correctly.
  2047. * FIXME - write a driver that takes all of the chip info as
  2048. * module parameters, doesn't probe but forces a load.
  2049. */
  2050. pr_debug("MTD %s(): check ID's disappear when not in ID mode\n",
  2051. __func__ );
  2052. jedec_reset( base, map, cfi );
  2053. mfr = jedec_read_mfr( map, base, cfi );
  2054. id = jedec_read_id( map, base, cfi );
  2055. if ( mfr == cfi->mfr && id == cfi->id ) {
  2056. pr_debug("MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
  2057. "You might need to manually specify JEDEC parameters.\n",
  2058. __func__, cfi->mfr, cfi->id );
  2059. goto match_done;
  2060. }
  2061. /* all tests passed - mark as success */
  2062. rc = 1;
  2063. /*
  2064. * Put the device back in ID mode - only need to do this if we
  2065. * were truly frobbing a real device.
  2066. */
  2067. pr_debug("MTD %s(): return to ID mode\n", __func__ );
  2068. if (cfi->addr_unlock1) {
  2069. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  2070. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  2071. }
  2072. cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  2073. /* FIXME - should have a delay before continuing */
  2074. match_done:
  2075. return rc;
  2076. }
  2077. static int jedec_probe_chip(struct map_info *map, __u32 base,
  2078. unsigned long *chip_map, struct cfi_private *cfi)
  2079. {
  2080. int i;
  2081. enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
  2082. u32 probe_offset1, probe_offset2;
  2083. retry:
  2084. if (!cfi->numchips) {
  2085. uaddr_idx++;
  2086. if (MTD_UADDR_UNNECESSARY == uaddr_idx)
  2087. return 0;
  2088. cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
  2089. cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
  2090. }
  2091. /* Make certain we aren't probing past the end of map */
  2092. if (base >= map->size) {
  2093. printk(KERN_NOTICE
  2094. "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
  2095. base, map->size -1);
  2096. return 0;
  2097. }
  2098. /* Ensure the unlock addresses we try stay inside the map */
  2099. probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi);
  2100. probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi);
  2101. if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
  2102. ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
  2103. goto retry;
  2104. /* Reset */
  2105. jedec_reset(base, map, cfi);
  2106. /* Autoselect Mode */
  2107. if(cfi->addr_unlock1) {
  2108. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  2109. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  2110. }
  2111. cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  2112. /* FIXME - should have a delay before continuing */
  2113. if (!cfi->numchips) {
  2114. /* This is the first time we're called. Set up the CFI
  2115. stuff accordingly and return */
  2116. cfi->mfr = jedec_read_mfr(map, base, cfi);
  2117. cfi->id = jedec_read_id(map, base, cfi);
  2118. pr_debug("Search for id:(%02x %02x) interleave(%d) type(%d)\n",
  2119. cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type);
  2120. for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
  2121. if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
  2122. pr_debug("MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
  2123. __func__, cfi->mfr, cfi->id,
  2124. cfi->addr_unlock1, cfi->addr_unlock2 );
  2125. if (!cfi_jedec_setup(map, cfi, i))
  2126. return 0;
  2127. goto ok_out;
  2128. }
  2129. }
  2130. goto retry;
  2131. } else {
  2132. uint16_t mfr;
  2133. uint16_t id;
  2134. /* Make sure it is a chip of the same manufacturer and id */
  2135. mfr = jedec_read_mfr(map, base, cfi);
  2136. id = jedec_read_id(map, base, cfi);
  2137. if ((mfr != cfi->mfr) || (id != cfi->id)) {
  2138. printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
  2139. map->name, mfr, id, base);
  2140. jedec_reset(base, map, cfi);
  2141. return 0;
  2142. }
  2143. }
  2144. /* Check each previous chip locations to see if it's an alias */
  2145. for (i=0; i < (base >> cfi->chipshift); i++) {
  2146. unsigned long start;
  2147. if(!test_bit(i, chip_map)) {
  2148. continue; /* Skip location; no valid chip at this address */
  2149. }
  2150. start = i << cfi->chipshift;
  2151. if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
  2152. jedec_read_id(map, start, cfi) == cfi->id) {
  2153. /* Eep. This chip also looks like it's in autoselect mode.
  2154. Is it an alias for the new one? */
  2155. jedec_reset(start, map, cfi);
  2156. /* If the device IDs go away, it's an alias */
  2157. if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
  2158. jedec_read_id(map, base, cfi) != cfi->id) {
  2159. printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
  2160. map->name, base, start);
  2161. return 0;
  2162. }
  2163. /* Yes, it's actually got the device IDs as data. Most
  2164. * unfortunate. Stick the new chip in read mode
  2165. * too and if it's the same, assume it's an alias. */
  2166. /* FIXME: Use other modes to do a proper check */
  2167. jedec_reset(base, map, cfi);
  2168. if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
  2169. jedec_read_id(map, base, cfi) == cfi->id) {
  2170. printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
  2171. map->name, base, start);
  2172. return 0;
  2173. }
  2174. }
  2175. }
  2176. /* OK, if we got to here, then none of the previous chips appear to
  2177. be aliases for the current one. */
  2178. set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
  2179. cfi->numchips++;
  2180. ok_out:
  2181. /* Put it back into Read Mode */
  2182. jedec_reset(base, map, cfi);
  2183. printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
  2184. map->name, cfi_interleave(cfi), cfi->device_type*8, base,
  2185. map->bankwidth*8);
  2186. return 1;
  2187. }
  2188. static struct chip_probe jedec_chip_probe = {
  2189. .name = "JEDEC",
  2190. .probe_chip = jedec_probe_chip
  2191. };
  2192. static struct mtd_info *jedec_probe(struct map_info *map)
  2193. {
  2194. /*
  2195. * Just use the generic probe stuff to call our CFI-specific
  2196. * chip_probe routine in all the possible permutations, etc.
  2197. */
  2198. return mtd_do_chip_probe(map, &jedec_chip_probe);
  2199. }
  2200. static struct mtd_chip_driver jedec_chipdrv = {
  2201. .probe = jedec_probe,
  2202. .name = "jedec_probe",
  2203. .module = THIS_MODULE
  2204. };
  2205. static int __init jedec_probe_init(void)
  2206. {
  2207. register_mtd_chip_driver(&jedec_chipdrv);
  2208. return 0;
  2209. }
  2210. static void __exit jedec_probe_exit(void)
  2211. {
  2212. unregister_mtd_chip_driver(&jedec_chipdrv);
  2213. }
  2214. module_init(jedec_probe_init);
  2215. module_exit(jedec_probe_exit);
  2216. MODULE_LICENSE("GPL");
  2217. MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
  2218. MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");