sdhci-s3c.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* linux/drivers/mmc/host/sdhci-s3c.c
  3. *
  4. * Copyright 2008 Openmoko Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * Ben Dooks <ben@simtec.co.uk>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * SDHCI (HSMMC) support for Samsung SoC
  10. */
  11. #include <linux/spinlock.h>
  12. #include <linux/delay.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/platform_data/mmc-sdhci-s3c.h>
  16. #include <linux/slab.h>
  17. #include <linux/clk.h>
  18. #include <linux/io.h>
  19. #include <linux/gpio.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_gpio.h>
  23. #include <linux/pm.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/mmc/host.h>
  26. #include "sdhci.h"
  27. #define MAX_BUS_CLK (4)
  28. #define S3C_SDHCI_CONTROL2 (0x80)
  29. #define S3C_SDHCI_CONTROL3 (0x84)
  30. #define S3C64XX_SDHCI_CONTROL4 (0x8C)
  31. #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
  32. #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
  33. #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
  34. #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
  35. #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
  36. #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
  37. #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
  38. #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
  39. #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
  40. #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
  41. #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
  42. #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
  43. #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
  44. #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
  45. #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
  46. #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
  47. #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
  48. #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
  49. #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
  50. #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
  51. #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
  52. #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
  53. #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
  54. #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
  55. #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
  56. #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
  57. #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
  58. #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
  59. #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
  60. #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
  61. #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
  62. #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
  63. #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
  64. #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
  65. #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
  66. #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
  67. #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
  68. #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
  69. #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
  70. #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
  71. #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
  72. #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
  73. #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
  74. #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
  75. #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
  76. #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
  77. #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
  78. #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
  79. #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
  80. #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
  81. #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
  82. #define S3C64XX_SDHCI_CONTROL4_BUSY (1)
  83. /**
  84. * struct sdhci_s3c - S3C SDHCI instance
  85. * @host: The SDHCI host created
  86. * @pdev: The platform device we where created from.
  87. * @ioarea: The resource created when we claimed the IO area.
  88. * @pdata: The platform data for this controller.
  89. * @cur_clk: The index of the current bus clock.
  90. * @ext_cd_irq: External card detect interrupt.
  91. * @clk_io: The clock for the internal bus interface.
  92. * @clk_rates: Clock frequencies.
  93. * @clk_bus: The clocks that are available for the SD/MMC bus clock.
  94. * @no_divider: No or non-standard internal clock divider.
  95. */
  96. struct sdhci_s3c {
  97. struct sdhci_host *host;
  98. struct platform_device *pdev;
  99. struct resource *ioarea;
  100. struct s3c_sdhci_platdata *pdata;
  101. int cur_clk;
  102. int ext_cd_irq;
  103. struct clk *clk_io;
  104. struct clk *clk_bus[MAX_BUS_CLK];
  105. unsigned long clk_rates[MAX_BUS_CLK];
  106. bool no_divider;
  107. };
  108. /**
  109. * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
  110. * @sdhci_quirks: sdhci host specific quirks.
  111. * @no_divider: no or non-standard internal clock divider.
  112. *
  113. * Specifies platform specific configuration of sdhci controller.
  114. * Note: A structure for driver specific platform data is used for future
  115. * expansion of its usage.
  116. */
  117. struct sdhci_s3c_drv_data {
  118. unsigned int sdhci_quirks;
  119. bool no_divider;
  120. };
  121. static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
  122. {
  123. return sdhci_priv(host);
  124. }
  125. /**
  126. * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
  127. * @host: The SDHCI host instance.
  128. *
  129. * Callback to return the maximum clock rate acheivable by the controller.
  130. */
  131. static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
  132. {
  133. struct sdhci_s3c *ourhost = to_s3c(host);
  134. unsigned long rate, max = 0;
  135. int src;
  136. for (src = 0; src < MAX_BUS_CLK; src++) {
  137. rate = ourhost->clk_rates[src];
  138. if (rate > max)
  139. max = rate;
  140. }
  141. return max;
  142. }
  143. /**
  144. * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
  145. * @ourhost: Our SDHCI instance.
  146. * @src: The source clock index.
  147. * @wanted: The clock frequency wanted.
  148. */
  149. static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
  150. unsigned int src,
  151. unsigned int wanted)
  152. {
  153. unsigned long rate;
  154. struct clk *clksrc = ourhost->clk_bus[src];
  155. int shift;
  156. if (IS_ERR(clksrc))
  157. return UINT_MAX;
  158. /*
  159. * If controller uses a non-standard clock division, find the best clock
  160. * speed possible with selected clock source and skip the division.
  161. */
  162. if (ourhost->no_divider) {
  163. rate = clk_round_rate(clksrc, wanted);
  164. return wanted - rate;
  165. }
  166. rate = ourhost->clk_rates[src];
  167. for (shift = 0; shift <= 8; ++shift) {
  168. if ((rate >> shift) <= wanted)
  169. break;
  170. }
  171. if (shift > 8) {
  172. dev_dbg(&ourhost->pdev->dev,
  173. "clk %d: rate %ld, min rate %lu > wanted %u\n",
  174. src, rate, rate / 256, wanted);
  175. return UINT_MAX;
  176. }
  177. dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
  178. src, rate, wanted, rate >> shift);
  179. return wanted - (rate >> shift);
  180. }
  181. /**
  182. * sdhci_s3c_set_clock - callback on clock change
  183. * @host: The SDHCI host being changed
  184. * @clock: The clock rate being requested.
  185. *
  186. * When the card's clock is going to be changed, look at the new frequency
  187. * and find the best clock source to go with it.
  188. */
  189. static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
  190. {
  191. struct sdhci_s3c *ourhost = to_s3c(host);
  192. unsigned int best = UINT_MAX;
  193. unsigned int delta;
  194. int best_src = 0;
  195. int src;
  196. u32 ctrl;
  197. host->mmc->actual_clock = 0;
  198. /* don't bother if the clock is going off. */
  199. if (clock == 0) {
  200. sdhci_set_clock(host, clock);
  201. return;
  202. }
  203. for (src = 0; src < MAX_BUS_CLK; src++) {
  204. delta = sdhci_s3c_consider_clock(ourhost, src, clock);
  205. if (delta < best) {
  206. best = delta;
  207. best_src = src;
  208. }
  209. }
  210. dev_dbg(&ourhost->pdev->dev,
  211. "selected source %d, clock %d, delta %d\n",
  212. best_src, clock, best);
  213. /* select the new clock source */
  214. if (ourhost->cur_clk != best_src) {
  215. struct clk *clk = ourhost->clk_bus[best_src];
  216. clk_prepare_enable(clk);
  217. if (ourhost->cur_clk >= 0)
  218. clk_disable_unprepare(
  219. ourhost->clk_bus[ourhost->cur_clk]);
  220. ourhost->cur_clk = best_src;
  221. host->max_clk = ourhost->clk_rates[best_src];
  222. }
  223. /* turn clock off to card before changing clock source */
  224. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  225. ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
  226. ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  227. ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
  228. writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
  229. /* reprogram default hardware configuration */
  230. writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
  231. host->ioaddr + S3C64XX_SDHCI_CONTROL4);
  232. ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
  233. ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
  234. S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
  235. S3C_SDHCI_CTRL2_ENFBCLKRX |
  236. S3C_SDHCI_CTRL2_DFCNT_NONE |
  237. S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
  238. writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
  239. /* reconfigure the controller for new clock rate */
  240. ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
  241. if (clock < 25 * 1000000)
  242. ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
  243. writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
  244. sdhci_set_clock(host, clock);
  245. }
  246. /**
  247. * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
  248. * @host: The SDHCI host being queried
  249. *
  250. * To init mmc host properly a minimal clock value is needed. For high system
  251. * bus clock's values the standard formula gives values out of allowed range.
  252. * The clock still can be set to lower values, if clock source other then
  253. * system bus is selected.
  254. */
  255. static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
  256. {
  257. struct sdhci_s3c *ourhost = to_s3c(host);
  258. unsigned long rate, min = ULONG_MAX;
  259. int src;
  260. for (src = 0; src < MAX_BUS_CLK; src++) {
  261. rate = ourhost->clk_rates[src] / 256;
  262. if (!rate)
  263. continue;
  264. if (rate < min)
  265. min = rate;
  266. }
  267. return min;
  268. }
  269. /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
  270. static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
  271. {
  272. struct sdhci_s3c *ourhost = to_s3c(host);
  273. unsigned long rate, max = 0;
  274. int src;
  275. for (src = 0; src < MAX_BUS_CLK; src++) {
  276. struct clk *clk;
  277. clk = ourhost->clk_bus[src];
  278. if (IS_ERR(clk))
  279. continue;
  280. rate = clk_round_rate(clk, ULONG_MAX);
  281. if (rate > max)
  282. max = rate;
  283. }
  284. return max;
  285. }
  286. /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
  287. static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
  288. {
  289. struct sdhci_s3c *ourhost = to_s3c(host);
  290. unsigned long rate, min = ULONG_MAX;
  291. int src;
  292. for (src = 0; src < MAX_BUS_CLK; src++) {
  293. struct clk *clk;
  294. clk = ourhost->clk_bus[src];
  295. if (IS_ERR(clk))
  296. continue;
  297. rate = clk_round_rate(clk, 0);
  298. if (rate < min)
  299. min = rate;
  300. }
  301. return min;
  302. }
  303. /* sdhci_cmu_set_clock - callback on clock change.*/
  304. static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
  305. {
  306. struct sdhci_s3c *ourhost = to_s3c(host);
  307. struct device *dev = &ourhost->pdev->dev;
  308. unsigned long timeout;
  309. u16 clk = 0;
  310. int ret;
  311. host->mmc->actual_clock = 0;
  312. /* If the clock is going off, set to 0 at clock control register */
  313. if (clock == 0) {
  314. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  315. return;
  316. }
  317. sdhci_s3c_set_clock(host, clock);
  318. /* Reset SD Clock Enable */
  319. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  320. clk &= ~SDHCI_CLOCK_CARD_EN;
  321. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  322. ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
  323. if (ret != 0) {
  324. dev_err(dev, "%s: failed to set clock rate %uHz\n",
  325. mmc_hostname(host->mmc), clock);
  326. return;
  327. }
  328. clk = SDHCI_CLOCK_INT_EN;
  329. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  330. /* Wait max 20 ms */
  331. timeout = 20;
  332. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  333. & SDHCI_CLOCK_INT_STABLE)) {
  334. if (timeout == 0) {
  335. dev_err(dev, "%s: Internal clock never stabilised.\n",
  336. mmc_hostname(host->mmc));
  337. return;
  338. }
  339. timeout--;
  340. mdelay(1);
  341. }
  342. clk |= SDHCI_CLOCK_CARD_EN;
  343. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  344. }
  345. static struct sdhci_ops sdhci_s3c_ops = {
  346. .get_max_clock = sdhci_s3c_get_max_clk,
  347. .set_clock = sdhci_s3c_set_clock,
  348. .get_min_clock = sdhci_s3c_get_min_clock,
  349. .set_bus_width = sdhci_set_bus_width,
  350. .reset = sdhci_reset,
  351. .set_uhs_signaling = sdhci_set_uhs_signaling,
  352. };
  353. #ifdef CONFIG_OF
  354. static int sdhci_s3c_parse_dt(struct device *dev,
  355. struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
  356. {
  357. struct device_node *node = dev->of_node;
  358. u32 max_width;
  359. /* if the bus-width property is not specified, assume width as 1 */
  360. if (of_property_read_u32(node, "bus-width", &max_width))
  361. max_width = 1;
  362. pdata->max_width = max_width;
  363. /* get the card detection method */
  364. if (of_get_property(node, "broken-cd", NULL)) {
  365. pdata->cd_type = S3C_SDHCI_CD_NONE;
  366. return 0;
  367. }
  368. if (of_get_property(node, "non-removable", NULL)) {
  369. pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
  370. return 0;
  371. }
  372. if (of_get_named_gpio(node, "cd-gpios", 0))
  373. return 0;
  374. /* assuming internal card detect that will be configured by pinctrl */
  375. pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
  376. return 0;
  377. }
  378. #else
  379. static int sdhci_s3c_parse_dt(struct device *dev,
  380. struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
  381. {
  382. return -EINVAL;
  383. }
  384. #endif
  385. #ifdef CONFIG_OF
  386. static const struct of_device_id sdhci_s3c_dt_match[];
  387. #endif
  388. static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
  389. struct platform_device *pdev)
  390. {
  391. #ifdef CONFIG_OF
  392. if (pdev->dev.of_node) {
  393. const struct of_device_id *match;
  394. match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
  395. return (struct sdhci_s3c_drv_data *)match->data;
  396. }
  397. #endif
  398. return (struct sdhci_s3c_drv_data *)
  399. platform_get_device_id(pdev)->driver_data;
  400. }
  401. static int sdhci_s3c_probe(struct platform_device *pdev)
  402. {
  403. struct s3c_sdhci_platdata *pdata;
  404. struct sdhci_s3c_drv_data *drv_data;
  405. struct device *dev = &pdev->dev;
  406. struct sdhci_host *host;
  407. struct sdhci_s3c *sc;
  408. int ret, irq, ptr, clks;
  409. if (!pdev->dev.platform_data && !pdev->dev.of_node) {
  410. dev_err(dev, "no device data specified\n");
  411. return -ENOENT;
  412. }
  413. irq = platform_get_irq(pdev, 0);
  414. if (irq < 0)
  415. return irq;
  416. host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
  417. if (IS_ERR(host)) {
  418. dev_err(dev, "sdhci_alloc_host() failed\n");
  419. return PTR_ERR(host);
  420. }
  421. sc = sdhci_priv(host);
  422. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  423. if (!pdata) {
  424. ret = -ENOMEM;
  425. goto err_pdata_io_clk;
  426. }
  427. if (pdev->dev.of_node) {
  428. ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
  429. if (ret)
  430. goto err_pdata_io_clk;
  431. } else {
  432. memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
  433. }
  434. drv_data = sdhci_s3c_get_driver_data(pdev);
  435. sc->host = host;
  436. sc->pdev = pdev;
  437. sc->pdata = pdata;
  438. sc->cur_clk = -1;
  439. platform_set_drvdata(pdev, host);
  440. sc->clk_io = devm_clk_get(dev, "hsmmc");
  441. if (IS_ERR(sc->clk_io)) {
  442. dev_err(dev, "failed to get io clock\n");
  443. ret = PTR_ERR(sc->clk_io);
  444. goto err_pdata_io_clk;
  445. }
  446. /* enable the local io clock and keep it running for the moment. */
  447. clk_prepare_enable(sc->clk_io);
  448. for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
  449. char name[14];
  450. snprintf(name, 14, "mmc_busclk.%d", ptr);
  451. sc->clk_bus[ptr] = devm_clk_get(dev, name);
  452. if (IS_ERR(sc->clk_bus[ptr]))
  453. continue;
  454. clks++;
  455. sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
  456. dev_info(dev, "clock source %d: %s (%ld Hz)\n",
  457. ptr, name, sc->clk_rates[ptr]);
  458. }
  459. if (clks == 0) {
  460. dev_err(dev, "failed to find any bus clocks\n");
  461. ret = -ENOENT;
  462. goto err_no_busclks;
  463. }
  464. host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
  465. if (IS_ERR(host->ioaddr)) {
  466. ret = PTR_ERR(host->ioaddr);
  467. goto err_req_regs;
  468. }
  469. /* Ensure we have minimal gpio selected CMD/CLK/Detect */
  470. if (pdata->cfg_gpio)
  471. pdata->cfg_gpio(pdev, pdata->max_width);
  472. host->hw_name = "samsung-hsmmc";
  473. host->ops = &sdhci_s3c_ops;
  474. host->quirks = 0;
  475. host->quirks2 = 0;
  476. host->irq = irq;
  477. /* Setup quirks for the controller */
  478. host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
  479. host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
  480. if (drv_data) {
  481. host->quirks |= drv_data->sdhci_quirks;
  482. sc->no_divider = drv_data->no_divider;
  483. }
  484. #ifndef CONFIG_MMC_SDHCI_S3C_DMA
  485. /* we currently see overruns on errors, so disable the SDMA
  486. * support as well. */
  487. host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
  488. #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
  489. /* It seems we do not get an DATA transfer complete on non-busy
  490. * transfers, not sure if this is a problem with this specific
  491. * SDHCI block, or a missing configuration that needs to be set. */
  492. host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
  493. /* This host supports the Auto CMD12 */
  494. host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
  495. /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
  496. host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
  497. if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
  498. pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
  499. host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  500. if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
  501. host->mmc->caps = MMC_CAP_NONREMOVABLE;
  502. switch (pdata->max_width) {
  503. case 8:
  504. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  505. fallthrough;
  506. case 4:
  507. host->mmc->caps |= MMC_CAP_4_BIT_DATA;
  508. break;
  509. }
  510. if (pdata->pm_caps)
  511. host->mmc->pm_caps |= pdata->pm_caps;
  512. host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
  513. SDHCI_QUIRK_32BIT_DMA_SIZE);
  514. /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
  515. host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
  516. /*
  517. * If controller does not have internal clock divider,
  518. * we can use overriding functions instead of default.
  519. */
  520. if (sc->no_divider) {
  521. sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
  522. sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
  523. sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
  524. }
  525. /* It supports additional host capabilities if needed */
  526. if (pdata->host_caps)
  527. host->mmc->caps |= pdata->host_caps;
  528. if (pdata->host_caps2)
  529. host->mmc->caps2 |= pdata->host_caps2;
  530. pm_runtime_enable(&pdev->dev);
  531. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  532. pm_runtime_use_autosuspend(&pdev->dev);
  533. pm_suspend_ignore_children(&pdev->dev, 1);
  534. ret = mmc_of_parse(host->mmc);
  535. if (ret)
  536. goto err_req_regs;
  537. ret = sdhci_add_host(host);
  538. if (ret)
  539. goto err_req_regs;
  540. #ifdef CONFIG_PM
  541. if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
  542. clk_disable_unprepare(sc->clk_io);
  543. #endif
  544. return 0;
  545. err_req_regs:
  546. pm_runtime_disable(&pdev->dev);
  547. err_no_busclks:
  548. clk_disable_unprepare(sc->clk_io);
  549. err_pdata_io_clk:
  550. sdhci_free_host(host);
  551. return ret;
  552. }
  553. static int sdhci_s3c_remove(struct platform_device *pdev)
  554. {
  555. struct sdhci_host *host = platform_get_drvdata(pdev);
  556. struct sdhci_s3c *sc = sdhci_priv(host);
  557. if (sc->ext_cd_irq)
  558. free_irq(sc->ext_cd_irq, sc);
  559. #ifdef CONFIG_PM
  560. if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
  561. clk_prepare_enable(sc->clk_io);
  562. #endif
  563. sdhci_remove_host(host, 1);
  564. pm_runtime_dont_use_autosuspend(&pdev->dev);
  565. pm_runtime_disable(&pdev->dev);
  566. clk_disable_unprepare(sc->clk_io);
  567. sdhci_free_host(host);
  568. return 0;
  569. }
  570. #ifdef CONFIG_PM_SLEEP
  571. static int sdhci_s3c_suspend(struct device *dev)
  572. {
  573. struct sdhci_host *host = dev_get_drvdata(dev);
  574. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  575. mmc_retune_needed(host->mmc);
  576. return sdhci_suspend_host(host);
  577. }
  578. static int sdhci_s3c_resume(struct device *dev)
  579. {
  580. struct sdhci_host *host = dev_get_drvdata(dev);
  581. return sdhci_resume_host(host);
  582. }
  583. #endif
  584. #ifdef CONFIG_PM
  585. static int sdhci_s3c_runtime_suspend(struct device *dev)
  586. {
  587. struct sdhci_host *host = dev_get_drvdata(dev);
  588. struct sdhci_s3c *ourhost = to_s3c(host);
  589. struct clk *busclk = ourhost->clk_io;
  590. int ret;
  591. ret = sdhci_runtime_suspend_host(host);
  592. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  593. mmc_retune_needed(host->mmc);
  594. if (ourhost->cur_clk >= 0)
  595. clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
  596. clk_disable_unprepare(busclk);
  597. return ret;
  598. }
  599. static int sdhci_s3c_runtime_resume(struct device *dev)
  600. {
  601. struct sdhci_host *host = dev_get_drvdata(dev);
  602. struct sdhci_s3c *ourhost = to_s3c(host);
  603. struct clk *busclk = ourhost->clk_io;
  604. int ret;
  605. clk_prepare_enable(busclk);
  606. if (ourhost->cur_clk >= 0)
  607. clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
  608. ret = sdhci_runtime_resume_host(host, 0);
  609. return ret;
  610. }
  611. #endif
  612. static const struct dev_pm_ops sdhci_s3c_pmops = {
  613. SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
  614. SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
  615. NULL)
  616. };
  617. static const struct platform_device_id sdhci_s3c_driver_ids[] = {
  618. {
  619. .name = "s3c-sdhci",
  620. .driver_data = (kernel_ulong_t)NULL,
  621. },
  622. { }
  623. };
  624. MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
  625. #ifdef CONFIG_OF
  626. static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
  627. .no_divider = true,
  628. };
  629. static const struct of_device_id sdhci_s3c_dt_match[] = {
  630. { .compatible = "samsung,s3c6410-sdhci", },
  631. { .compatible = "samsung,exynos4210-sdhci",
  632. .data = &exynos4_sdhci_drv_data },
  633. {},
  634. };
  635. MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
  636. #endif
  637. static struct platform_driver sdhci_s3c_driver = {
  638. .probe = sdhci_s3c_probe,
  639. .remove = sdhci_s3c_remove,
  640. .id_table = sdhci_s3c_driver_ids,
  641. .driver = {
  642. .name = "s3c-sdhci",
  643. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  644. .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
  645. .pm = &sdhci_s3c_pmops,
  646. },
  647. };
  648. module_platform_driver(sdhci_s3c_driver);
  649. MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
  650. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  651. MODULE_LICENSE("GPL v2");
  652. MODULE_ALIAS("platform:s3c-sdhci");