sdhci-pxav2.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 Marvell International Ltd.
  4. * Zhangfei Gao <zhangfei.gao@marvell.com>
  5. * Kevin Wang <dwang4@marvell.com>
  6. * Jun Nie <njun@marvell.com>
  7. * Qiming Wu <wuqm@marvell.com>
  8. * Philip Rakity <prakity@marvell.com>
  9. */
  10. #include <linux/err.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/clk.h>
  14. #include <linux/module.h>
  15. #include <linux/io.h>
  16. #include <linux/mmc/card.h>
  17. #include <linux/mmc/host.h>
  18. #include <linux/platform_data/pxa_sdhci.h>
  19. #include <linux/slab.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include "sdhci.h"
  23. #include "sdhci-pltfm.h"
  24. #define SD_FIFO_PARAM 0xe0
  25. #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
  26. #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
  27. #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
  28. #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
  29. CLK_GATE_ON | CLK_GATE_CTL)
  30. #define SD_CLOCK_BURST_SIZE_SETUP 0xe6
  31. #define SDCLK_SEL_SHIFT 8
  32. #define SDCLK_SEL_MASK 0x3
  33. #define SDCLK_DELAY_SHIFT 10
  34. #define SDCLK_DELAY_MASK 0x3c
  35. #define SD_CE_ATA_2 0xea
  36. #define MMC_CARD 0x1000
  37. #define MMC_WIDTH 0x0100
  38. static void pxav2_reset(struct sdhci_host *host, u8 mask)
  39. {
  40. struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  41. struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  42. sdhci_reset(host, mask);
  43. if (mask == SDHCI_RESET_ALL) {
  44. u16 tmp = 0;
  45. /*
  46. * tune timing of read data/command when crc error happen
  47. * no performance impact
  48. */
  49. if (pdata && pdata->clk_delay_sel == 1) {
  50. tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  51. tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
  52. tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  53. << SDCLK_DELAY_SHIFT;
  54. tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
  55. tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
  56. writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  57. }
  58. if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
  59. tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  60. tmp &= ~CLK_GATE_SETTING_BITS;
  61. writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  62. } else {
  63. tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  64. tmp &= ~CLK_GATE_SETTING_BITS;
  65. tmp |= CLK_GATE_SETTING_BITS;
  66. writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  67. }
  68. }
  69. }
  70. static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
  71. {
  72. u8 ctrl;
  73. u16 tmp;
  74. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  75. tmp = readw(host->ioaddr + SD_CE_ATA_2);
  76. if (width == MMC_BUS_WIDTH_8) {
  77. ctrl &= ~SDHCI_CTRL_4BITBUS;
  78. tmp |= MMC_CARD | MMC_WIDTH;
  79. } else {
  80. tmp &= ~(MMC_CARD | MMC_WIDTH);
  81. if (width == MMC_BUS_WIDTH_4)
  82. ctrl |= SDHCI_CTRL_4BITBUS;
  83. else
  84. ctrl &= ~SDHCI_CTRL_4BITBUS;
  85. }
  86. writew(tmp, host->ioaddr + SD_CE_ATA_2);
  87. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  88. }
  89. static const struct sdhci_ops pxav2_sdhci_ops = {
  90. .set_clock = sdhci_set_clock,
  91. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  92. .set_bus_width = pxav2_mmc_set_bus_width,
  93. .reset = pxav2_reset,
  94. .set_uhs_signaling = sdhci_set_uhs_signaling,
  95. };
  96. #ifdef CONFIG_OF
  97. static const struct of_device_id sdhci_pxav2_of_match[] = {
  98. {
  99. .compatible = "mrvl,pxav2-mmc",
  100. },
  101. {},
  102. };
  103. MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
  104. static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
  105. {
  106. struct sdhci_pxa_platdata *pdata;
  107. struct device_node *np = dev->of_node;
  108. u32 bus_width;
  109. u32 clk_delay_cycles;
  110. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  111. if (!pdata)
  112. return NULL;
  113. if (of_find_property(np, "non-removable", NULL))
  114. pdata->flags |= PXA_FLAG_CARD_PERMANENT;
  115. of_property_read_u32(np, "bus-width", &bus_width);
  116. if (bus_width == 8)
  117. pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
  118. of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
  119. if (clk_delay_cycles > 0) {
  120. pdata->clk_delay_sel = 1;
  121. pdata->clk_delay_cycles = clk_delay_cycles;
  122. }
  123. return pdata;
  124. }
  125. #else
  126. static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
  127. {
  128. return NULL;
  129. }
  130. #endif
  131. static int sdhci_pxav2_probe(struct platform_device *pdev)
  132. {
  133. struct sdhci_pltfm_host *pltfm_host;
  134. struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  135. struct device *dev = &pdev->dev;
  136. struct sdhci_host *host = NULL;
  137. const struct of_device_id *match;
  138. int ret;
  139. struct clk *clk;
  140. host = sdhci_pltfm_init(pdev, NULL, 0);
  141. if (IS_ERR(host))
  142. return PTR_ERR(host);
  143. pltfm_host = sdhci_priv(host);
  144. clk = devm_clk_get(dev, "PXA-SDHCLK");
  145. if (IS_ERR(clk)) {
  146. dev_err(dev, "failed to get io clock\n");
  147. ret = PTR_ERR(clk);
  148. goto free;
  149. }
  150. pltfm_host->clk = clk;
  151. ret = clk_prepare_enable(clk);
  152. if (ret) {
  153. dev_err(&pdev->dev, "failed to enable io clock\n");
  154. goto free;
  155. }
  156. host->quirks = SDHCI_QUIRK_BROKEN_ADMA
  157. | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
  158. | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
  159. match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
  160. if (match) {
  161. pdata = pxav2_get_mmc_pdata(dev);
  162. }
  163. if (pdata) {
  164. if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
  165. /* on-chip device */
  166. host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  167. host->mmc->caps |= MMC_CAP_NONREMOVABLE;
  168. }
  169. /* If slot design supports 8 bit data, indicate this to MMC. */
  170. if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
  171. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  172. if (pdata->quirks)
  173. host->quirks |= pdata->quirks;
  174. if (pdata->host_caps)
  175. host->mmc->caps |= pdata->host_caps;
  176. if (pdata->pm_caps)
  177. host->mmc->pm_caps |= pdata->pm_caps;
  178. }
  179. host->ops = &pxav2_sdhci_ops;
  180. ret = sdhci_add_host(host);
  181. if (ret)
  182. goto disable_clk;
  183. return 0;
  184. disable_clk:
  185. clk_disable_unprepare(clk);
  186. free:
  187. sdhci_pltfm_free(pdev);
  188. return ret;
  189. }
  190. static struct platform_driver sdhci_pxav2_driver = {
  191. .driver = {
  192. .name = "sdhci-pxav2",
  193. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  194. .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
  195. .pm = &sdhci_pltfm_pmops,
  196. },
  197. .probe = sdhci_pxav2_probe,
  198. .remove = sdhci_pltfm_unregister,
  199. };
  200. module_platform_driver(sdhci_pxav2_driver);
  201. MODULE_DESCRIPTION("SDHCI driver for pxav2");
  202. MODULE_AUTHOR("Marvell International Ltd.");
  203. MODULE_LICENSE("GPL v2");