sdhci-cns3xxx.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SDHCI support for CNS3xxx SoC
  4. *
  5. * Copyright 2008 Cavium Networks
  6. * Copyright 2010 MontaVista Software, LLC.
  7. *
  8. * Authors: Scott Shu
  9. * Anton Vorontsov <avorontsov@mvista.com>
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/module.h>
  15. #include "sdhci-pltfm.h"
  16. static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
  17. {
  18. return 150000000;
  19. }
  20. static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock)
  21. {
  22. struct device *dev = mmc_dev(host->mmc);
  23. int div = 1;
  24. u16 clk;
  25. unsigned long timeout;
  26. host->mmc->actual_clock = 0;
  27. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  28. if (clock == 0)
  29. return;
  30. while (host->max_clk / div > clock) {
  31. /*
  32. * On CNS3xxx divider grows linearly up to 4, and then
  33. * exponentially up to 256.
  34. */
  35. if (div < 4)
  36. div += 1;
  37. else if (div < 256)
  38. div *= 2;
  39. else
  40. break;
  41. }
  42. dev_dbg(dev, "desired SD clock: %d, actual: %d\n",
  43. clock, host->max_clk / div);
  44. /* Divide by 3 is special. */
  45. if (div != 3)
  46. div >>= 1;
  47. clk = div << SDHCI_DIVIDER_SHIFT;
  48. clk |= SDHCI_CLOCK_INT_EN;
  49. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  50. timeout = 20;
  51. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  52. & SDHCI_CLOCK_INT_STABLE)) {
  53. if (timeout == 0) {
  54. dev_warn(dev, "clock is unstable");
  55. break;
  56. }
  57. timeout--;
  58. mdelay(1);
  59. }
  60. clk |= SDHCI_CLOCK_CARD_EN;
  61. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  62. }
  63. static const struct sdhci_ops sdhci_cns3xxx_ops = {
  64. .get_max_clock = sdhci_cns3xxx_get_max_clk,
  65. .set_clock = sdhci_cns3xxx_set_clock,
  66. .set_bus_width = sdhci_set_bus_width,
  67. .reset = sdhci_reset,
  68. .set_uhs_signaling = sdhci_set_uhs_signaling,
  69. };
  70. static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
  71. .ops = &sdhci_cns3xxx_ops,
  72. .quirks = SDHCI_QUIRK_BROKEN_DMA |
  73. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  74. SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
  75. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
  76. SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
  77. };
  78. static int sdhci_cns3xxx_probe(struct platform_device *pdev)
  79. {
  80. return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
  81. }
  82. static struct platform_driver sdhci_cns3xxx_driver = {
  83. .driver = {
  84. .name = "sdhci-cns3xxx",
  85. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  86. .pm = &sdhci_pltfm_pmops,
  87. },
  88. .probe = sdhci_cns3xxx_probe,
  89. .remove = sdhci_pltfm_unregister,
  90. };
  91. module_platform_driver(sdhci_cns3xxx_driver);
  92. MODULE_DESCRIPTION("SDHCI driver for CNS3xxx");
  93. MODULE_AUTHOR("Scott Shu, "
  94. "Anton Vorontsov <avorontsov@mvista.com>");
  95. MODULE_LICENSE("GPL v2");