sdhci-cadence.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/bits.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/module.h>
  10. #include <linux/mmc/host.h>
  11. #include <linux/mmc/mmc.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include "sdhci-pltfm.h"
  15. /* HRS - Host Register Set (specific to Cadence) */
  16. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  17. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  18. #define SDHCI_CDNS_HRS04_RD BIT(25)
  19. #define SDHCI_CDNS_HRS04_WR BIT(24)
  20. #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
  21. #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
  22. #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
  23. #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
  24. #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
  25. #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
  26. #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
  27. #define SDHCI_CDNS_HRS06_MODE_SD 0x0
  28. #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
  29. #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
  30. #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
  31. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
  32. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
  33. /* SRS - Slot Register Set (SDHCI-compatible) */
  34. #define SDHCI_CDNS_SRS_BASE 0x200
  35. /* PHY */
  36. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  37. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  38. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  39. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  40. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  41. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  42. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  43. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  44. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  45. #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
  46. #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
  47. #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
  48. /*
  49. * The tuned val register is 6 bit-wide, but not the whole of the range is
  50. * available. The range 0-42 seems to be available (then 43 wraps around to 0)
  51. * but I am not quite sure if it is official. Use only 0 to 39 for safety.
  52. */
  53. #define SDHCI_CDNS_MAX_TUNING_LOOP 40
  54. struct sdhci_cdns_phy_param {
  55. u8 addr;
  56. u8 data;
  57. };
  58. struct sdhci_cdns_priv {
  59. void __iomem *hrs_addr;
  60. bool enhanced_strobe;
  61. unsigned int nr_phy_params;
  62. struct sdhci_cdns_phy_param phy_params[];
  63. };
  64. struct sdhci_cdns_phy_cfg {
  65. const char *property;
  66. u8 addr;
  67. };
  68. static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  69. { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  70. { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  71. { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  72. { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  73. { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  74. { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  75. { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  76. { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  77. { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  78. { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  79. { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  80. };
  81. static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
  82. u8 addr, u8 data)
  83. {
  84. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
  85. u32 tmp;
  86. int ret;
  87. ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
  88. 0, 10);
  89. if (ret)
  90. return ret;
  91. tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  92. FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  93. writel(tmp, reg);
  94. tmp |= SDHCI_CDNS_HRS04_WR;
  95. writel(tmp, reg);
  96. ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
  97. if (ret)
  98. return ret;
  99. tmp &= ~SDHCI_CDNS_HRS04_WR;
  100. writel(tmp, reg);
  101. ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
  102. 0, 10);
  103. return ret;
  104. }
  105. static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
  106. {
  107. unsigned int count = 0;
  108. int i;
  109. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
  110. if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
  111. count++;
  112. return count;
  113. }
  114. static void sdhci_cdns_phy_param_parse(struct device_node *np,
  115. struct sdhci_cdns_priv *priv)
  116. {
  117. struct sdhci_cdns_phy_param *p = priv->phy_params;
  118. u32 val;
  119. int ret, i;
  120. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
  121. ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
  122. &val);
  123. if (ret)
  124. continue;
  125. p->addr = sdhci_cdns_phy_cfgs[i].addr;
  126. p->data = val;
  127. p++;
  128. }
  129. }
  130. static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
  131. {
  132. int ret, i;
  133. for (i = 0; i < priv->nr_phy_params; i++) {
  134. ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
  135. priv->phy_params[i].data);
  136. if (ret)
  137. return ret;
  138. }
  139. return 0;
  140. }
  141. static void *sdhci_cdns_priv(struct sdhci_host *host)
  142. {
  143. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  144. return sdhci_pltfm_priv(pltfm_host);
  145. }
  146. static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
  147. {
  148. /*
  149. * Cadence's spec says the Timeout Clock Frequency is the same as the
  150. * Base Clock Frequency.
  151. */
  152. return host->max_clk;
  153. }
  154. static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
  155. {
  156. u32 tmp;
  157. /* The speed mode for eMMC is selected by HRS06 register */
  158. tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
  159. tmp &= ~SDHCI_CDNS_HRS06_MODE;
  160. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
  161. writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
  162. }
  163. static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
  164. {
  165. u32 tmp;
  166. tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
  167. return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
  168. }
  169. static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
  170. {
  171. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  172. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
  173. u32 tmp;
  174. int i, ret;
  175. if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
  176. return -EINVAL;
  177. tmp = readl(reg);
  178. tmp &= ~SDHCI_CDNS_HRS06_TUNE;
  179. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
  180. /*
  181. * Workaround for IP errata:
  182. * The IP6116 SD/eMMC PHY design has a timing issue on receive data
  183. * path. Send tune request twice.
  184. */
  185. for (i = 0; i < 2; i++) {
  186. tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
  187. writel(tmp, reg);
  188. ret = readl_poll_timeout(reg, tmp,
  189. !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
  190. 0, 1);
  191. if (ret)
  192. return ret;
  193. }
  194. return 0;
  195. }
  196. /*
  197. * In SD mode, software must not use the hardware tuning and instead perform
  198. * an almost identical procedure to eMMC.
  199. */
  200. static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
  201. {
  202. int cur_streak = 0;
  203. int max_streak = 0;
  204. int end_of_streak = 0;
  205. int i;
  206. /*
  207. * Do not execute tuning for UHS_SDR50 or UHS_DDR50.
  208. * The delay is set by probe, based on the DT properties.
  209. */
  210. if (host->timing != MMC_TIMING_MMC_HS200 &&
  211. host->timing != MMC_TIMING_UHS_SDR104)
  212. return 0;
  213. for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
  214. if (sdhci_cdns_set_tune_val(host, i) ||
  215. mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
  216. cur_streak = 0;
  217. } else { /* good */
  218. cur_streak++;
  219. if (cur_streak > max_streak) {
  220. max_streak = cur_streak;
  221. end_of_streak = i;
  222. }
  223. }
  224. }
  225. if (!max_streak) {
  226. dev_err(mmc_dev(host->mmc), "no tuning point found\n");
  227. return -EIO;
  228. }
  229. return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
  230. }
  231. static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
  232. unsigned int timing)
  233. {
  234. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  235. u32 mode;
  236. switch (timing) {
  237. case MMC_TIMING_MMC_HS:
  238. mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
  239. break;
  240. case MMC_TIMING_MMC_DDR52:
  241. mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
  242. break;
  243. case MMC_TIMING_MMC_HS200:
  244. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
  245. break;
  246. case MMC_TIMING_MMC_HS400:
  247. if (priv->enhanced_strobe)
  248. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
  249. else
  250. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
  251. break;
  252. default:
  253. mode = SDHCI_CDNS_HRS06_MODE_SD;
  254. break;
  255. }
  256. sdhci_cdns_set_emmc_mode(priv, mode);
  257. /* For SD, fall back to the default handler */
  258. if (mode == SDHCI_CDNS_HRS06_MODE_SD)
  259. sdhci_set_uhs_signaling(host, timing);
  260. }
  261. static const struct sdhci_ops sdhci_cdns_ops = {
  262. .set_clock = sdhci_set_clock,
  263. .get_timeout_clock = sdhci_cdns_get_timeout_clock,
  264. .set_bus_width = sdhci_set_bus_width,
  265. .reset = sdhci_reset,
  266. .platform_execute_tuning = sdhci_cdns_execute_tuning,
  267. .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
  268. };
  269. static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
  270. .ops = &sdhci_cdns_ops,
  271. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  272. };
  273. static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
  274. .ops = &sdhci_cdns_ops,
  275. };
  276. static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
  277. struct mmc_ios *ios)
  278. {
  279. struct sdhci_host *host = mmc_priv(mmc);
  280. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  281. u32 mode;
  282. priv->enhanced_strobe = ios->enhanced_strobe;
  283. mode = sdhci_cdns_get_emmc_mode(priv);
  284. if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
  285. sdhci_cdns_set_emmc_mode(priv,
  286. SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
  287. if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
  288. sdhci_cdns_set_emmc_mode(priv,
  289. SDHCI_CDNS_HRS06_MODE_MMC_HS400);
  290. }
  291. static int sdhci_cdns_probe(struct platform_device *pdev)
  292. {
  293. struct sdhci_host *host;
  294. const struct sdhci_pltfm_data *data;
  295. struct sdhci_pltfm_host *pltfm_host;
  296. struct sdhci_cdns_priv *priv;
  297. struct clk *clk;
  298. unsigned int nr_phy_params;
  299. int ret;
  300. struct device *dev = &pdev->dev;
  301. static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
  302. clk = devm_clk_get(dev, NULL);
  303. if (IS_ERR(clk))
  304. return PTR_ERR(clk);
  305. ret = clk_prepare_enable(clk);
  306. if (ret)
  307. return ret;
  308. data = of_device_get_match_data(dev);
  309. if (!data)
  310. data = &sdhci_cdns_pltfm_data;
  311. nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
  312. host = sdhci_pltfm_init(pdev, data,
  313. struct_size(priv, phy_params, nr_phy_params));
  314. if (IS_ERR(host)) {
  315. ret = PTR_ERR(host);
  316. goto disable_clk;
  317. }
  318. pltfm_host = sdhci_priv(host);
  319. pltfm_host->clk = clk;
  320. priv = sdhci_pltfm_priv(pltfm_host);
  321. priv->nr_phy_params = nr_phy_params;
  322. priv->hrs_addr = host->ioaddr;
  323. priv->enhanced_strobe = false;
  324. host->ioaddr += SDHCI_CDNS_SRS_BASE;
  325. host->mmc_host_ops.hs400_enhanced_strobe =
  326. sdhci_cdns_hs400_enhanced_strobe;
  327. sdhci_enable_v4_mode(host);
  328. __sdhci_read_caps(host, &version, NULL, NULL);
  329. sdhci_get_of_property(pdev);
  330. ret = mmc_of_parse(host->mmc);
  331. if (ret)
  332. goto free;
  333. sdhci_cdns_phy_param_parse(dev->of_node, priv);
  334. ret = sdhci_cdns_phy_init(priv);
  335. if (ret)
  336. goto free;
  337. ret = sdhci_add_host(host);
  338. if (ret)
  339. goto free;
  340. return 0;
  341. free:
  342. sdhci_pltfm_free(pdev);
  343. disable_clk:
  344. clk_disable_unprepare(clk);
  345. return ret;
  346. }
  347. #ifdef CONFIG_PM_SLEEP
  348. static int sdhci_cdns_resume(struct device *dev)
  349. {
  350. struct sdhci_host *host = dev_get_drvdata(dev);
  351. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  352. struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
  353. int ret;
  354. ret = clk_prepare_enable(pltfm_host->clk);
  355. if (ret)
  356. return ret;
  357. ret = sdhci_cdns_phy_init(priv);
  358. if (ret)
  359. goto disable_clk;
  360. ret = sdhci_resume_host(host);
  361. if (ret)
  362. goto disable_clk;
  363. return 0;
  364. disable_clk:
  365. clk_disable_unprepare(pltfm_host->clk);
  366. return ret;
  367. }
  368. #endif
  369. static const struct dev_pm_ops sdhci_cdns_pm_ops = {
  370. SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
  371. };
  372. static const struct of_device_id sdhci_cdns_match[] = {
  373. {
  374. .compatible = "socionext,uniphier-sd4hc",
  375. .data = &sdhci_cdns_uniphier_pltfm_data,
  376. },
  377. { .compatible = "cdns,sd4hc" },
  378. { /* sentinel */ }
  379. };
  380. MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
  381. static struct platform_driver sdhci_cdns_driver = {
  382. .driver = {
  383. .name = "sdhci-cdns",
  384. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  385. .pm = &sdhci_cdns_pm_ops,
  386. .of_match_table = sdhci_cdns_match,
  387. },
  388. .probe = sdhci_cdns_probe,
  389. .remove = sdhci_pltfm_unregister,
  390. };
  391. module_platform_driver(sdhci_cdns_driver);
  392. MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
  393. MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
  394. MODULE_LICENSE("GPL");