sdhci-acpi.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Secure Digital Host Controller Interface ACPI driver.
  4. *
  5. * Copyright (c) 2012, Intel Corporation.
  6. */
  7. #include <linux/init.h>
  8. #include <linux/export.h>
  9. #include <linux/module.h>
  10. #include <linux/device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/ioport.h>
  13. #include <linux/io.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/compiler.h>
  16. #include <linux/stddef.h>
  17. #include <linux/bitops.h>
  18. #include <linux/types.h>
  19. #include <linux/err.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/acpi.h>
  22. #include <linux/pm.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/delay.h>
  25. #include <linux/dmi.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/mmc/pm.h>
  28. #include <linux/mmc/slot-gpio.h>
  29. #ifdef CONFIG_X86
  30. #include <asm/cpu_device_id.h>
  31. #include <asm/intel-family.h>
  32. #include <asm/iosf_mbi.h>
  33. #include <linux/pci.h>
  34. #endif
  35. #include "sdhci.h"
  36. enum {
  37. SDHCI_ACPI_SD_CD = BIT(0),
  38. SDHCI_ACPI_RUNTIME_PM = BIT(1),
  39. SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
  40. };
  41. struct sdhci_acpi_chip {
  42. const struct sdhci_ops *ops;
  43. unsigned int quirks;
  44. unsigned int quirks2;
  45. unsigned long caps;
  46. unsigned int caps2;
  47. mmc_pm_flag_t pm_caps;
  48. };
  49. struct sdhci_acpi_slot {
  50. const struct sdhci_acpi_chip *chip;
  51. unsigned int quirks;
  52. unsigned int quirks2;
  53. unsigned long caps;
  54. unsigned int caps2;
  55. mmc_pm_flag_t pm_caps;
  56. unsigned int flags;
  57. size_t priv_size;
  58. int (*probe_slot)(struct platform_device *, struct acpi_device *);
  59. int (*remove_slot)(struct platform_device *);
  60. int (*free_slot)(struct platform_device *pdev);
  61. int (*setup_host)(struct platform_device *pdev);
  62. };
  63. struct sdhci_acpi_host {
  64. struct sdhci_host *host;
  65. const struct sdhci_acpi_slot *slot;
  66. struct platform_device *pdev;
  67. bool use_runtime_pm;
  68. bool is_intel;
  69. bool reset_signal_volt_on_suspend;
  70. unsigned long private[] ____cacheline_aligned;
  71. };
  72. enum {
  73. DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
  74. DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
  75. };
  76. static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
  77. {
  78. return (void *)c->private;
  79. }
  80. static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
  81. {
  82. return c->slot && (c->slot->flags & flag);
  83. }
  84. #define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
  85. #define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
  86. #define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
  87. #define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
  88. enum {
  89. INTEL_DSM_FNS = 0,
  90. INTEL_DSM_V18_SWITCH = 3,
  91. INTEL_DSM_V33_SWITCH = 4,
  92. INTEL_DSM_HS_CAPS = 8,
  93. };
  94. struct intel_host {
  95. u32 dsm_fns;
  96. u32 hs_caps;
  97. };
  98. static const guid_t intel_dsm_guid =
  99. GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
  100. 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
  101. static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
  102. unsigned int fn, u32 *result)
  103. {
  104. union acpi_object *obj;
  105. int err = 0;
  106. obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
  107. if (!obj)
  108. return -EOPNOTSUPP;
  109. if (obj->type == ACPI_TYPE_INTEGER) {
  110. *result = obj->integer.value;
  111. } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
  112. size_t len = min_t(size_t, obj->buffer.length, 4);
  113. *result = 0;
  114. memcpy(result, obj->buffer.pointer, len);
  115. } else {
  116. dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
  117. __func__, fn, obj->type, obj->buffer.length);
  118. err = -EINVAL;
  119. }
  120. ACPI_FREE(obj);
  121. return err;
  122. }
  123. static int intel_dsm(struct intel_host *intel_host, struct device *dev,
  124. unsigned int fn, u32 *result)
  125. {
  126. if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
  127. return -EOPNOTSUPP;
  128. return __intel_dsm(intel_host, dev, fn, result);
  129. }
  130. static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
  131. struct mmc_host *mmc)
  132. {
  133. int err;
  134. intel_host->hs_caps = ~0;
  135. err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
  136. if (err) {
  137. pr_debug("%s: DSM not supported, error %d\n",
  138. mmc_hostname(mmc), err);
  139. return;
  140. }
  141. pr_debug("%s: DSM function mask %#x\n",
  142. mmc_hostname(mmc), intel_host->dsm_fns);
  143. intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
  144. }
  145. static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
  146. struct mmc_ios *ios)
  147. {
  148. struct device *dev = mmc_dev(mmc);
  149. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  150. struct intel_host *intel_host = sdhci_acpi_priv(c);
  151. unsigned int fn;
  152. u32 result = 0;
  153. int err;
  154. err = sdhci_start_signal_voltage_switch(mmc, ios);
  155. if (err)
  156. return err;
  157. switch (ios->signal_voltage) {
  158. case MMC_SIGNAL_VOLTAGE_330:
  159. fn = INTEL_DSM_V33_SWITCH;
  160. break;
  161. case MMC_SIGNAL_VOLTAGE_180:
  162. fn = INTEL_DSM_V18_SWITCH;
  163. break;
  164. default:
  165. return 0;
  166. }
  167. err = intel_dsm(intel_host, dev, fn, &result);
  168. pr_debug("%s: %s DSM fn %u error %d result %u\n",
  169. mmc_hostname(mmc), __func__, fn, err, result);
  170. return 0;
  171. }
  172. static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
  173. {
  174. u8 reg;
  175. reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
  176. reg |= 0x10;
  177. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  178. /* For eMMC, minimum is 1us but give it 9us for good measure */
  179. udelay(9);
  180. reg &= ~0x10;
  181. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  182. /* For eMMC, minimum is 200us but give it 300us for good measure */
  183. usleep_range(300, 1000);
  184. }
  185. static const struct sdhci_ops sdhci_acpi_ops_dflt = {
  186. .set_clock = sdhci_set_clock,
  187. .set_bus_width = sdhci_set_bus_width,
  188. .reset = sdhci_reset,
  189. .set_uhs_signaling = sdhci_set_uhs_signaling,
  190. };
  191. static const struct sdhci_ops sdhci_acpi_ops_int = {
  192. .set_clock = sdhci_set_clock,
  193. .set_bus_width = sdhci_set_bus_width,
  194. .reset = sdhci_reset,
  195. .set_uhs_signaling = sdhci_set_uhs_signaling,
  196. .hw_reset = sdhci_acpi_int_hw_reset,
  197. };
  198. static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
  199. .ops = &sdhci_acpi_ops_int,
  200. };
  201. #ifdef CONFIG_X86
  202. static bool sdhci_acpi_byt(void)
  203. {
  204. static const struct x86_cpu_id byt[] = {
  205. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
  206. {}
  207. };
  208. return x86_match_cpu(byt);
  209. }
  210. static bool sdhci_acpi_cht(void)
  211. {
  212. static const struct x86_cpu_id cht[] = {
  213. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
  214. {}
  215. };
  216. return x86_match_cpu(cht);
  217. }
  218. #define BYT_IOSF_SCCEP 0x63
  219. #define BYT_IOSF_OCP_NETCTRL0 0x1078
  220. #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
  221. static void sdhci_acpi_byt_setting(struct device *dev)
  222. {
  223. u32 val = 0;
  224. if (!sdhci_acpi_byt())
  225. return;
  226. if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
  227. &val)) {
  228. dev_err(dev, "%s read error\n", __func__);
  229. return;
  230. }
  231. if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
  232. return;
  233. val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
  234. if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
  235. val)) {
  236. dev_err(dev, "%s write error\n", __func__);
  237. return;
  238. }
  239. dev_dbg(dev, "%s completed\n", __func__);
  240. }
  241. static bool sdhci_acpi_byt_defer(struct device *dev)
  242. {
  243. if (!sdhci_acpi_byt())
  244. return false;
  245. if (!iosf_mbi_available())
  246. return true;
  247. sdhci_acpi_byt_setting(dev);
  248. return false;
  249. }
  250. static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
  251. unsigned int slot, unsigned int parent_slot)
  252. {
  253. struct pci_dev *dev, *parent, *from = NULL;
  254. while (1) {
  255. dev = pci_get_device(vendor, device, from);
  256. pci_dev_put(from);
  257. if (!dev)
  258. break;
  259. parent = pci_upstream_bridge(dev);
  260. if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
  261. parent && PCI_SLOT(parent->devfn) == parent_slot &&
  262. !pci_upstream_bridge(parent)) {
  263. pci_dev_put(dev);
  264. return true;
  265. }
  266. from = dev;
  267. }
  268. return false;
  269. }
  270. /*
  271. * GPDwin uses PCI wifi which conflicts with SDIO's use of
  272. * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is
  273. * problematic, but since SDIO is only used for wifi, the presence of the PCI
  274. * wifi card in the expected slot with an ACPI companion node, is used to
  275. * indicate that acpi_device_fix_up_power() should be avoided.
  276. */
  277. static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
  278. {
  279. return sdhci_acpi_cht() &&
  280. acpi_dev_hid_uid_match(adev, "80860F14", "2") &&
  281. sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
  282. }
  283. #else
  284. static inline void sdhci_acpi_byt_setting(struct device *dev)
  285. {
  286. }
  287. static inline bool sdhci_acpi_byt_defer(struct device *dev)
  288. {
  289. return false;
  290. }
  291. static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
  292. {
  293. return false;
  294. }
  295. #endif
  296. static int bxt_get_cd(struct mmc_host *mmc)
  297. {
  298. int gpio_cd = mmc_gpio_get_cd(mmc);
  299. struct sdhci_host *host = mmc_priv(mmc);
  300. unsigned long flags;
  301. int ret = 0;
  302. if (!gpio_cd)
  303. return 0;
  304. spin_lock_irqsave(&host->lock, flags);
  305. if (host->flags & SDHCI_DEVICE_DEAD)
  306. goto out;
  307. ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
  308. out:
  309. spin_unlock_irqrestore(&host->lock, flags);
  310. return ret;
  311. }
  312. static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
  313. {
  314. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  315. struct intel_host *intel_host = sdhci_acpi_priv(c);
  316. struct sdhci_host *host = c->host;
  317. if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
  318. sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
  319. sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
  320. host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
  321. if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
  322. host->mmc_host_ops.get_cd = bxt_get_cd;
  323. intel_dsm_init(intel_host, &pdev->dev, host->mmc);
  324. host->mmc_host_ops.start_signal_voltage_switch =
  325. intel_start_signal_voltage_switch;
  326. c->is_intel = true;
  327. return 0;
  328. }
  329. static int intel_setup_host(struct platform_device *pdev)
  330. {
  331. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  332. struct intel_host *intel_host = sdhci_acpi_priv(c);
  333. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
  334. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
  335. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
  336. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
  337. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
  338. c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
  339. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
  340. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
  341. return 0;
  342. }
  343. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
  344. .chip = &sdhci_acpi_chip_int,
  345. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
  346. MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
  347. MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
  348. .flags = SDHCI_ACPI_RUNTIME_PM,
  349. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  350. SDHCI_QUIRK_NO_LED,
  351. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  352. SDHCI_QUIRK2_STOP_WITH_TC |
  353. SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
  354. .probe_slot = intel_probe_slot,
  355. .setup_host = intel_setup_host,
  356. .priv_size = sizeof(struct intel_host),
  357. };
  358. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
  359. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  360. SDHCI_QUIRK_NO_LED |
  361. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  362. .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
  363. .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
  364. MMC_CAP_WAIT_WHILE_BUSY,
  365. .flags = SDHCI_ACPI_RUNTIME_PM,
  366. .pm_caps = MMC_PM_KEEP_POWER,
  367. .probe_slot = intel_probe_slot,
  368. .setup_host = intel_setup_host,
  369. .priv_size = sizeof(struct intel_host),
  370. };
  371. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
  372. .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
  373. SDHCI_ACPI_RUNTIME_PM,
  374. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  375. SDHCI_QUIRK_NO_LED,
  376. .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
  377. SDHCI_QUIRK2_STOP_WITH_TC,
  378. .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
  379. .probe_slot = intel_probe_slot,
  380. .setup_host = intel_setup_host,
  381. .priv_size = sizeof(struct intel_host),
  382. };
  383. #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
  384. #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
  385. static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
  386. {
  387. struct sdhci_host *host = ptr;
  388. sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
  389. sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
  390. return IRQ_HANDLED;
  391. }
  392. static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
  393. {
  394. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  395. struct sdhci_host *host = c->host;
  396. int *irq = sdhci_acpi_priv(c);
  397. *irq = -EINVAL;
  398. if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
  399. return 0;
  400. *irq = platform_get_irq(pdev, 1);
  401. if (*irq < 0)
  402. return 0;
  403. return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
  404. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  405. "sdhci_qcom", host);
  406. }
  407. static int qcom_free_slot(struct platform_device *pdev)
  408. {
  409. struct device *dev = &pdev->dev;
  410. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  411. struct sdhci_host *host = c->host;
  412. struct acpi_device *adev;
  413. int *irq = sdhci_acpi_priv(c);
  414. adev = ACPI_COMPANION(dev);
  415. if (!adev)
  416. return -ENODEV;
  417. if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
  418. return 0;
  419. if (*irq < 0)
  420. return 0;
  421. free_irq(*irq, host);
  422. return 0;
  423. }
  424. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
  425. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  426. .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
  427. .caps = MMC_CAP_NONREMOVABLE,
  428. .priv_size = sizeof(int),
  429. .probe_slot = qcom_probe_slot,
  430. .free_slot = qcom_free_slot,
  431. };
  432. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
  433. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  434. .caps = MMC_CAP_NONREMOVABLE,
  435. };
  436. struct amd_sdhci_host {
  437. bool tuned_clock;
  438. bool dll_enabled;
  439. };
  440. /* AMD sdhci reset dll register. */
  441. #define SDHCI_AMD_RESET_DLL_REGISTER 0x908
  442. static int amd_select_drive_strength(struct mmc_card *card,
  443. unsigned int max_dtr, int host_drv,
  444. int card_drv, int *drv_type)
  445. {
  446. *drv_type = MMC_SET_DRIVER_TYPE_A;
  447. return MMC_SET_DRIVER_TYPE_A;
  448. }
  449. static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
  450. {
  451. struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
  452. struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
  453. /* AMD Platform requires dll setting */
  454. sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
  455. usleep_range(10, 20);
  456. if (enable)
  457. sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
  458. amd_host->dll_enabled = enable;
  459. }
  460. /*
  461. * The initialization sequence for HS400 is:
  462. * HS->HS200->Perform Tuning->HS->HS400
  463. *
  464. * The re-tuning sequence is:
  465. * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
  466. *
  467. * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
  468. * mode. If we switch to a different mode, we need to disable the tuned clock.
  469. * If we have previously performed tuning and switch back to HS200 or
  470. * HS400, we can re-enable the tuned clock.
  471. *
  472. */
  473. static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  474. {
  475. struct sdhci_host *host = mmc_priv(mmc);
  476. struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
  477. struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
  478. unsigned int old_timing = host->timing;
  479. u16 val;
  480. sdhci_set_ios(mmc, ios);
  481. if (old_timing != host->timing && amd_host->tuned_clock) {
  482. if (host->timing == MMC_TIMING_MMC_HS400 ||
  483. host->timing == MMC_TIMING_MMC_HS200) {
  484. val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  485. val |= SDHCI_CTRL_TUNED_CLK;
  486. sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
  487. } else {
  488. val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  489. val &= ~SDHCI_CTRL_TUNED_CLK;
  490. sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
  491. }
  492. /* DLL is only required for HS400 */
  493. if (host->timing == MMC_TIMING_MMC_HS400 &&
  494. !amd_host->dll_enabled)
  495. sdhci_acpi_amd_hs400_dll(host, true);
  496. }
  497. }
  498. static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
  499. {
  500. int err;
  501. struct sdhci_host *host = mmc_priv(mmc);
  502. struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
  503. struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
  504. amd_host->tuned_clock = false;
  505. err = sdhci_execute_tuning(mmc, opcode);
  506. if (!err && !host->tuning_err)
  507. amd_host->tuned_clock = true;
  508. return err;
  509. }
  510. static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
  511. {
  512. struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
  513. struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
  514. if (mask & SDHCI_RESET_ALL) {
  515. amd_host->tuned_clock = false;
  516. sdhci_acpi_amd_hs400_dll(host, false);
  517. }
  518. sdhci_reset(host, mask);
  519. }
  520. static const struct sdhci_ops sdhci_acpi_ops_amd = {
  521. .set_clock = sdhci_set_clock,
  522. .set_bus_width = sdhci_set_bus_width,
  523. .reset = amd_sdhci_reset,
  524. .set_uhs_signaling = sdhci_set_uhs_signaling,
  525. };
  526. static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
  527. .ops = &sdhci_acpi_ops_amd,
  528. };
  529. static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
  530. struct acpi_device *adev)
  531. {
  532. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  533. struct sdhci_host *host = c->host;
  534. sdhci_read_caps(host);
  535. if (host->caps1 & SDHCI_SUPPORT_DDR50)
  536. host->mmc->caps = MMC_CAP_1_8V_DDR;
  537. if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
  538. (host->mmc->caps & MMC_CAP_1_8V_DDR))
  539. host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
  540. /*
  541. * There are two types of presets out in the wild:
  542. * 1) Default/broken presets.
  543. * These presets have two sets of problems:
  544. * a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
  545. * This results in clock frequencies that are 2x higher than
  546. * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
  547. * 100 MHz.x
  548. * b) The HS200 and HS400 driver strengths don't match.
  549. * By default, the SDR104 preset register has a driver strength of
  550. * A, but the (internal) HS400 preset register has a driver
  551. * strength of B. As part of initializing HS400, HS200 tuning
  552. * needs to be performed. Having different driver strengths
  553. * between tuning and operation is wrong. It results in different
  554. * rise/fall times that lead to incorrect sampling.
  555. * 2) Firmware with properly initialized presets.
  556. * These presets have proper clock divisors. i.e., SDR12 => 12MHz,
  557. * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
  558. * HS400 preset driver strengths match.
  559. *
  560. * Enabling presets for HS400 doesn't work for the following reasons:
  561. * 1) sdhci_set_ios has a hard coded list of timings that are used
  562. * to determine if presets should be enabled.
  563. * 2) sdhci_get_preset_value is using a non-standard register to
  564. * read out HS400 presets. The AMD controller doesn't support this
  565. * non-standard register. In fact, it doesn't expose the HS400
  566. * preset register anywhere in the SDHCI memory map. This results
  567. * in reading a garbage value and using the wrong presets.
  568. *
  569. * Since HS400 and HS200 presets must be identical, we could
  570. * instead use the the SDR104 preset register.
  571. *
  572. * If the above issues are resolved we could remove this quirk for
  573. * firmware that that has valid presets (i.e., SDR12 <= 12 MHz).
  574. */
  575. host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  576. host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
  577. host->mmc_host_ops.set_ios = amd_set_ios;
  578. host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
  579. return 0;
  580. }
  581. static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
  582. .chip = &sdhci_acpi_chip_amd,
  583. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
  584. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  585. SDHCI_QUIRK_32BIT_DMA_SIZE |
  586. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  587. .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  588. .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
  589. .priv_size = sizeof(struct amd_sdhci_host),
  590. };
  591. struct sdhci_acpi_uid_slot {
  592. const char *hid;
  593. const char *uid;
  594. const struct sdhci_acpi_slot *slot;
  595. };
  596. static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
  597. { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
  598. { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
  599. { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
  600. { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
  601. { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
  602. { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
  603. { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
  604. { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
  605. { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
  606. { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
  607. { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
  608. { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
  609. { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
  610. { "PNP0D40" },
  611. { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
  612. { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
  613. { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
  614. { },
  615. };
  616. static const struct acpi_device_id sdhci_acpi_ids[] = {
  617. { "80865ACA" },
  618. { "80865ACC" },
  619. { "80865AD0" },
  620. { "80860F14" },
  621. { "80860F16" },
  622. { "INT33BB" },
  623. { "INT33C6" },
  624. { "INT3436" },
  625. { "INT344D" },
  626. { "PNP0D40" },
  627. { "QCOM8051" },
  628. { "QCOM8052" },
  629. { "AMDI0040" },
  630. { },
  631. };
  632. MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
  633. static const struct dmi_system_id sdhci_acpi_quirks[] = {
  634. {
  635. /*
  636. * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
  637. * the SHC1 ACPI device, this bug causes it to reprogram the
  638. * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
  639. * card is (runtime) suspended + resumed. DLDO3 is used for
  640. * the LCD and setting it to 1.8V causes the LCD to go black.
  641. */
  642. .matches = {
  643. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  644. DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
  645. },
  646. .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
  647. },
  648. {
  649. /*
  650. * The Acer Aspire Switch 10 (SW5-012) microSD slot always
  651. * reports the card being write-protected even though microSD
  652. * cards do not have a write-protect switch at all.
  653. */
  654. .matches = {
  655. DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
  656. DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
  657. },
  658. .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
  659. },
  660. {
  661. /*
  662. * The Toshiba WT8-B's microSD slot always reports the card being
  663. * write-protected.
  664. */
  665. .matches = {
  666. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  667. DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
  668. },
  669. .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
  670. },
  671. {} /* Terminating entry */
  672. };
  673. static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
  674. {
  675. const struct sdhci_acpi_uid_slot *u;
  676. for (u = sdhci_acpi_uids; u->hid; u++) {
  677. if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
  678. return u->slot;
  679. }
  680. return NULL;
  681. }
  682. static int sdhci_acpi_probe(struct platform_device *pdev)
  683. {
  684. struct device *dev = &pdev->dev;
  685. const struct sdhci_acpi_slot *slot;
  686. struct acpi_device *device, *child;
  687. const struct dmi_system_id *id;
  688. struct sdhci_acpi_host *c;
  689. struct sdhci_host *host;
  690. struct resource *iomem;
  691. resource_size_t len;
  692. size_t priv_size;
  693. int quirks = 0;
  694. int err;
  695. device = ACPI_COMPANION(dev);
  696. if (!device)
  697. return -ENODEV;
  698. id = dmi_first_match(sdhci_acpi_quirks);
  699. if (id)
  700. quirks = (long)id->driver_data;
  701. slot = sdhci_acpi_get_slot(device);
  702. /* Power on the SDHCI controller and its children */
  703. acpi_device_fix_up_power(device);
  704. if (!sdhci_acpi_no_fixup_child_power(device)) {
  705. list_for_each_entry(child, &device->children, node)
  706. if (child->status.present && child->status.enabled)
  707. acpi_device_fix_up_power(child);
  708. }
  709. if (sdhci_acpi_byt_defer(dev))
  710. return -EPROBE_DEFER;
  711. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  712. if (!iomem)
  713. return -ENOMEM;
  714. len = resource_size(iomem);
  715. if (len < 0x100)
  716. dev_err(dev, "Invalid iomem size!\n");
  717. if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
  718. return -ENOMEM;
  719. priv_size = slot ? slot->priv_size : 0;
  720. host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
  721. if (IS_ERR(host))
  722. return PTR_ERR(host);
  723. c = sdhci_priv(host);
  724. c->host = host;
  725. c->slot = slot;
  726. c->pdev = pdev;
  727. c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
  728. platform_set_drvdata(pdev, c);
  729. host->hw_name = "ACPI";
  730. host->ops = &sdhci_acpi_ops_dflt;
  731. host->irq = platform_get_irq(pdev, 0);
  732. if (host->irq < 0) {
  733. err = -EINVAL;
  734. goto err_free;
  735. }
  736. host->ioaddr = devm_ioremap(dev, iomem->start,
  737. resource_size(iomem));
  738. if (host->ioaddr == NULL) {
  739. err = -ENOMEM;
  740. goto err_free;
  741. }
  742. if (c->slot) {
  743. if (c->slot->probe_slot) {
  744. err = c->slot->probe_slot(pdev, device);
  745. if (err)
  746. goto err_free;
  747. }
  748. if (c->slot->chip) {
  749. host->ops = c->slot->chip->ops;
  750. host->quirks |= c->slot->chip->quirks;
  751. host->quirks2 |= c->slot->chip->quirks2;
  752. host->mmc->caps |= c->slot->chip->caps;
  753. host->mmc->caps2 |= c->slot->chip->caps2;
  754. host->mmc->pm_caps |= c->slot->chip->pm_caps;
  755. }
  756. host->quirks |= c->slot->quirks;
  757. host->quirks2 |= c->slot->quirks2;
  758. host->mmc->caps |= c->slot->caps;
  759. host->mmc->caps2 |= c->slot->caps2;
  760. host->mmc->pm_caps |= c->slot->pm_caps;
  761. }
  762. host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
  763. if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
  764. bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
  765. err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
  766. if (err) {
  767. if (err == -EPROBE_DEFER)
  768. goto err_free;
  769. dev_warn(dev, "failed to setup card detect gpio\n");
  770. c->use_runtime_pm = false;
  771. }
  772. if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
  773. c->reset_signal_volt_on_suspend = true;
  774. if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
  775. host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
  776. }
  777. err = sdhci_setup_host(host);
  778. if (err)
  779. goto err_free;
  780. if (c->slot && c->slot->setup_host) {
  781. err = c->slot->setup_host(pdev);
  782. if (err)
  783. goto err_cleanup;
  784. }
  785. err = __sdhci_add_host(host);
  786. if (err)
  787. goto err_cleanup;
  788. if (c->use_runtime_pm) {
  789. pm_runtime_set_active(dev);
  790. pm_suspend_ignore_children(dev, 1);
  791. pm_runtime_set_autosuspend_delay(dev, 50);
  792. pm_runtime_use_autosuspend(dev);
  793. pm_runtime_enable(dev);
  794. }
  795. device_enable_async_suspend(dev);
  796. return 0;
  797. err_cleanup:
  798. sdhci_cleanup_host(c->host);
  799. err_free:
  800. if (c->slot && c->slot->free_slot)
  801. c->slot->free_slot(pdev);
  802. sdhci_free_host(c->host);
  803. return err;
  804. }
  805. static int sdhci_acpi_remove(struct platform_device *pdev)
  806. {
  807. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  808. struct device *dev = &pdev->dev;
  809. int dead;
  810. if (c->use_runtime_pm) {
  811. pm_runtime_get_sync(dev);
  812. pm_runtime_disable(dev);
  813. pm_runtime_put_noidle(dev);
  814. }
  815. if (c->slot && c->slot->remove_slot)
  816. c->slot->remove_slot(pdev);
  817. dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
  818. sdhci_remove_host(c->host, dead);
  819. if (c->slot && c->slot->free_slot)
  820. c->slot->free_slot(pdev);
  821. sdhci_free_host(c->host);
  822. return 0;
  823. }
  824. static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
  825. struct device *dev)
  826. {
  827. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  828. struct sdhci_host *host = c->host;
  829. if (c->is_intel && c->reset_signal_volt_on_suspend &&
  830. host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
  831. struct intel_host *intel_host = sdhci_acpi_priv(c);
  832. unsigned int fn = INTEL_DSM_V33_SWITCH;
  833. u32 result = 0;
  834. intel_dsm(intel_host, dev, fn, &result);
  835. }
  836. }
  837. #ifdef CONFIG_PM_SLEEP
  838. static int sdhci_acpi_suspend(struct device *dev)
  839. {
  840. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  841. struct sdhci_host *host = c->host;
  842. int ret;
  843. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  844. mmc_retune_needed(host->mmc);
  845. ret = sdhci_suspend_host(host);
  846. if (ret)
  847. return ret;
  848. sdhci_acpi_reset_signal_voltage_if_needed(dev);
  849. return 0;
  850. }
  851. static int sdhci_acpi_resume(struct device *dev)
  852. {
  853. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  854. sdhci_acpi_byt_setting(&c->pdev->dev);
  855. return sdhci_resume_host(c->host);
  856. }
  857. #endif
  858. #ifdef CONFIG_PM
  859. static int sdhci_acpi_runtime_suspend(struct device *dev)
  860. {
  861. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  862. struct sdhci_host *host = c->host;
  863. int ret;
  864. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  865. mmc_retune_needed(host->mmc);
  866. ret = sdhci_runtime_suspend_host(host);
  867. if (ret)
  868. return ret;
  869. sdhci_acpi_reset_signal_voltage_if_needed(dev);
  870. return 0;
  871. }
  872. static int sdhci_acpi_runtime_resume(struct device *dev)
  873. {
  874. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  875. sdhci_acpi_byt_setting(&c->pdev->dev);
  876. return sdhci_runtime_resume_host(c->host, 0);
  877. }
  878. #endif
  879. static const struct dev_pm_ops sdhci_acpi_pm_ops = {
  880. SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
  881. SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
  882. sdhci_acpi_runtime_resume, NULL)
  883. };
  884. static struct platform_driver sdhci_acpi_driver = {
  885. .driver = {
  886. .name = "sdhci-acpi",
  887. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  888. .acpi_match_table = sdhci_acpi_ids,
  889. .pm = &sdhci_acpi_pm_ops,
  890. },
  891. .probe = sdhci_acpi_probe,
  892. .remove = sdhci_acpi_remove,
  893. };
  894. module_platform_driver(sdhci_acpi_driver);
  895. MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
  896. MODULE_AUTHOR("Adrian Hunter");
  897. MODULE_LICENSE("GPL v2");