s3cmci.c 43 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
  4. *
  5. * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
  6. *
  7. * Current driver maintained by Ben Dooks and Simtec Electronics
  8. * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/clk.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/cpufreq.h>
  17. #include <linux/debugfs.h>
  18. #include <linux/seq_file.h>
  19. #include <linux/gpio.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/io.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/mmc/slot-gpio.h>
  26. #include <linux/platform_data/mmc-s3cmci.h>
  27. #include "s3cmci.h"
  28. #define DRIVER_NAME "s3c-mci"
  29. #define S3C2410_SDICON (0x00)
  30. #define S3C2410_SDIPRE (0x04)
  31. #define S3C2410_SDICMDARG (0x08)
  32. #define S3C2410_SDICMDCON (0x0C)
  33. #define S3C2410_SDICMDSTAT (0x10)
  34. #define S3C2410_SDIRSP0 (0x14)
  35. #define S3C2410_SDIRSP1 (0x18)
  36. #define S3C2410_SDIRSP2 (0x1C)
  37. #define S3C2410_SDIRSP3 (0x20)
  38. #define S3C2410_SDITIMER (0x24)
  39. #define S3C2410_SDIBSIZE (0x28)
  40. #define S3C2410_SDIDCON (0x2C)
  41. #define S3C2410_SDIDCNT (0x30)
  42. #define S3C2410_SDIDSTA (0x34)
  43. #define S3C2410_SDIFSTA (0x38)
  44. #define S3C2410_SDIDATA (0x3C)
  45. #define S3C2410_SDIIMSK (0x40)
  46. #define S3C2440_SDIDATA (0x40)
  47. #define S3C2440_SDIIMSK (0x3C)
  48. #define S3C2440_SDICON_SDRESET (1 << 8)
  49. #define S3C2410_SDICON_SDIOIRQ (1 << 3)
  50. #define S3C2410_SDICON_FIFORESET (1 << 1)
  51. #define S3C2410_SDICON_CLOCKTYPE (1 << 0)
  52. #define S3C2410_SDICMDCON_LONGRSP (1 << 10)
  53. #define S3C2410_SDICMDCON_WAITRSP (1 << 9)
  54. #define S3C2410_SDICMDCON_CMDSTART (1 << 8)
  55. #define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
  56. #define S3C2410_SDICMDCON_INDEX (0x3f)
  57. #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
  58. #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
  59. #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
  60. #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
  61. #define S3C2440_SDIDCON_DS_WORD (2 << 22)
  62. #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
  63. #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
  64. #define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
  65. #define S3C2410_SDIDCON_WIDEBUS (1 << 16)
  66. #define S3C2410_SDIDCON_DMAEN (1 << 15)
  67. #define S3C2410_SDIDCON_STOP (1 << 14)
  68. #define S3C2440_SDIDCON_DATSTART (1 << 14)
  69. #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
  70. #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
  71. #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
  72. #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
  73. #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
  74. #define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
  75. #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
  76. #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
  77. #define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
  78. #define S3C2410_SDIDSTA_TXDATAON (1 << 1)
  79. #define S3C2410_SDIDSTA_RXDATAON (1 << 0)
  80. #define S3C2440_SDIFSTA_FIFORESET (1 << 16)
  81. #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
  82. #define S3C2410_SDIFSTA_TFDET (1 << 13)
  83. #define S3C2410_SDIFSTA_RFDET (1 << 12)
  84. #define S3C2410_SDIFSTA_COUNTMASK (0x7f)
  85. #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
  86. #define S3C2410_SDIIMSK_CMDSENT (1 << 16)
  87. #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
  88. #define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
  89. #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
  90. #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
  91. #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
  92. #define S3C2410_SDIIMSK_DATACRC (1 << 9)
  93. #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
  94. #define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
  95. #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
  96. #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
  97. #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
  98. enum dbg_channels {
  99. dbg_err = (1 << 0),
  100. dbg_debug = (1 << 1),
  101. dbg_info = (1 << 2),
  102. dbg_irq = (1 << 3),
  103. dbg_sg = (1 << 4),
  104. dbg_dma = (1 << 5),
  105. dbg_pio = (1 << 6),
  106. dbg_fail = (1 << 7),
  107. dbg_conf = (1 << 8),
  108. };
  109. static const int dbgmap_err = dbg_fail;
  110. static const int dbgmap_info = dbg_info | dbg_conf;
  111. static const int dbgmap_debug = dbg_err | dbg_debug;
  112. #define dbg(host, channels, args...) \
  113. do { \
  114. if (dbgmap_err & channels) \
  115. dev_err(&host->pdev->dev, args); \
  116. else if (dbgmap_info & channels) \
  117. dev_info(&host->pdev->dev, args); \
  118. else if (dbgmap_debug & channels) \
  119. dev_dbg(&host->pdev->dev, args); \
  120. } while (0)
  121. static void finalize_request(struct s3cmci_host *host);
  122. static void s3cmci_send_request(struct mmc_host *mmc);
  123. static void s3cmci_reset(struct s3cmci_host *host);
  124. #ifdef CONFIG_MMC_DEBUG
  125. static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  126. {
  127. u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer;
  128. u32 datcon, datcnt, datsta, fsta;
  129. con = readl(host->base + S3C2410_SDICON);
  130. pre = readl(host->base + S3C2410_SDIPRE);
  131. cmdarg = readl(host->base + S3C2410_SDICMDARG);
  132. cmdcon = readl(host->base + S3C2410_SDICMDCON);
  133. cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
  134. r0 = readl(host->base + S3C2410_SDIRSP0);
  135. r1 = readl(host->base + S3C2410_SDIRSP1);
  136. r2 = readl(host->base + S3C2410_SDIRSP2);
  137. r3 = readl(host->base + S3C2410_SDIRSP3);
  138. timer = readl(host->base + S3C2410_SDITIMER);
  139. datcon = readl(host->base + S3C2410_SDIDCON);
  140. datcnt = readl(host->base + S3C2410_SDIDCNT);
  141. datsta = readl(host->base + S3C2410_SDIDSTA);
  142. fsta = readl(host->base + S3C2410_SDIFSTA);
  143. dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
  144. prefix, con, pre, timer);
  145. dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  146. prefix, cmdcon, cmdarg, cmdsta);
  147. dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
  148. " DSTA:[%08x] DCNT:[%08x]\n",
  149. prefix, datcon, fsta, datsta, datcnt);
  150. dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
  151. " R2:[%08x] R3:[%08x]\n",
  152. prefix, r0, r1, r2, r3);
  153. }
  154. static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
  155. int stop)
  156. {
  157. snprintf(host->dbgmsg_cmd, 300,
  158. "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
  159. host->ccnt, (stop ? " (STOP)" : ""),
  160. cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
  161. if (cmd->data) {
  162. snprintf(host->dbgmsg_dat, 300,
  163. "#%u bsize:%u blocks:%u bytes:%u",
  164. host->dcnt, cmd->data->blksz,
  165. cmd->data->blocks,
  166. cmd->data->blocks * cmd->data->blksz);
  167. } else {
  168. host->dbgmsg_dat[0] = '\0';
  169. }
  170. }
  171. static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
  172. int fail)
  173. {
  174. unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
  175. if (!cmd)
  176. return;
  177. if (cmd->error == 0) {
  178. dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
  179. host->dbgmsg_cmd, cmd->resp[0]);
  180. } else {
  181. dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
  182. cmd->error, host->dbgmsg_cmd, host->status);
  183. }
  184. if (!cmd->data)
  185. return;
  186. if (cmd->data->error == 0) {
  187. dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
  188. } else {
  189. dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
  190. cmd->data->error, host->dbgmsg_dat,
  191. readl(host->base + S3C2410_SDIDCNT));
  192. }
  193. }
  194. #else
  195. static void dbg_dumpcmd(struct s3cmci_host *host,
  196. struct mmc_command *cmd, int fail) { }
  197. static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
  198. int stop) { }
  199. static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
  200. #endif /* CONFIG_MMC_DEBUG */
  201. /**
  202. * s3cmci_host_usedma - return whether the host is using dma or pio
  203. * @host: The host state
  204. *
  205. * Return true if the host is using DMA to transfer data, else false
  206. * to use PIO mode. Will return static data depending on the driver
  207. * configuration.
  208. */
  209. static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
  210. {
  211. #ifdef CONFIG_MMC_S3C_PIO
  212. return false;
  213. #else /* CONFIG_MMC_S3C_DMA */
  214. return true;
  215. #endif
  216. }
  217. static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
  218. {
  219. u32 newmask;
  220. newmask = readl(host->base + host->sdiimsk);
  221. newmask |= imask;
  222. writel(newmask, host->base + host->sdiimsk);
  223. return newmask;
  224. }
  225. static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
  226. {
  227. u32 newmask;
  228. newmask = readl(host->base + host->sdiimsk);
  229. newmask &= ~imask;
  230. writel(newmask, host->base + host->sdiimsk);
  231. return newmask;
  232. }
  233. static inline void clear_imask(struct s3cmci_host *host)
  234. {
  235. u32 mask = readl(host->base + host->sdiimsk);
  236. /* preserve the SDIO IRQ mask state */
  237. mask &= S3C2410_SDIIMSK_SDIOIRQ;
  238. writel(mask, host->base + host->sdiimsk);
  239. }
  240. /**
  241. * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
  242. * @host: The host to check.
  243. *
  244. * Test to see if the SDIO interrupt is being signalled in case the
  245. * controller has failed to re-detect a card interrupt. Read GPE8 and
  246. * see if it is low and if so, signal a SDIO interrupt.
  247. *
  248. * This is currently called if a request is finished (we assume that the
  249. * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
  250. * already being indicated.
  251. */
  252. static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
  253. {
  254. if (host->sdio_irqen) {
  255. if (host->pdata->bus[3] &&
  256. gpiod_get_value(host->pdata->bus[3]) == 0) {
  257. pr_debug("%s: signalling irq\n", __func__);
  258. mmc_signal_sdio_irq(host->mmc);
  259. }
  260. }
  261. }
  262. static inline int get_data_buffer(struct s3cmci_host *host,
  263. u32 *bytes, u32 **pointer)
  264. {
  265. struct scatterlist *sg;
  266. if (host->pio_active == XFER_NONE)
  267. return -EINVAL;
  268. if ((!host->mrq) || (!host->mrq->data))
  269. return -EINVAL;
  270. if (host->pio_sgptr >= host->mrq->data->sg_len) {
  271. dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
  272. host->pio_sgptr, host->mrq->data->sg_len);
  273. return -EBUSY;
  274. }
  275. sg = &host->mrq->data->sg[host->pio_sgptr];
  276. *bytes = sg->length;
  277. *pointer = sg_virt(sg);
  278. host->pio_sgptr++;
  279. dbg(host, dbg_sg, "new buffer (%i/%i)\n",
  280. host->pio_sgptr, host->mrq->data->sg_len);
  281. return 0;
  282. }
  283. static inline u32 fifo_count(struct s3cmci_host *host)
  284. {
  285. u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
  286. fifostat &= S3C2410_SDIFSTA_COUNTMASK;
  287. return fifostat;
  288. }
  289. static inline u32 fifo_free(struct s3cmci_host *host)
  290. {
  291. u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
  292. fifostat &= S3C2410_SDIFSTA_COUNTMASK;
  293. return 63 - fifostat;
  294. }
  295. /**
  296. * s3cmci_enable_irq - enable IRQ, after having disabled it.
  297. * @host: The device state.
  298. * @more: True if more IRQs are expected from transfer.
  299. *
  300. * Enable the main IRQ if needed after it has been disabled.
  301. *
  302. * The IRQ can be one of the following states:
  303. * - disabled during IDLE
  304. * - disabled whilst processing data
  305. * - enabled during transfer
  306. * - enabled whilst awaiting SDIO interrupt detection
  307. */
  308. static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
  309. {
  310. unsigned long flags;
  311. bool enable = false;
  312. local_irq_save(flags);
  313. host->irq_enabled = more;
  314. host->irq_disabled = false;
  315. enable = more | host->sdio_irqen;
  316. if (host->irq_state != enable) {
  317. host->irq_state = enable;
  318. if (enable)
  319. enable_irq(host->irq);
  320. else
  321. disable_irq(host->irq);
  322. }
  323. local_irq_restore(flags);
  324. }
  325. static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
  326. {
  327. unsigned long flags;
  328. local_irq_save(flags);
  329. /* pr_debug("%s: transfer %d\n", __func__, transfer); */
  330. host->irq_disabled = transfer;
  331. if (transfer && host->irq_state) {
  332. host->irq_state = false;
  333. disable_irq(host->irq);
  334. }
  335. local_irq_restore(flags);
  336. }
  337. static void do_pio_read(struct s3cmci_host *host)
  338. {
  339. int res;
  340. u32 fifo;
  341. u32 *ptr;
  342. u32 fifo_words;
  343. void __iomem *from_ptr;
  344. /* write real prescaler to host, it might be set slow to fix */
  345. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  346. from_ptr = host->base + host->sdidata;
  347. while ((fifo = fifo_count(host))) {
  348. if (!host->pio_bytes) {
  349. res = get_data_buffer(host, &host->pio_bytes,
  350. &host->pio_ptr);
  351. if (res) {
  352. host->pio_active = XFER_NONE;
  353. host->complete_what = COMPLETION_FINALIZE;
  354. dbg(host, dbg_pio, "pio_read(): "
  355. "complete (no more data).\n");
  356. return;
  357. }
  358. dbg(host, dbg_pio,
  359. "pio_read(): new target: [%i]@[%p]\n",
  360. host->pio_bytes, host->pio_ptr);
  361. }
  362. dbg(host, dbg_pio,
  363. "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
  364. fifo, host->pio_bytes,
  365. readl(host->base + S3C2410_SDIDCNT));
  366. /* If we have reached the end of the block, we can
  367. * read a word and get 1 to 3 bytes. If we in the
  368. * middle of the block, we have to read full words,
  369. * otherwise we will write garbage, so round down to
  370. * an even multiple of 4. */
  371. if (fifo >= host->pio_bytes)
  372. fifo = host->pio_bytes;
  373. else
  374. fifo -= fifo & 3;
  375. host->pio_bytes -= fifo;
  376. host->pio_count += fifo;
  377. fifo_words = fifo >> 2;
  378. ptr = host->pio_ptr;
  379. while (fifo_words--)
  380. *ptr++ = readl(from_ptr);
  381. host->pio_ptr = ptr;
  382. if (fifo & 3) {
  383. u32 n = fifo & 3;
  384. u32 data = readl(from_ptr);
  385. u8 *p = (u8 *)host->pio_ptr;
  386. while (n--) {
  387. *p++ = data;
  388. data >>= 8;
  389. }
  390. }
  391. }
  392. if (!host->pio_bytes) {
  393. res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
  394. if (res) {
  395. dbg(host, dbg_pio,
  396. "pio_read(): complete (no more buffers).\n");
  397. host->pio_active = XFER_NONE;
  398. host->complete_what = COMPLETION_FINALIZE;
  399. return;
  400. }
  401. }
  402. enable_imask(host,
  403. S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
  404. }
  405. static void do_pio_write(struct s3cmci_host *host)
  406. {
  407. void __iomem *to_ptr;
  408. int res;
  409. u32 fifo;
  410. u32 *ptr;
  411. to_ptr = host->base + host->sdidata;
  412. while ((fifo = fifo_free(host)) > 3) {
  413. if (!host->pio_bytes) {
  414. res = get_data_buffer(host, &host->pio_bytes,
  415. &host->pio_ptr);
  416. if (res) {
  417. dbg(host, dbg_pio,
  418. "pio_write(): complete (no more data).\n");
  419. host->pio_active = XFER_NONE;
  420. return;
  421. }
  422. dbg(host, dbg_pio,
  423. "pio_write(): new source: [%i]@[%p]\n",
  424. host->pio_bytes, host->pio_ptr);
  425. }
  426. /* If we have reached the end of the block, we have to
  427. * write exactly the remaining number of bytes. If we
  428. * in the middle of the block, we have to write full
  429. * words, so round down to an even multiple of 4. */
  430. if (fifo >= host->pio_bytes)
  431. fifo = host->pio_bytes;
  432. else
  433. fifo -= fifo & 3;
  434. host->pio_bytes -= fifo;
  435. host->pio_count += fifo;
  436. fifo = (fifo + 3) >> 2;
  437. ptr = host->pio_ptr;
  438. while (fifo--)
  439. writel(*ptr++, to_ptr);
  440. host->pio_ptr = ptr;
  441. }
  442. enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  443. }
  444. static void pio_tasklet(unsigned long data)
  445. {
  446. struct s3cmci_host *host = (struct s3cmci_host *) data;
  447. s3cmci_disable_irq(host, true);
  448. if (host->pio_active == XFER_WRITE)
  449. do_pio_write(host);
  450. if (host->pio_active == XFER_READ)
  451. do_pio_read(host);
  452. if (host->complete_what == COMPLETION_FINALIZE) {
  453. clear_imask(host);
  454. if (host->pio_active != XFER_NONE) {
  455. dbg(host, dbg_err, "unfinished %s "
  456. "- pio_count:[%u] pio_bytes:[%u]\n",
  457. (host->pio_active == XFER_READ) ? "read" : "write",
  458. host->pio_count, host->pio_bytes);
  459. if (host->mrq->data)
  460. host->mrq->data->error = -EINVAL;
  461. }
  462. s3cmci_enable_irq(host, false);
  463. finalize_request(host);
  464. } else
  465. s3cmci_enable_irq(host, true);
  466. }
  467. /*
  468. * ISR for SDI Interface IRQ
  469. * Communication between driver and ISR works as follows:
  470. * host->mrq points to current request
  471. * host->complete_what Indicates when the request is considered done
  472. * COMPLETION_CMDSENT when the command was sent
  473. * COMPLETION_RSPFIN when a response was received
  474. * COMPLETION_XFERFINISH when the data transfer is finished
  475. * COMPLETION_XFERFINISH_RSPFIN both of the above.
  476. * host->complete_request is the completion-object the driver waits for
  477. *
  478. * 1) Driver sets up host->mrq and host->complete_what
  479. * 2) Driver prepares the transfer
  480. * 3) Driver enables interrupts
  481. * 4) Driver starts transfer
  482. * 5) Driver waits for host->complete_rquest
  483. * 6) ISR checks for request status (errors and success)
  484. * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
  485. * 7) ISR completes host->complete_request
  486. * 8) ISR disables interrupts
  487. * 9) Driver wakes up and takes care of the request
  488. *
  489. * Note: "->error"-fields are expected to be set to 0 before the request
  490. * was issued by mmc.c - therefore they are only set, when an error
  491. * contition comes up
  492. */
  493. static irqreturn_t s3cmci_irq(int irq, void *dev_id)
  494. {
  495. struct s3cmci_host *host = dev_id;
  496. struct mmc_command *cmd;
  497. u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
  498. u32 mci_cclear = 0, mci_dclear;
  499. unsigned long iflags;
  500. mci_dsta = readl(host->base + S3C2410_SDIDSTA);
  501. mci_imsk = readl(host->base + host->sdiimsk);
  502. if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
  503. if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
  504. mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
  505. writel(mci_dclear, host->base + S3C2410_SDIDSTA);
  506. mmc_signal_sdio_irq(host->mmc);
  507. return IRQ_HANDLED;
  508. }
  509. }
  510. spin_lock_irqsave(&host->complete_lock, iflags);
  511. mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
  512. mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
  513. mci_fsta = readl(host->base + S3C2410_SDIFSTA);
  514. mci_dclear = 0;
  515. if ((host->complete_what == COMPLETION_NONE) ||
  516. (host->complete_what == COMPLETION_FINALIZE)) {
  517. host->status = "nothing to complete";
  518. clear_imask(host);
  519. goto irq_out;
  520. }
  521. if (!host->mrq) {
  522. host->status = "no active mrq";
  523. clear_imask(host);
  524. goto irq_out;
  525. }
  526. cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
  527. if (!cmd) {
  528. host->status = "no active cmd";
  529. clear_imask(host);
  530. goto irq_out;
  531. }
  532. if (!s3cmci_host_usedma(host)) {
  533. if ((host->pio_active == XFER_WRITE) &&
  534. (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
  535. disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  536. tasklet_schedule(&host->pio_tasklet);
  537. host->status = "pio tx";
  538. }
  539. if ((host->pio_active == XFER_READ) &&
  540. (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
  541. disable_imask(host,
  542. S3C2410_SDIIMSK_RXFIFOHALF |
  543. S3C2410_SDIIMSK_RXFIFOLAST);
  544. tasklet_schedule(&host->pio_tasklet);
  545. host->status = "pio rx";
  546. }
  547. }
  548. if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
  549. dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
  550. cmd->error = -ETIMEDOUT;
  551. host->status = "error: command timeout";
  552. goto fail_transfer;
  553. }
  554. if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
  555. if (host->complete_what == COMPLETION_CMDSENT) {
  556. host->status = "ok: command sent";
  557. goto close_transfer;
  558. }
  559. mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
  560. }
  561. if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
  562. if (cmd->flags & MMC_RSP_CRC) {
  563. if (host->mrq->cmd->flags & MMC_RSP_136) {
  564. dbg(host, dbg_irq,
  565. "fixup: ignore CRC fail with long rsp\n");
  566. } else {
  567. /* note, we used to fail the transfer
  568. * here, but it seems that this is just
  569. * the hardware getting it wrong.
  570. *
  571. * cmd->error = -EILSEQ;
  572. * host->status = "error: bad command crc";
  573. * goto fail_transfer;
  574. */
  575. }
  576. }
  577. mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
  578. }
  579. if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
  580. if (host->complete_what == COMPLETION_RSPFIN) {
  581. host->status = "ok: command response received";
  582. goto close_transfer;
  583. }
  584. if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
  585. host->complete_what = COMPLETION_XFERFINISH;
  586. mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
  587. }
  588. /* errors handled after this point are only relevant
  589. when a data transfer is in progress */
  590. if (!cmd->data)
  591. goto clear_status_bits;
  592. /* Check for FIFO failure */
  593. if (host->is2440) {
  594. if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
  595. dbg(host, dbg_err, "FIFO failure\n");
  596. host->mrq->data->error = -EILSEQ;
  597. host->status = "error: 2440 fifo failure";
  598. goto fail_transfer;
  599. }
  600. } else {
  601. if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
  602. dbg(host, dbg_err, "FIFO failure\n");
  603. cmd->data->error = -EILSEQ;
  604. host->status = "error: fifo failure";
  605. goto fail_transfer;
  606. }
  607. }
  608. if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
  609. dbg(host, dbg_err, "bad data crc (outgoing)\n");
  610. cmd->data->error = -EILSEQ;
  611. host->status = "error: bad data crc (outgoing)";
  612. goto fail_transfer;
  613. }
  614. if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
  615. dbg(host, dbg_err, "bad data crc (incoming)\n");
  616. cmd->data->error = -EILSEQ;
  617. host->status = "error: bad data crc (incoming)";
  618. goto fail_transfer;
  619. }
  620. if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
  621. dbg(host, dbg_err, "data timeout\n");
  622. cmd->data->error = -ETIMEDOUT;
  623. host->status = "error: data timeout";
  624. goto fail_transfer;
  625. }
  626. if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
  627. if (host->complete_what == COMPLETION_XFERFINISH) {
  628. host->status = "ok: data transfer completed";
  629. goto close_transfer;
  630. }
  631. if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
  632. host->complete_what = COMPLETION_RSPFIN;
  633. mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
  634. }
  635. clear_status_bits:
  636. writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
  637. writel(mci_dclear, host->base + S3C2410_SDIDSTA);
  638. goto irq_out;
  639. fail_transfer:
  640. host->pio_active = XFER_NONE;
  641. close_transfer:
  642. host->complete_what = COMPLETION_FINALIZE;
  643. clear_imask(host);
  644. tasklet_schedule(&host->pio_tasklet);
  645. goto irq_out;
  646. irq_out:
  647. dbg(host, dbg_irq,
  648. "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
  649. mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
  650. spin_unlock_irqrestore(&host->complete_lock, iflags);
  651. return IRQ_HANDLED;
  652. }
  653. static void s3cmci_dma_done_callback(void *arg)
  654. {
  655. struct s3cmci_host *host = arg;
  656. unsigned long iflags;
  657. BUG_ON(!host->mrq);
  658. BUG_ON(!host->mrq->data);
  659. spin_lock_irqsave(&host->complete_lock, iflags);
  660. dbg(host, dbg_dma, "DMA FINISHED\n");
  661. host->dma_complete = 1;
  662. host->complete_what = COMPLETION_FINALIZE;
  663. tasklet_schedule(&host->pio_tasklet);
  664. spin_unlock_irqrestore(&host->complete_lock, iflags);
  665. }
  666. static void finalize_request(struct s3cmci_host *host)
  667. {
  668. struct mmc_request *mrq = host->mrq;
  669. struct mmc_command *cmd;
  670. int debug_as_failure = 0;
  671. if (host->complete_what != COMPLETION_FINALIZE)
  672. return;
  673. if (!mrq)
  674. return;
  675. cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
  676. if (cmd->data && (cmd->error == 0) &&
  677. (cmd->data->error == 0)) {
  678. if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
  679. dbg(host, dbg_dma, "DMA Missing (%d)!\n",
  680. host->dma_complete);
  681. return;
  682. }
  683. }
  684. /* Read response from controller. */
  685. cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
  686. cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
  687. cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
  688. cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
  689. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  690. if (cmd->error)
  691. debug_as_failure = 1;
  692. if (cmd->data && cmd->data->error)
  693. debug_as_failure = 1;
  694. dbg_dumpcmd(host, cmd, debug_as_failure);
  695. /* Cleanup controller */
  696. writel(0, host->base + S3C2410_SDICMDARG);
  697. writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
  698. writel(0, host->base + S3C2410_SDICMDCON);
  699. clear_imask(host);
  700. if (cmd->data && cmd->error)
  701. cmd->data->error = cmd->error;
  702. if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
  703. host->cmd_is_stop = 1;
  704. s3cmci_send_request(host->mmc);
  705. return;
  706. }
  707. /* If we have no data transfer we are finished here */
  708. if (!mrq->data)
  709. goto request_done;
  710. /* Calculate the amout of bytes transfer if there was no error */
  711. if (mrq->data->error == 0) {
  712. mrq->data->bytes_xfered =
  713. (mrq->data->blocks * mrq->data->blksz);
  714. } else {
  715. mrq->data->bytes_xfered = 0;
  716. }
  717. /* If we had an error while transferring data we flush the
  718. * DMA channel and the fifo to clear out any garbage. */
  719. if (mrq->data->error != 0) {
  720. if (s3cmci_host_usedma(host))
  721. dmaengine_terminate_all(host->dma);
  722. if (host->is2440) {
  723. /* Clear failure register and reset fifo. */
  724. writel(S3C2440_SDIFSTA_FIFORESET |
  725. S3C2440_SDIFSTA_FIFOFAIL,
  726. host->base + S3C2410_SDIFSTA);
  727. } else {
  728. u32 mci_con;
  729. /* reset fifo */
  730. mci_con = readl(host->base + S3C2410_SDICON);
  731. mci_con |= S3C2410_SDICON_FIFORESET;
  732. writel(mci_con, host->base + S3C2410_SDICON);
  733. }
  734. }
  735. request_done:
  736. host->complete_what = COMPLETION_NONE;
  737. host->mrq = NULL;
  738. s3cmci_check_sdio_irq(host);
  739. mmc_request_done(host->mmc, mrq);
  740. }
  741. static void s3cmci_send_command(struct s3cmci_host *host,
  742. struct mmc_command *cmd)
  743. {
  744. u32 ccon, imsk;
  745. imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
  746. S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
  747. S3C2410_SDIIMSK_RESPONSECRC;
  748. enable_imask(host, imsk);
  749. if (cmd->data)
  750. host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
  751. else if (cmd->flags & MMC_RSP_PRESENT)
  752. host->complete_what = COMPLETION_RSPFIN;
  753. else
  754. host->complete_what = COMPLETION_CMDSENT;
  755. writel(cmd->arg, host->base + S3C2410_SDICMDARG);
  756. ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
  757. ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
  758. if (cmd->flags & MMC_RSP_PRESENT)
  759. ccon |= S3C2410_SDICMDCON_WAITRSP;
  760. if (cmd->flags & MMC_RSP_136)
  761. ccon |= S3C2410_SDICMDCON_LONGRSP;
  762. writel(ccon, host->base + S3C2410_SDICMDCON);
  763. }
  764. static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
  765. {
  766. u32 dcon, imsk, stoptries = 3;
  767. if ((data->blksz & 3) != 0) {
  768. /* We cannot deal with unaligned blocks with more than
  769. * one block being transferred. */
  770. if (data->blocks > 1) {
  771. pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
  772. __func__, data->blksz);
  773. return -EINVAL;
  774. }
  775. }
  776. while (readl(host->base + S3C2410_SDIDSTA) &
  777. (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
  778. dbg(host, dbg_err,
  779. "mci_setup_data() transfer stillin progress.\n");
  780. writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
  781. s3cmci_reset(host);
  782. if ((stoptries--) == 0) {
  783. dbg_dumpregs(host, "DRF");
  784. return -EINVAL;
  785. }
  786. }
  787. dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
  788. if (s3cmci_host_usedma(host))
  789. dcon |= S3C2410_SDIDCON_DMAEN;
  790. if (host->bus_width == MMC_BUS_WIDTH_4)
  791. dcon |= S3C2410_SDIDCON_WIDEBUS;
  792. dcon |= S3C2410_SDIDCON_BLOCKMODE;
  793. if (data->flags & MMC_DATA_WRITE) {
  794. dcon |= S3C2410_SDIDCON_TXAFTERRESP;
  795. dcon |= S3C2410_SDIDCON_XFER_TXSTART;
  796. }
  797. if (data->flags & MMC_DATA_READ) {
  798. dcon |= S3C2410_SDIDCON_RXAFTERCMD;
  799. dcon |= S3C2410_SDIDCON_XFER_RXSTART;
  800. }
  801. if (host->is2440) {
  802. dcon |= S3C2440_SDIDCON_DS_WORD;
  803. dcon |= S3C2440_SDIDCON_DATSTART;
  804. }
  805. writel(dcon, host->base + S3C2410_SDIDCON);
  806. /* write BSIZE register */
  807. writel(data->blksz, host->base + S3C2410_SDIBSIZE);
  808. /* add to IMASK register */
  809. imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
  810. S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
  811. enable_imask(host, imsk);
  812. /* write TIMER register */
  813. if (host->is2440) {
  814. writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
  815. } else {
  816. writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
  817. /* FIX: set slow clock to prevent timeouts on read */
  818. if (data->flags & MMC_DATA_READ)
  819. writel(0xFF, host->base + S3C2410_SDIPRE);
  820. }
  821. return 0;
  822. }
  823. #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
  824. static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
  825. {
  826. int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
  827. BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
  828. host->pio_sgptr = 0;
  829. host->pio_bytes = 0;
  830. host->pio_count = 0;
  831. host->pio_active = rw ? XFER_WRITE : XFER_READ;
  832. if (rw) {
  833. do_pio_write(host);
  834. enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  835. } else {
  836. enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
  837. | S3C2410_SDIIMSK_RXFIFOLAST);
  838. }
  839. return 0;
  840. }
  841. static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
  842. {
  843. int rw = data->flags & MMC_DATA_WRITE;
  844. struct dma_async_tx_descriptor *desc;
  845. struct dma_slave_config conf = {
  846. .src_addr = host->mem->start + host->sdidata,
  847. .dst_addr = host->mem->start + host->sdidata,
  848. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  849. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  850. };
  851. BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
  852. /* Restore prescaler value */
  853. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  854. if (!rw)
  855. conf.direction = DMA_DEV_TO_MEM;
  856. else
  857. conf.direction = DMA_MEM_TO_DEV;
  858. dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  859. mmc_get_dma_dir(data));
  860. dmaengine_slave_config(host->dma, &conf);
  861. desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
  862. conf.direction,
  863. DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
  864. if (!desc)
  865. goto unmap_exit;
  866. desc->callback = s3cmci_dma_done_callback;
  867. desc->callback_param = host;
  868. dmaengine_submit(desc);
  869. dma_async_issue_pending(host->dma);
  870. return 0;
  871. unmap_exit:
  872. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  873. mmc_get_dma_dir(data));
  874. return -ENOMEM;
  875. }
  876. static void s3cmci_send_request(struct mmc_host *mmc)
  877. {
  878. struct s3cmci_host *host = mmc_priv(mmc);
  879. struct mmc_request *mrq = host->mrq;
  880. struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
  881. host->ccnt++;
  882. prepare_dbgmsg(host, cmd, host->cmd_is_stop);
  883. /* Clear command, data and fifo status registers
  884. Fifo clear only necessary on 2440, but doesn't hurt on 2410
  885. */
  886. writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
  887. writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
  888. writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
  889. if (cmd->data) {
  890. int res = s3cmci_setup_data(host, cmd->data);
  891. host->dcnt++;
  892. if (res) {
  893. dbg(host, dbg_err, "setup data error %d\n", res);
  894. cmd->error = res;
  895. cmd->data->error = res;
  896. mmc_request_done(mmc, mrq);
  897. return;
  898. }
  899. if (s3cmci_host_usedma(host))
  900. res = s3cmci_prepare_dma(host, cmd->data);
  901. else
  902. res = s3cmci_prepare_pio(host, cmd->data);
  903. if (res) {
  904. dbg(host, dbg_err, "data prepare error %d\n", res);
  905. cmd->error = res;
  906. cmd->data->error = res;
  907. mmc_request_done(mmc, mrq);
  908. return;
  909. }
  910. }
  911. /* Send command */
  912. s3cmci_send_command(host, cmd);
  913. /* Enable Interrupt */
  914. s3cmci_enable_irq(host, true);
  915. }
  916. static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  917. {
  918. struct s3cmci_host *host = mmc_priv(mmc);
  919. host->status = "mmc request";
  920. host->cmd_is_stop = 0;
  921. host->mrq = mrq;
  922. if (mmc_gpio_get_cd(mmc) == 0) {
  923. dbg(host, dbg_err, "%s: no medium present\n", __func__);
  924. host->mrq->cmd->error = -ENOMEDIUM;
  925. mmc_request_done(mmc, mrq);
  926. } else
  927. s3cmci_send_request(mmc);
  928. }
  929. static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
  930. {
  931. u32 mci_psc;
  932. /* Set clock */
  933. for (mci_psc = 0; mci_psc < 255; mci_psc++) {
  934. host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
  935. if (host->real_rate <= ios->clock)
  936. break;
  937. }
  938. if (mci_psc > 255)
  939. mci_psc = 255;
  940. host->prescaler = mci_psc;
  941. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  942. /* If requested clock is 0, real_rate will be 0, too */
  943. if (ios->clock == 0)
  944. host->real_rate = 0;
  945. }
  946. static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  947. {
  948. struct s3cmci_host *host = mmc_priv(mmc);
  949. u32 mci_con;
  950. /* Set the power state */
  951. mci_con = readl(host->base + S3C2410_SDICON);
  952. switch (ios->power_mode) {
  953. case MMC_POWER_ON:
  954. case MMC_POWER_UP:
  955. if (!host->is2440)
  956. mci_con |= S3C2410_SDICON_FIFORESET;
  957. break;
  958. case MMC_POWER_OFF:
  959. default:
  960. if (host->is2440)
  961. mci_con |= S3C2440_SDICON_SDRESET;
  962. break;
  963. }
  964. if (host->pdata->set_power)
  965. host->pdata->set_power(ios->power_mode, ios->vdd);
  966. s3cmci_set_clk(host, ios);
  967. /* Set CLOCK_ENABLE */
  968. if (ios->clock)
  969. mci_con |= S3C2410_SDICON_CLOCKTYPE;
  970. else
  971. mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
  972. writel(mci_con, host->base + S3C2410_SDICON);
  973. if ((ios->power_mode == MMC_POWER_ON) ||
  974. (ios->power_mode == MMC_POWER_UP)) {
  975. dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
  976. host->real_rate/1000, ios->clock/1000);
  977. } else {
  978. dbg(host, dbg_conf, "powered down.\n");
  979. }
  980. host->bus_width = ios->bus_width;
  981. }
  982. static void s3cmci_reset(struct s3cmci_host *host)
  983. {
  984. u32 con = readl(host->base + S3C2410_SDICON);
  985. con |= S3C2440_SDICON_SDRESET;
  986. writel(con, host->base + S3C2410_SDICON);
  987. }
  988. static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
  989. {
  990. struct s3cmci_host *host = mmc_priv(mmc);
  991. unsigned long flags;
  992. u32 con;
  993. local_irq_save(flags);
  994. con = readl(host->base + S3C2410_SDICON);
  995. host->sdio_irqen = enable;
  996. if (enable == host->sdio_irqen)
  997. goto same_state;
  998. if (enable) {
  999. con |= S3C2410_SDICON_SDIOIRQ;
  1000. enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
  1001. if (!host->irq_state && !host->irq_disabled) {
  1002. host->irq_state = true;
  1003. enable_irq(host->irq);
  1004. }
  1005. } else {
  1006. disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
  1007. con &= ~S3C2410_SDICON_SDIOIRQ;
  1008. if (!host->irq_enabled && host->irq_state) {
  1009. disable_irq_nosync(host->irq);
  1010. host->irq_state = false;
  1011. }
  1012. }
  1013. writel(con, host->base + S3C2410_SDICON);
  1014. same_state:
  1015. local_irq_restore(flags);
  1016. s3cmci_check_sdio_irq(host);
  1017. }
  1018. static const struct mmc_host_ops s3cmci_ops = {
  1019. .request = s3cmci_request,
  1020. .set_ios = s3cmci_set_ios,
  1021. .get_ro = mmc_gpio_get_ro,
  1022. .get_cd = mmc_gpio_get_cd,
  1023. .enable_sdio_irq = s3cmci_enable_sdio_irq,
  1024. };
  1025. #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
  1026. static int s3cmci_cpufreq_transition(struct notifier_block *nb,
  1027. unsigned long val, void *data)
  1028. {
  1029. struct s3cmci_host *host;
  1030. struct mmc_host *mmc;
  1031. unsigned long newclk;
  1032. unsigned long flags;
  1033. host = container_of(nb, struct s3cmci_host, freq_transition);
  1034. newclk = clk_get_rate(host->clk);
  1035. mmc = host->mmc;
  1036. if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
  1037. (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
  1038. spin_lock_irqsave(&mmc->lock, flags);
  1039. host->clk_rate = newclk;
  1040. if (mmc->ios.power_mode != MMC_POWER_OFF &&
  1041. mmc->ios.clock != 0)
  1042. s3cmci_set_clk(host, &mmc->ios);
  1043. spin_unlock_irqrestore(&mmc->lock, flags);
  1044. }
  1045. return 0;
  1046. }
  1047. static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
  1048. {
  1049. host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
  1050. return cpufreq_register_notifier(&host->freq_transition,
  1051. CPUFREQ_TRANSITION_NOTIFIER);
  1052. }
  1053. static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
  1054. {
  1055. cpufreq_unregister_notifier(&host->freq_transition,
  1056. CPUFREQ_TRANSITION_NOTIFIER);
  1057. }
  1058. #else
  1059. static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
  1060. {
  1061. return 0;
  1062. }
  1063. static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
  1064. {
  1065. }
  1066. #endif
  1067. #ifdef CONFIG_DEBUG_FS
  1068. static int s3cmci_state_show(struct seq_file *seq, void *v)
  1069. {
  1070. struct s3cmci_host *host = seq->private;
  1071. seq_printf(seq, "Register base = 0x%p\n", host->base);
  1072. seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
  1073. seq_printf(seq, "Prescale = %d\n", host->prescaler);
  1074. seq_printf(seq, "is2440 = %d\n", host->is2440);
  1075. seq_printf(seq, "IRQ = %d\n", host->irq);
  1076. seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
  1077. seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
  1078. seq_printf(seq, "IRQ state = %d\n", host->irq_state);
  1079. seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
  1080. seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
  1081. seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
  1082. seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
  1083. return 0;
  1084. }
  1085. DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
  1086. #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
  1087. struct s3cmci_reg {
  1088. unsigned short addr;
  1089. unsigned char *name;
  1090. };
  1091. static const struct s3cmci_reg debug_regs[] = {
  1092. DBG_REG(CON),
  1093. DBG_REG(PRE),
  1094. DBG_REG(CMDARG),
  1095. DBG_REG(CMDCON),
  1096. DBG_REG(CMDSTAT),
  1097. DBG_REG(RSP0),
  1098. DBG_REG(RSP1),
  1099. DBG_REG(RSP2),
  1100. DBG_REG(RSP3),
  1101. DBG_REG(TIMER),
  1102. DBG_REG(BSIZE),
  1103. DBG_REG(DCON),
  1104. DBG_REG(DCNT),
  1105. DBG_REG(DSTA),
  1106. DBG_REG(FSTA),
  1107. {}
  1108. };
  1109. static int s3cmci_regs_show(struct seq_file *seq, void *v)
  1110. {
  1111. struct s3cmci_host *host = seq->private;
  1112. const struct s3cmci_reg *rptr = debug_regs;
  1113. for (; rptr->name; rptr++)
  1114. seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
  1115. readl(host->base + rptr->addr));
  1116. seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
  1117. return 0;
  1118. }
  1119. DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
  1120. static void s3cmci_debugfs_attach(struct s3cmci_host *host)
  1121. {
  1122. struct device *dev = &host->pdev->dev;
  1123. struct dentry *root;
  1124. root = debugfs_create_dir(dev_name(dev), NULL);
  1125. host->debug_root = root;
  1126. debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
  1127. debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
  1128. }
  1129. static void s3cmci_debugfs_remove(struct s3cmci_host *host)
  1130. {
  1131. debugfs_remove_recursive(host->debug_root);
  1132. }
  1133. #else
  1134. static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
  1135. static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
  1136. #endif /* CONFIG_DEBUG_FS */
  1137. static int s3cmci_probe_pdata(struct s3cmci_host *host)
  1138. {
  1139. struct platform_device *pdev = host->pdev;
  1140. struct mmc_host *mmc = host->mmc;
  1141. struct s3c24xx_mci_pdata *pdata;
  1142. int i, ret;
  1143. host->is2440 = platform_get_device_id(pdev)->driver_data;
  1144. pdata = pdev->dev.platform_data;
  1145. if (!pdata) {
  1146. dev_err(&pdev->dev, "need platform data");
  1147. return -ENXIO;
  1148. }
  1149. for (i = 0; i < 6; i++) {
  1150. pdata->bus[i] = devm_gpiod_get_index(&pdev->dev, "bus", i,
  1151. GPIOD_OUT_LOW);
  1152. if (IS_ERR(pdata->bus[i])) {
  1153. dev_err(&pdev->dev, "failed to get gpio %d\n", i);
  1154. return PTR_ERR(pdata->bus[i]);
  1155. }
  1156. }
  1157. if (pdata->no_wprotect)
  1158. mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
  1159. if (pdata->no_detect)
  1160. mmc->caps |= MMC_CAP_NEEDS_POLL;
  1161. if (pdata->wprotect_invert)
  1162. mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
  1163. /* If we get -ENOENT we have no card detect GPIO line */
  1164. ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
  1165. if (ret != -ENOENT) {
  1166. dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
  1167. ret);
  1168. return ret;
  1169. }
  1170. ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
  1171. if (ret != -ENOENT) {
  1172. dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
  1173. ret);
  1174. return ret;
  1175. }
  1176. return 0;
  1177. }
  1178. static int s3cmci_probe_dt(struct s3cmci_host *host)
  1179. {
  1180. struct platform_device *pdev = host->pdev;
  1181. struct s3c24xx_mci_pdata *pdata;
  1182. struct mmc_host *mmc = host->mmc;
  1183. int ret;
  1184. host->is2440 = (long) of_device_get_match_data(&pdev->dev);
  1185. ret = mmc_of_parse(mmc);
  1186. if (ret)
  1187. return ret;
  1188. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  1189. if (!pdata)
  1190. return -ENOMEM;
  1191. pdev->dev.platform_data = pdata;
  1192. return 0;
  1193. }
  1194. static int s3cmci_probe(struct platform_device *pdev)
  1195. {
  1196. struct s3cmci_host *host;
  1197. struct mmc_host *mmc;
  1198. int ret;
  1199. mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
  1200. if (!mmc) {
  1201. ret = -ENOMEM;
  1202. goto probe_out;
  1203. }
  1204. host = mmc_priv(mmc);
  1205. host->mmc = mmc;
  1206. host->pdev = pdev;
  1207. if (pdev->dev.of_node)
  1208. ret = s3cmci_probe_dt(host);
  1209. else
  1210. ret = s3cmci_probe_pdata(host);
  1211. if (ret)
  1212. goto probe_free_host;
  1213. host->pdata = pdev->dev.platform_data;
  1214. spin_lock_init(&host->complete_lock);
  1215. tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
  1216. if (host->is2440) {
  1217. host->sdiimsk = S3C2440_SDIIMSK;
  1218. host->sdidata = S3C2440_SDIDATA;
  1219. host->clk_div = 1;
  1220. } else {
  1221. host->sdiimsk = S3C2410_SDIIMSK;
  1222. host->sdidata = S3C2410_SDIDATA;
  1223. host->clk_div = 2;
  1224. }
  1225. host->complete_what = COMPLETION_NONE;
  1226. host->pio_active = XFER_NONE;
  1227. host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1228. if (!host->mem) {
  1229. dev_err(&pdev->dev,
  1230. "failed to get io memory region resource.\n");
  1231. ret = -ENOENT;
  1232. goto probe_free_host;
  1233. }
  1234. host->mem = request_mem_region(host->mem->start,
  1235. resource_size(host->mem), pdev->name);
  1236. if (!host->mem) {
  1237. dev_err(&pdev->dev, "failed to request io memory region.\n");
  1238. ret = -ENOENT;
  1239. goto probe_free_host;
  1240. }
  1241. host->base = ioremap(host->mem->start, resource_size(host->mem));
  1242. if (!host->base) {
  1243. dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
  1244. ret = -EINVAL;
  1245. goto probe_free_mem_region;
  1246. }
  1247. host->irq = platform_get_irq(pdev, 0);
  1248. if (host->irq <= 0) {
  1249. ret = -EINVAL;
  1250. goto probe_iounmap;
  1251. }
  1252. if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
  1253. dev_err(&pdev->dev, "failed to request mci interrupt.\n");
  1254. ret = -ENOENT;
  1255. goto probe_iounmap;
  1256. }
  1257. /* We get spurious interrupts even when we have set the IMSK
  1258. * register to ignore everything, so use disable_irq() to make
  1259. * ensure we don't lock the system with un-serviceable requests. */
  1260. disable_irq(host->irq);
  1261. host->irq_state = false;
  1262. /* Depending on the dma state, get a DMA channel to use. */
  1263. if (s3cmci_host_usedma(host)) {
  1264. host->dma = dma_request_chan(&pdev->dev, "rx-tx");
  1265. ret = PTR_ERR_OR_ZERO(host->dma);
  1266. if (ret) {
  1267. dev_err(&pdev->dev, "cannot get DMA channel.\n");
  1268. goto probe_free_irq;
  1269. }
  1270. }
  1271. host->clk = clk_get(&pdev->dev, "sdi");
  1272. if (IS_ERR(host->clk)) {
  1273. dev_err(&pdev->dev, "failed to find clock source.\n");
  1274. ret = PTR_ERR(host->clk);
  1275. host->clk = NULL;
  1276. goto probe_free_dma;
  1277. }
  1278. ret = clk_prepare_enable(host->clk);
  1279. if (ret) {
  1280. dev_err(&pdev->dev, "failed to enable clock source.\n");
  1281. goto clk_free;
  1282. }
  1283. host->clk_rate = clk_get_rate(host->clk);
  1284. mmc->ops = &s3cmci_ops;
  1285. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  1286. #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
  1287. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  1288. #else
  1289. mmc->caps = MMC_CAP_4_BIT_DATA;
  1290. #endif
  1291. mmc->f_min = host->clk_rate / (host->clk_div * 256);
  1292. mmc->f_max = host->clk_rate / host->clk_div;
  1293. if (host->pdata->ocr_avail)
  1294. mmc->ocr_avail = host->pdata->ocr_avail;
  1295. mmc->max_blk_count = 4095;
  1296. mmc->max_blk_size = 4095;
  1297. mmc->max_req_size = 4095 * 512;
  1298. mmc->max_seg_size = mmc->max_req_size;
  1299. mmc->max_segs = 128;
  1300. dbg(host, dbg_debug,
  1301. "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
  1302. (host->is2440?"2440":""),
  1303. host->base, host->irq, host->irq_cd, host->dma);
  1304. ret = s3cmci_cpufreq_register(host);
  1305. if (ret) {
  1306. dev_err(&pdev->dev, "failed to register cpufreq\n");
  1307. goto free_dmabuf;
  1308. }
  1309. ret = mmc_add_host(mmc);
  1310. if (ret) {
  1311. dev_err(&pdev->dev, "failed to add mmc host.\n");
  1312. goto free_cpufreq;
  1313. }
  1314. s3cmci_debugfs_attach(host);
  1315. platform_set_drvdata(pdev, mmc);
  1316. dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
  1317. s3cmci_host_usedma(host) ? "dma" : "pio",
  1318. mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
  1319. return 0;
  1320. free_cpufreq:
  1321. s3cmci_cpufreq_deregister(host);
  1322. free_dmabuf:
  1323. clk_disable_unprepare(host->clk);
  1324. clk_free:
  1325. clk_put(host->clk);
  1326. probe_free_dma:
  1327. if (s3cmci_host_usedma(host))
  1328. dma_release_channel(host->dma);
  1329. probe_free_irq:
  1330. free_irq(host->irq, host);
  1331. probe_iounmap:
  1332. iounmap(host->base);
  1333. probe_free_mem_region:
  1334. release_mem_region(host->mem->start, resource_size(host->mem));
  1335. probe_free_host:
  1336. mmc_free_host(mmc);
  1337. probe_out:
  1338. return ret;
  1339. }
  1340. static void s3cmci_shutdown(struct platform_device *pdev)
  1341. {
  1342. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1343. struct s3cmci_host *host = mmc_priv(mmc);
  1344. if (host->irq_cd >= 0)
  1345. free_irq(host->irq_cd, host);
  1346. s3cmci_debugfs_remove(host);
  1347. s3cmci_cpufreq_deregister(host);
  1348. mmc_remove_host(mmc);
  1349. clk_disable_unprepare(host->clk);
  1350. }
  1351. static int s3cmci_remove(struct platform_device *pdev)
  1352. {
  1353. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1354. struct s3cmci_host *host = mmc_priv(mmc);
  1355. s3cmci_shutdown(pdev);
  1356. clk_put(host->clk);
  1357. tasklet_disable(&host->pio_tasklet);
  1358. if (s3cmci_host_usedma(host))
  1359. dma_release_channel(host->dma);
  1360. free_irq(host->irq, host);
  1361. iounmap(host->base);
  1362. release_mem_region(host->mem->start, resource_size(host->mem));
  1363. mmc_free_host(mmc);
  1364. return 0;
  1365. }
  1366. static const struct of_device_id s3cmci_dt_match[] = {
  1367. {
  1368. .compatible = "samsung,s3c2410-sdi",
  1369. .data = (void *)0,
  1370. },
  1371. {
  1372. .compatible = "samsung,s3c2412-sdi",
  1373. .data = (void *)1,
  1374. },
  1375. {
  1376. .compatible = "samsung,s3c2440-sdi",
  1377. .data = (void *)1,
  1378. },
  1379. { /* sentinel */ },
  1380. };
  1381. MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
  1382. static const struct platform_device_id s3cmci_driver_ids[] = {
  1383. {
  1384. .name = "s3c2410-sdi",
  1385. .driver_data = 0,
  1386. }, {
  1387. .name = "s3c2412-sdi",
  1388. .driver_data = 1,
  1389. }, {
  1390. .name = "s3c2440-sdi",
  1391. .driver_data = 1,
  1392. },
  1393. { }
  1394. };
  1395. MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
  1396. static struct platform_driver s3cmci_driver = {
  1397. .driver = {
  1398. .name = "s3c-sdi",
  1399. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1400. .of_match_table = s3cmci_dt_match,
  1401. },
  1402. .id_table = s3cmci_driver_ids,
  1403. .probe = s3cmci_probe,
  1404. .remove = s3cmci_remove,
  1405. .shutdown = s3cmci_shutdown,
  1406. };
  1407. module_platform_driver(s3cmci_driver);
  1408. MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
  1409. MODULE_LICENSE("GPL v2");
  1410. MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");