pxamci.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
  4. *
  5. * Copyright (C) 2003 Russell King, All Rights Reserved.
  6. *
  7. * This hardware is really sick:
  8. * - No way to clear interrupts.
  9. * - Have to turn off the clock whenever we touch the device.
  10. * - Doesn't tell you how many data blocks were transferred.
  11. * Yuck!
  12. *
  13. * 1 and 3 byte data transfers not supported
  14. * max block length up to 1023
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/ioport.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/delay.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/dmaengine.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/clk.h>
  25. #include <linux/err.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/mmc/slot-gpio.h>
  28. #include <linux/io.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <linux/gpio/consumer.h>
  31. #include <linux/gfp.h>
  32. #include <linux/of.h>
  33. #include <linux/of_device.h>
  34. #include <linux/sizes.h>
  35. #include <mach/hardware.h>
  36. #include <linux/platform_data/mmc-pxamci.h>
  37. #include "pxamci.h"
  38. #define DRIVER_NAME "pxa2xx-mci"
  39. #define NR_SG 1
  40. #define CLKRT_OFF (~0)
  41. #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
  42. || cpu_is_pxa935())
  43. struct pxamci_host {
  44. struct mmc_host *mmc;
  45. spinlock_t lock;
  46. struct resource *res;
  47. void __iomem *base;
  48. struct clk *clk;
  49. unsigned long clkrate;
  50. unsigned int clkrt;
  51. unsigned int cmdat;
  52. unsigned int imask;
  53. unsigned int power_mode;
  54. unsigned long detect_delay_ms;
  55. bool use_ro_gpio;
  56. struct gpio_desc *power;
  57. struct pxamci_platform_data *pdata;
  58. struct mmc_request *mrq;
  59. struct mmc_command *cmd;
  60. struct mmc_data *data;
  61. struct dma_chan *dma_chan_rx;
  62. struct dma_chan *dma_chan_tx;
  63. dma_cookie_t dma_cookie;
  64. unsigned int dma_len;
  65. unsigned int dma_dir;
  66. };
  67. static int pxamci_init_ocr(struct pxamci_host *host)
  68. {
  69. struct mmc_host *mmc = host->mmc;
  70. int ret;
  71. ret = mmc_regulator_get_supply(mmc);
  72. if (ret < 0)
  73. return ret;
  74. if (IS_ERR(mmc->supply.vmmc)) {
  75. /* fall-back to platform data */
  76. mmc->ocr_avail = host->pdata ?
  77. host->pdata->ocr_mask :
  78. MMC_VDD_32_33 | MMC_VDD_33_34;
  79. }
  80. return 0;
  81. }
  82. static inline int pxamci_set_power(struct pxamci_host *host,
  83. unsigned char power_mode,
  84. unsigned int vdd)
  85. {
  86. struct mmc_host *mmc = host->mmc;
  87. struct regulator *supply = mmc->supply.vmmc;
  88. if (!IS_ERR(supply))
  89. return mmc_regulator_set_ocr(mmc, supply, vdd);
  90. if (host->power) {
  91. bool on = !!((1 << vdd) & host->pdata->ocr_mask);
  92. gpiod_set_value(host->power, on);
  93. }
  94. if (host->pdata && host->pdata->setpower)
  95. return host->pdata->setpower(mmc_dev(host->mmc), vdd);
  96. return 0;
  97. }
  98. static void pxamci_stop_clock(struct pxamci_host *host)
  99. {
  100. if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
  101. unsigned long timeout = 10000;
  102. unsigned int v;
  103. writel(STOP_CLOCK, host->base + MMC_STRPCL);
  104. do {
  105. v = readl(host->base + MMC_STAT);
  106. if (!(v & STAT_CLK_EN))
  107. break;
  108. udelay(1);
  109. } while (timeout--);
  110. if (v & STAT_CLK_EN)
  111. dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
  112. }
  113. }
  114. static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
  115. {
  116. unsigned long flags;
  117. spin_lock_irqsave(&host->lock, flags);
  118. host->imask &= ~mask;
  119. writel(host->imask, host->base + MMC_I_MASK);
  120. spin_unlock_irqrestore(&host->lock, flags);
  121. }
  122. static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
  123. {
  124. unsigned long flags;
  125. spin_lock_irqsave(&host->lock, flags);
  126. host->imask |= mask;
  127. writel(host->imask, host->base + MMC_I_MASK);
  128. spin_unlock_irqrestore(&host->lock, flags);
  129. }
  130. static void pxamci_dma_irq(void *param);
  131. static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
  132. {
  133. struct dma_async_tx_descriptor *tx;
  134. enum dma_transfer_direction direction;
  135. struct dma_slave_config config;
  136. struct dma_chan *chan;
  137. unsigned int nob = data->blocks;
  138. unsigned long long clks;
  139. unsigned int timeout;
  140. int ret;
  141. host->data = data;
  142. writel(nob, host->base + MMC_NOB);
  143. writel(data->blksz, host->base + MMC_BLKLEN);
  144. clks = (unsigned long long)data->timeout_ns * host->clkrate;
  145. do_div(clks, 1000000000UL);
  146. timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
  147. writel((timeout + 255) / 256, host->base + MMC_RDTO);
  148. memset(&config, 0, sizeof(config));
  149. config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  150. config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  151. config.src_addr = host->res->start + MMC_RXFIFO;
  152. config.dst_addr = host->res->start + MMC_TXFIFO;
  153. config.src_maxburst = 32;
  154. config.dst_maxburst = 32;
  155. if (data->flags & MMC_DATA_READ) {
  156. host->dma_dir = DMA_FROM_DEVICE;
  157. direction = DMA_DEV_TO_MEM;
  158. chan = host->dma_chan_rx;
  159. } else {
  160. host->dma_dir = DMA_TO_DEVICE;
  161. direction = DMA_MEM_TO_DEV;
  162. chan = host->dma_chan_tx;
  163. }
  164. config.direction = direction;
  165. ret = dmaengine_slave_config(chan, &config);
  166. if (ret < 0) {
  167. dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
  168. return;
  169. }
  170. host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
  171. host->dma_dir);
  172. tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
  173. DMA_PREP_INTERRUPT);
  174. if (!tx) {
  175. dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
  176. return;
  177. }
  178. if (!(data->flags & MMC_DATA_READ)) {
  179. tx->callback = pxamci_dma_irq;
  180. tx->callback_param = host;
  181. }
  182. host->dma_cookie = dmaengine_submit(tx);
  183. /*
  184. * workaround for erratum #91:
  185. * only start DMA now if we are doing a read,
  186. * otherwise we wait until CMD/RESP has finished
  187. * before starting DMA.
  188. */
  189. if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
  190. dma_async_issue_pending(chan);
  191. }
  192. static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
  193. {
  194. WARN_ON(host->cmd != NULL);
  195. host->cmd = cmd;
  196. if (cmd->flags & MMC_RSP_BUSY)
  197. cmdat |= CMDAT_BUSY;
  198. #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
  199. switch (RSP_TYPE(mmc_resp_type(cmd))) {
  200. case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
  201. cmdat |= CMDAT_RESP_SHORT;
  202. break;
  203. case RSP_TYPE(MMC_RSP_R3):
  204. cmdat |= CMDAT_RESP_R3;
  205. break;
  206. case RSP_TYPE(MMC_RSP_R2):
  207. cmdat |= CMDAT_RESP_R2;
  208. break;
  209. default:
  210. break;
  211. }
  212. writel(cmd->opcode, host->base + MMC_CMD);
  213. writel(cmd->arg >> 16, host->base + MMC_ARGH);
  214. writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
  215. writel(cmdat, host->base + MMC_CMDAT);
  216. writel(host->clkrt, host->base + MMC_CLKRT);
  217. writel(START_CLOCK, host->base + MMC_STRPCL);
  218. pxamci_enable_irq(host, END_CMD_RES);
  219. }
  220. static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
  221. {
  222. host->mrq = NULL;
  223. host->cmd = NULL;
  224. host->data = NULL;
  225. mmc_request_done(host->mmc, mrq);
  226. }
  227. static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
  228. {
  229. struct mmc_command *cmd = host->cmd;
  230. int i;
  231. u32 v;
  232. if (!cmd)
  233. return 0;
  234. host->cmd = NULL;
  235. /*
  236. * Did I mention this is Sick. We always need to
  237. * discard the upper 8 bits of the first 16-bit word.
  238. */
  239. v = readl(host->base + MMC_RES) & 0xffff;
  240. for (i = 0; i < 4; i++) {
  241. u32 w1 = readl(host->base + MMC_RES) & 0xffff;
  242. u32 w2 = readl(host->base + MMC_RES) & 0xffff;
  243. cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
  244. v = w2;
  245. }
  246. if (stat & STAT_TIME_OUT_RESPONSE) {
  247. cmd->error = -ETIMEDOUT;
  248. } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
  249. /*
  250. * workaround for erratum #42:
  251. * Intel PXA27x Family Processor Specification Update Rev 001
  252. * A bogus CRC error can appear if the msb of a 136 bit
  253. * response is a one.
  254. */
  255. if (cpu_is_pxa27x() &&
  256. (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
  257. pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
  258. else
  259. cmd->error = -EILSEQ;
  260. }
  261. pxamci_disable_irq(host, END_CMD_RES);
  262. if (host->data && !cmd->error) {
  263. pxamci_enable_irq(host, DATA_TRAN_DONE);
  264. /*
  265. * workaround for erratum #91, if doing write
  266. * enable DMA late
  267. */
  268. if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
  269. dma_async_issue_pending(host->dma_chan_tx);
  270. } else {
  271. pxamci_finish_request(host, host->mrq);
  272. }
  273. return 1;
  274. }
  275. static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
  276. {
  277. struct mmc_data *data = host->data;
  278. struct dma_chan *chan;
  279. if (!data)
  280. return 0;
  281. if (data->flags & MMC_DATA_READ)
  282. chan = host->dma_chan_rx;
  283. else
  284. chan = host->dma_chan_tx;
  285. dma_unmap_sg(chan->device->dev,
  286. data->sg, data->sg_len, host->dma_dir);
  287. if (stat & STAT_READ_TIME_OUT)
  288. data->error = -ETIMEDOUT;
  289. else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
  290. data->error = -EILSEQ;
  291. /*
  292. * There appears to be a hardware design bug here. There seems to
  293. * be no way to find out how much data was transferred to the card.
  294. * This means that if there was an error on any block, we mark all
  295. * data blocks as being in error.
  296. */
  297. if (!data->error)
  298. data->bytes_xfered = data->blocks * data->blksz;
  299. else
  300. data->bytes_xfered = 0;
  301. pxamci_disable_irq(host, DATA_TRAN_DONE);
  302. host->data = NULL;
  303. if (host->mrq->stop) {
  304. pxamci_stop_clock(host);
  305. pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
  306. } else {
  307. pxamci_finish_request(host, host->mrq);
  308. }
  309. return 1;
  310. }
  311. static irqreturn_t pxamci_irq(int irq, void *devid)
  312. {
  313. struct pxamci_host *host = devid;
  314. unsigned int ireg;
  315. int handled = 0;
  316. ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
  317. if (ireg) {
  318. unsigned stat = readl(host->base + MMC_STAT);
  319. pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
  320. if (ireg & END_CMD_RES)
  321. handled |= pxamci_cmd_done(host, stat);
  322. if (ireg & DATA_TRAN_DONE)
  323. handled |= pxamci_data_done(host, stat);
  324. if (ireg & SDIO_INT) {
  325. mmc_signal_sdio_irq(host->mmc);
  326. handled = 1;
  327. }
  328. }
  329. return IRQ_RETVAL(handled);
  330. }
  331. static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  332. {
  333. struct pxamci_host *host = mmc_priv(mmc);
  334. unsigned int cmdat;
  335. WARN_ON(host->mrq != NULL);
  336. host->mrq = mrq;
  337. pxamci_stop_clock(host);
  338. cmdat = host->cmdat;
  339. host->cmdat &= ~CMDAT_INIT;
  340. if (mrq->data) {
  341. pxamci_setup_data(host, mrq->data);
  342. cmdat &= ~CMDAT_BUSY;
  343. cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
  344. if (mrq->data->flags & MMC_DATA_WRITE)
  345. cmdat |= CMDAT_WRITE;
  346. }
  347. pxamci_start_cmd(host, mrq->cmd, cmdat);
  348. }
  349. static int pxamci_get_ro(struct mmc_host *mmc)
  350. {
  351. struct pxamci_host *host = mmc_priv(mmc);
  352. if (host->use_ro_gpio)
  353. return mmc_gpio_get_ro(mmc);
  354. if (host->pdata && host->pdata->get_ro)
  355. return !!host->pdata->get_ro(mmc_dev(mmc));
  356. /*
  357. * Board doesn't support read only detection; let the mmc core
  358. * decide what to do.
  359. */
  360. return -ENOSYS;
  361. }
  362. static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  363. {
  364. struct pxamci_host *host = mmc_priv(mmc);
  365. if (ios->clock) {
  366. unsigned long rate = host->clkrate;
  367. unsigned int clk = rate / ios->clock;
  368. if (host->clkrt == CLKRT_OFF)
  369. clk_prepare_enable(host->clk);
  370. if (ios->clock == 26000000) {
  371. /* to support 26MHz */
  372. host->clkrt = 7;
  373. } else {
  374. /* to handle (19.5MHz, 26MHz) */
  375. if (!clk)
  376. clk = 1;
  377. /*
  378. * clk might result in a lower divisor than we
  379. * desire. check for that condition and adjust
  380. * as appropriate.
  381. */
  382. if (rate / clk > ios->clock)
  383. clk <<= 1;
  384. host->clkrt = fls(clk) - 1;
  385. }
  386. /*
  387. * we write clkrt on the next command
  388. */
  389. } else {
  390. pxamci_stop_clock(host);
  391. if (host->clkrt != CLKRT_OFF) {
  392. host->clkrt = CLKRT_OFF;
  393. clk_disable_unprepare(host->clk);
  394. }
  395. }
  396. if (host->power_mode != ios->power_mode) {
  397. int ret;
  398. host->power_mode = ios->power_mode;
  399. ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
  400. if (ret) {
  401. dev_err(mmc_dev(mmc), "unable to set power\n");
  402. /*
  403. * The .set_ios() function in the mmc_host_ops
  404. * struct return void, and failing to set the
  405. * power should be rare so we print an error and
  406. * return here.
  407. */
  408. return;
  409. }
  410. if (ios->power_mode == MMC_POWER_ON)
  411. host->cmdat |= CMDAT_INIT;
  412. }
  413. if (ios->bus_width == MMC_BUS_WIDTH_4)
  414. host->cmdat |= CMDAT_SD_4DAT;
  415. else
  416. host->cmdat &= ~CMDAT_SD_4DAT;
  417. dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
  418. host->clkrt, host->cmdat);
  419. }
  420. static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
  421. {
  422. struct pxamci_host *pxa_host = mmc_priv(host);
  423. if (enable)
  424. pxamci_enable_irq(pxa_host, SDIO_INT);
  425. else
  426. pxamci_disable_irq(pxa_host, SDIO_INT);
  427. }
  428. static const struct mmc_host_ops pxamci_ops = {
  429. .request = pxamci_request,
  430. .get_cd = mmc_gpio_get_cd,
  431. .get_ro = pxamci_get_ro,
  432. .set_ios = pxamci_set_ios,
  433. .enable_sdio_irq = pxamci_enable_sdio_irq,
  434. };
  435. static void pxamci_dma_irq(void *param)
  436. {
  437. struct pxamci_host *host = param;
  438. struct dma_tx_state state;
  439. enum dma_status status;
  440. struct dma_chan *chan;
  441. unsigned long flags;
  442. spin_lock_irqsave(&host->lock, flags);
  443. if (!host->data)
  444. goto out_unlock;
  445. if (host->data->flags & MMC_DATA_READ)
  446. chan = host->dma_chan_rx;
  447. else
  448. chan = host->dma_chan_tx;
  449. status = dmaengine_tx_status(chan, host->dma_cookie, &state);
  450. if (likely(status == DMA_COMPLETE)) {
  451. writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
  452. } else {
  453. pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
  454. host->data->flags & MMC_DATA_READ ? "rx" : "tx");
  455. host->data->error = -EIO;
  456. pxamci_data_done(host, 0);
  457. }
  458. out_unlock:
  459. spin_unlock_irqrestore(&host->lock, flags);
  460. }
  461. static irqreturn_t pxamci_detect_irq(int irq, void *devid)
  462. {
  463. struct pxamci_host *host = mmc_priv(devid);
  464. mmc_detect_change(devid, msecs_to_jiffies(host->detect_delay_ms));
  465. return IRQ_HANDLED;
  466. }
  467. #ifdef CONFIG_OF
  468. static const struct of_device_id pxa_mmc_dt_ids[] = {
  469. { .compatible = "marvell,pxa-mmc" },
  470. { }
  471. };
  472. MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
  473. static int pxamci_of_init(struct platform_device *pdev,
  474. struct mmc_host *mmc)
  475. {
  476. struct device_node *np = pdev->dev.of_node;
  477. struct pxamci_host *host = mmc_priv(mmc);
  478. u32 tmp;
  479. int ret;
  480. if (!np)
  481. return 0;
  482. /* pxa-mmc specific */
  483. if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
  484. host->detect_delay_ms = tmp;
  485. ret = mmc_of_parse(mmc);
  486. if (ret < 0)
  487. return ret;
  488. return 0;
  489. }
  490. #else
  491. static int pxamci_of_init(struct platform_device *pdev,
  492. struct mmc_host *mmc)
  493. {
  494. return 0;
  495. }
  496. #endif
  497. static int pxamci_probe(struct platform_device *pdev)
  498. {
  499. struct mmc_host *mmc;
  500. struct pxamci_host *host = NULL;
  501. struct device *dev = &pdev->dev;
  502. struct resource *r;
  503. int ret, irq;
  504. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  505. irq = platform_get_irq(pdev, 0);
  506. if (irq < 0)
  507. return irq;
  508. mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
  509. if (!mmc) {
  510. ret = -ENOMEM;
  511. goto out;
  512. }
  513. mmc->ops = &pxamci_ops;
  514. /*
  515. * We can do SG-DMA, but we don't because we never know how much
  516. * data we successfully wrote to the card.
  517. */
  518. mmc->max_segs = NR_SG;
  519. /*
  520. * Our hardware DMA can handle a maximum of one page per SG entry.
  521. */
  522. mmc->max_seg_size = PAGE_SIZE;
  523. /*
  524. * Block length register is only 10 bits before PXA27x.
  525. */
  526. mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
  527. /*
  528. * Block count register is 16 bits.
  529. */
  530. mmc->max_blk_count = 65535;
  531. ret = pxamci_of_init(pdev, mmc);
  532. if (ret)
  533. return ret;
  534. host = mmc_priv(mmc);
  535. host->mmc = mmc;
  536. host->pdata = pdev->dev.platform_data;
  537. host->clkrt = CLKRT_OFF;
  538. host->clk = devm_clk_get(dev, NULL);
  539. if (IS_ERR(host->clk)) {
  540. ret = PTR_ERR(host->clk);
  541. host->clk = NULL;
  542. goto out;
  543. }
  544. host->clkrate = clk_get_rate(host->clk);
  545. /*
  546. * Calculate minimum clock rate, rounding up.
  547. */
  548. mmc->f_min = (host->clkrate + 63) / 64;
  549. mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
  550. ret = pxamci_init_ocr(host);
  551. if (ret < 0)
  552. return ret;
  553. mmc->caps = 0;
  554. host->cmdat = 0;
  555. if (!cpu_is_pxa25x()) {
  556. mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  557. host->cmdat |= CMDAT_SDIO_INT_EN;
  558. if (mmc_has_26MHz())
  559. mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
  560. MMC_CAP_SD_HIGHSPEED;
  561. }
  562. spin_lock_init(&host->lock);
  563. host->res = r;
  564. host->imask = MMC_I_MASK_ALL;
  565. host->base = devm_ioremap_resource(dev, r);
  566. if (IS_ERR(host->base)) {
  567. ret = PTR_ERR(host->base);
  568. goto out;
  569. }
  570. /*
  571. * Ensure that the host controller is shut down, and setup
  572. * with our defaults.
  573. */
  574. pxamci_stop_clock(host);
  575. writel(0, host->base + MMC_SPI);
  576. writel(64, host->base + MMC_RESTO);
  577. writel(host->imask, host->base + MMC_I_MASK);
  578. ret = devm_request_irq(dev, irq, pxamci_irq, 0,
  579. DRIVER_NAME, host);
  580. if (ret)
  581. goto out;
  582. platform_set_drvdata(pdev, mmc);
  583. host->dma_chan_rx = dma_request_chan(dev, "rx");
  584. if (IS_ERR(host->dma_chan_rx)) {
  585. dev_err(dev, "unable to request rx dma channel\n");
  586. ret = PTR_ERR(host->dma_chan_rx);
  587. host->dma_chan_rx = NULL;
  588. goto out;
  589. }
  590. host->dma_chan_tx = dma_request_chan(dev, "tx");
  591. if (IS_ERR(host->dma_chan_tx)) {
  592. dev_err(dev, "unable to request tx dma channel\n");
  593. ret = PTR_ERR(host->dma_chan_tx);
  594. host->dma_chan_tx = NULL;
  595. goto out;
  596. }
  597. if (host->pdata) {
  598. host->detect_delay_ms = host->pdata->detect_delay_ms;
  599. host->power = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
  600. if (IS_ERR(host->power)) {
  601. ret = PTR_ERR(host->power);
  602. dev_err(dev, "Failed requesting gpio_power\n");
  603. goto out;
  604. }
  605. /* FIXME: should we pass detection delay to debounce? */
  606. ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
  607. if (ret && ret != -ENOENT) {
  608. dev_err(dev, "Failed requesting gpio_cd\n");
  609. goto out;
  610. }
  611. if (!host->pdata->gpio_card_ro_invert)
  612. mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
  613. ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
  614. if (ret && ret != -ENOENT) {
  615. dev_err(dev, "Failed requesting gpio_ro\n");
  616. goto out;
  617. }
  618. if (!ret)
  619. host->use_ro_gpio = true;
  620. if (host->pdata->init)
  621. host->pdata->init(dev, pxamci_detect_irq, mmc);
  622. if (host->power && host->pdata->setpower)
  623. dev_warn(dev, "gpio_power and setpower() both defined\n");
  624. if (host->use_ro_gpio && host->pdata->get_ro)
  625. dev_warn(dev, "gpio_ro and get_ro() both defined\n");
  626. }
  627. mmc_add_host(mmc);
  628. return 0;
  629. out:
  630. if (host) {
  631. if (host->dma_chan_rx)
  632. dma_release_channel(host->dma_chan_rx);
  633. if (host->dma_chan_tx)
  634. dma_release_channel(host->dma_chan_tx);
  635. }
  636. if (mmc)
  637. mmc_free_host(mmc);
  638. return ret;
  639. }
  640. static int pxamci_remove(struct platform_device *pdev)
  641. {
  642. struct mmc_host *mmc = platform_get_drvdata(pdev);
  643. if (mmc) {
  644. struct pxamci_host *host = mmc_priv(mmc);
  645. mmc_remove_host(mmc);
  646. if (host->pdata && host->pdata->exit)
  647. host->pdata->exit(&pdev->dev, mmc);
  648. pxamci_stop_clock(host);
  649. writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
  650. END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
  651. host->base + MMC_I_MASK);
  652. dmaengine_terminate_all(host->dma_chan_rx);
  653. dmaengine_terminate_all(host->dma_chan_tx);
  654. dma_release_channel(host->dma_chan_rx);
  655. dma_release_channel(host->dma_chan_tx);
  656. mmc_free_host(mmc);
  657. }
  658. return 0;
  659. }
  660. static struct platform_driver pxamci_driver = {
  661. .probe = pxamci_probe,
  662. .remove = pxamci_remove,
  663. .driver = {
  664. .name = DRIVER_NAME,
  665. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  666. .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
  667. },
  668. };
  669. module_platform_driver(pxamci_driver);
  670. MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
  671. MODULE_LICENSE("GPL");
  672. MODULE_ALIAS("platform:pxa2xx-mci");