omap_hsmmc.c 54 KB

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  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sizes.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/timer.h>
  29. #include <linux/clk.h>
  30. #include <linux/of.h>
  31. #include <linux/of_irq.h>
  32. #include <linux/of_device.h>
  33. #include <linux/mmc/host.h>
  34. #include <linux/mmc/core.h>
  35. #include <linux/mmc/mmc.h>
  36. #include <linux/mmc/slot-gpio.h>
  37. #include <linux/io.h>
  38. #include <linux/irq.h>
  39. #include <linux/regulator/consumer.h>
  40. #include <linux/pinctrl/consumer.h>
  41. #include <linux/pm_runtime.h>
  42. #include <linux/pm_wakeirq.h>
  43. #include <linux/platform_data/hsmmc-omap.h>
  44. /* OMAP HSMMC Host Controller Registers */
  45. #define OMAP_HSMMC_SYSSTATUS 0x0014
  46. #define OMAP_HSMMC_CON 0x002C
  47. #define OMAP_HSMMC_SDMASA 0x0100
  48. #define OMAP_HSMMC_BLK 0x0104
  49. #define OMAP_HSMMC_ARG 0x0108
  50. #define OMAP_HSMMC_CMD 0x010C
  51. #define OMAP_HSMMC_RSP10 0x0110
  52. #define OMAP_HSMMC_RSP32 0x0114
  53. #define OMAP_HSMMC_RSP54 0x0118
  54. #define OMAP_HSMMC_RSP76 0x011C
  55. #define OMAP_HSMMC_DATA 0x0120
  56. #define OMAP_HSMMC_PSTATE 0x0124
  57. #define OMAP_HSMMC_HCTL 0x0128
  58. #define OMAP_HSMMC_SYSCTL 0x012C
  59. #define OMAP_HSMMC_STAT 0x0130
  60. #define OMAP_HSMMC_IE 0x0134
  61. #define OMAP_HSMMC_ISE 0x0138
  62. #define OMAP_HSMMC_AC12 0x013C
  63. #define OMAP_HSMMC_CAPA 0x0140
  64. #define VS18 (1 << 26)
  65. #define VS30 (1 << 25)
  66. #define HSS (1 << 21)
  67. #define SDVS18 (0x5 << 9)
  68. #define SDVS30 (0x6 << 9)
  69. #define SDVS33 (0x7 << 9)
  70. #define SDVS_MASK 0x00000E00
  71. #define SDVSCLR 0xFFFFF1FF
  72. #define SDVSDET 0x00000400
  73. #define AUTOIDLE 0x1
  74. #define SDBP (1 << 8)
  75. #define DTO 0xe
  76. #define ICE 0x1
  77. #define ICS 0x2
  78. #define CEN (1 << 2)
  79. #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
  80. #define CLKD_MASK 0x0000FFC0
  81. #define CLKD_SHIFT 6
  82. #define DTO_MASK 0x000F0000
  83. #define DTO_SHIFT 16
  84. #define INIT_STREAM (1 << 1)
  85. #define ACEN_ACMD23 (2 << 2)
  86. #define DP_SELECT (1 << 21)
  87. #define DDIR (1 << 4)
  88. #define DMAE 0x1
  89. #define MSBS (1 << 5)
  90. #define BCE (1 << 1)
  91. #define FOUR_BIT (1 << 1)
  92. #define HSPE (1 << 2)
  93. #define IWE (1 << 24)
  94. #define DDR (1 << 19)
  95. #define CLKEXTFREE (1 << 16)
  96. #define CTPL (1 << 11)
  97. #define DW8 (1 << 5)
  98. #define OD 0x1
  99. #define STAT_CLEAR 0xFFFFFFFF
  100. #define INIT_STREAM_CMD 0x00000000
  101. #define DUAL_VOLT_OCR_BIT 7
  102. #define SRC (1 << 25)
  103. #define SRD (1 << 26)
  104. #define SOFTRESET (1 << 1)
  105. /* PSTATE */
  106. #define DLEV_DAT(x) (1 << (20 + (x)))
  107. /* Interrupt masks for IE and ISE register */
  108. #define CC_EN (1 << 0)
  109. #define TC_EN (1 << 1)
  110. #define BWR_EN (1 << 4)
  111. #define BRR_EN (1 << 5)
  112. #define CIRQ_EN (1 << 8)
  113. #define ERR_EN (1 << 15)
  114. #define CTO_EN (1 << 16)
  115. #define CCRC_EN (1 << 17)
  116. #define CEB_EN (1 << 18)
  117. #define CIE_EN (1 << 19)
  118. #define DTO_EN (1 << 20)
  119. #define DCRC_EN (1 << 21)
  120. #define DEB_EN (1 << 22)
  121. #define ACE_EN (1 << 24)
  122. #define CERR_EN (1 << 28)
  123. #define BADA_EN (1 << 29)
  124. #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
  125. DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
  126. BRR_EN | BWR_EN | TC_EN | CC_EN)
  127. #define CNI (1 << 7)
  128. #define ACIE (1 << 4)
  129. #define ACEB (1 << 3)
  130. #define ACCE (1 << 2)
  131. #define ACTO (1 << 1)
  132. #define ACNE (1 << 0)
  133. #define MMC_AUTOSUSPEND_DELAY 100
  134. #define MMC_TIMEOUT_MS 20 /* 20 mSec */
  135. #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
  136. #define OMAP_MMC_MIN_CLOCK 400000
  137. #define OMAP_MMC_MAX_CLOCK 52000000
  138. #define DRIVER_NAME "omap_hsmmc"
  139. /*
  140. * One controller can have multiple slots, like on some omap boards using
  141. * omap.c controller driver. Luckily this is not currently done on any known
  142. * omap_hsmmc.c device.
  143. */
  144. #define mmc_pdata(host) host->pdata
  145. /*
  146. * MMC Host controller read/write API's
  147. */
  148. #define OMAP_HSMMC_READ(base, reg) \
  149. __raw_readl((base) + OMAP_HSMMC_##reg)
  150. #define OMAP_HSMMC_WRITE(base, reg, val) \
  151. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  152. struct omap_hsmmc_next {
  153. unsigned int dma_len;
  154. s32 cookie;
  155. };
  156. struct omap_hsmmc_host {
  157. struct device *dev;
  158. struct mmc_host *mmc;
  159. struct mmc_request *mrq;
  160. struct mmc_command *cmd;
  161. struct mmc_data *data;
  162. struct clk *fclk;
  163. struct clk *dbclk;
  164. struct regulator *pbias;
  165. bool pbias_enabled;
  166. void __iomem *base;
  167. int vqmmc_enabled;
  168. resource_size_t mapbase;
  169. spinlock_t irq_lock; /* Prevent races with irq handler */
  170. unsigned int dma_len;
  171. unsigned int dma_sg_idx;
  172. unsigned char bus_mode;
  173. unsigned char power_mode;
  174. int suspended;
  175. u32 con;
  176. u32 hctl;
  177. u32 sysctl;
  178. u32 capa;
  179. int irq;
  180. int wake_irq;
  181. int use_dma, dma_ch;
  182. struct dma_chan *tx_chan;
  183. struct dma_chan *rx_chan;
  184. int response_busy;
  185. int context_loss;
  186. int reqs_blocked;
  187. int req_in_progress;
  188. unsigned long clk_rate;
  189. unsigned int flags;
  190. #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
  191. #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
  192. struct omap_hsmmc_next next_data;
  193. struct omap_hsmmc_platform_data *pdata;
  194. };
  195. struct omap_mmc_of_data {
  196. u32 reg_offset;
  197. u8 controller_flags;
  198. };
  199. static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
  200. static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
  201. {
  202. int ret;
  203. struct omap_hsmmc_host *host = mmc_priv(mmc);
  204. struct mmc_ios *ios = &mmc->ios;
  205. if (!IS_ERR(mmc->supply.vmmc)) {
  206. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
  207. if (ret)
  208. return ret;
  209. }
  210. /* Enable interface voltage rail, if needed */
  211. if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
  212. ret = regulator_enable(mmc->supply.vqmmc);
  213. if (ret) {
  214. dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
  215. goto err_vqmmc;
  216. }
  217. host->vqmmc_enabled = 1;
  218. }
  219. return 0;
  220. err_vqmmc:
  221. if (!IS_ERR(mmc->supply.vmmc))
  222. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  223. return ret;
  224. }
  225. static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
  226. {
  227. int ret;
  228. int status;
  229. struct omap_hsmmc_host *host = mmc_priv(mmc);
  230. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
  231. ret = regulator_disable(mmc->supply.vqmmc);
  232. if (ret) {
  233. dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
  234. return ret;
  235. }
  236. host->vqmmc_enabled = 0;
  237. }
  238. if (!IS_ERR(mmc->supply.vmmc)) {
  239. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  240. if (ret)
  241. goto err_set_ocr;
  242. }
  243. return 0;
  244. err_set_ocr:
  245. if (!IS_ERR(mmc->supply.vqmmc)) {
  246. status = regulator_enable(mmc->supply.vqmmc);
  247. if (status)
  248. dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
  249. }
  250. return ret;
  251. }
  252. static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
  253. {
  254. int ret;
  255. if (IS_ERR(host->pbias))
  256. return 0;
  257. if (power_on) {
  258. if (host->pbias_enabled == 0) {
  259. ret = regulator_enable(host->pbias);
  260. if (ret) {
  261. dev_err(host->dev, "pbias reg enable fail\n");
  262. return ret;
  263. }
  264. host->pbias_enabled = 1;
  265. }
  266. } else {
  267. if (host->pbias_enabled == 1) {
  268. ret = regulator_disable(host->pbias);
  269. if (ret) {
  270. dev_err(host->dev, "pbias reg disable fail\n");
  271. return ret;
  272. }
  273. host->pbias_enabled = 0;
  274. }
  275. }
  276. return 0;
  277. }
  278. static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
  279. {
  280. struct mmc_host *mmc = host->mmc;
  281. int ret = 0;
  282. /*
  283. * If we don't see a Vcc regulator, assume it's a fixed
  284. * voltage always-on regulator.
  285. */
  286. if (IS_ERR(mmc->supply.vmmc))
  287. return 0;
  288. ret = omap_hsmmc_set_pbias(host, false);
  289. if (ret)
  290. return ret;
  291. /*
  292. * Assume Vcc regulator is used only to power the card ... OMAP
  293. * VDDS is used to power the pins, optionally with a transceiver to
  294. * support cards using voltages other than VDDS (1.8V nominal). When a
  295. * transceiver is used, DAT3..7 are muxed as transceiver control pins.
  296. *
  297. * In some cases this regulator won't support enable/disable;
  298. * e.g. it's a fixed rail for a WLAN chip.
  299. *
  300. * In other cases vcc_aux switches interface power. Example, for
  301. * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
  302. * chips/cards need an interface voltage rail too.
  303. */
  304. if (power_on) {
  305. ret = omap_hsmmc_enable_supply(mmc);
  306. if (ret)
  307. return ret;
  308. ret = omap_hsmmc_set_pbias(host, true);
  309. if (ret)
  310. goto err_set_voltage;
  311. } else {
  312. ret = omap_hsmmc_disable_supply(mmc);
  313. if (ret)
  314. return ret;
  315. }
  316. return 0;
  317. err_set_voltage:
  318. omap_hsmmc_disable_supply(mmc);
  319. return ret;
  320. }
  321. static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
  322. {
  323. int ret;
  324. if (IS_ERR(reg))
  325. return 0;
  326. if (regulator_is_enabled(reg)) {
  327. ret = regulator_enable(reg);
  328. if (ret)
  329. return ret;
  330. ret = regulator_disable(reg);
  331. if (ret)
  332. return ret;
  333. }
  334. return 0;
  335. }
  336. static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
  337. {
  338. struct mmc_host *mmc = host->mmc;
  339. int ret;
  340. /*
  341. * disable regulators enabled during boot and get the usecount
  342. * right so that regulators can be enabled/disabled by checking
  343. * the return value of regulator_is_enabled
  344. */
  345. ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
  346. if (ret) {
  347. dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
  348. return ret;
  349. }
  350. ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
  351. if (ret) {
  352. dev_err(host->dev,
  353. "fail to disable boot enabled vmmc_aux reg\n");
  354. return ret;
  355. }
  356. ret = omap_hsmmc_disable_boot_regulator(host->pbias);
  357. if (ret) {
  358. dev_err(host->dev,
  359. "failed to disable boot enabled pbias reg\n");
  360. return ret;
  361. }
  362. return 0;
  363. }
  364. static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  365. {
  366. int ret;
  367. struct mmc_host *mmc = host->mmc;
  368. ret = mmc_regulator_get_supply(mmc);
  369. if (ret)
  370. return ret;
  371. /* Allow an aux regulator */
  372. if (IS_ERR(mmc->supply.vqmmc)) {
  373. mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
  374. "vmmc_aux");
  375. if (IS_ERR(mmc->supply.vqmmc)) {
  376. ret = PTR_ERR(mmc->supply.vqmmc);
  377. if ((ret != -ENODEV) && host->dev->of_node)
  378. return ret;
  379. dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
  380. PTR_ERR(mmc->supply.vqmmc));
  381. }
  382. }
  383. host->pbias = devm_regulator_get_optional(host->dev, "pbias");
  384. if (IS_ERR(host->pbias)) {
  385. ret = PTR_ERR(host->pbias);
  386. if ((ret != -ENODEV) && host->dev->of_node) {
  387. dev_err(host->dev,
  388. "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
  389. return ret;
  390. }
  391. dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
  392. PTR_ERR(host->pbias));
  393. }
  394. /* For eMMC do not power off when not in sleep state */
  395. if (mmc_pdata(host)->no_regulator_off_init)
  396. return 0;
  397. ret = omap_hsmmc_disable_boot_regulators(host);
  398. if (ret)
  399. return ret;
  400. return 0;
  401. }
  402. /*
  403. * Start clock to the card
  404. */
  405. static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  406. {
  407. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  408. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  409. }
  410. /*
  411. * Stop clock to the card
  412. */
  413. static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
  414. {
  415. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  416. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  417. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  418. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
  419. }
  420. static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
  421. struct mmc_command *cmd)
  422. {
  423. u32 irq_mask = INT_EN_MASK;
  424. unsigned long flags;
  425. if (host->use_dma)
  426. irq_mask &= ~(BRR_EN | BWR_EN);
  427. /* Disable timeout for erases */
  428. if (cmd->opcode == MMC_ERASE)
  429. irq_mask &= ~DTO_EN;
  430. spin_lock_irqsave(&host->irq_lock, flags);
  431. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  432. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  433. /* latch pending CIRQ, but don't signal MMC core */
  434. if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
  435. irq_mask |= CIRQ_EN;
  436. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  437. spin_unlock_irqrestore(&host->irq_lock, flags);
  438. }
  439. static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
  440. {
  441. u32 irq_mask = 0;
  442. unsigned long flags;
  443. spin_lock_irqsave(&host->irq_lock, flags);
  444. /* no transfer running but need to keep cirq if enabled */
  445. if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
  446. irq_mask |= CIRQ_EN;
  447. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  448. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  449. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  450. spin_unlock_irqrestore(&host->irq_lock, flags);
  451. }
  452. /* Calculate divisor for the given clock frequency */
  453. static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
  454. {
  455. u16 dsor = 0;
  456. if (ios->clock) {
  457. dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
  458. if (dsor > CLKD_MAX)
  459. dsor = CLKD_MAX;
  460. }
  461. return dsor;
  462. }
  463. static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
  464. {
  465. struct mmc_ios *ios = &host->mmc->ios;
  466. unsigned long regval;
  467. unsigned long timeout;
  468. unsigned long clkdiv;
  469. dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
  470. omap_hsmmc_stop_clock(host);
  471. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  472. regval = regval & ~(CLKD_MASK | DTO_MASK);
  473. clkdiv = calc_divisor(host, ios);
  474. regval = regval | (clkdiv << 6) | (DTO << 16);
  475. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  476. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  477. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  478. /* Wait till the ICS bit is set */
  479. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  480. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  481. && time_before(jiffies, timeout))
  482. cpu_relax();
  483. /*
  484. * Enable High-Speed Support
  485. * Pre-Requisites
  486. * - Controller should support High-Speed-Enable Bit
  487. * - Controller should not be using DDR Mode
  488. * - Controller should advertise that it supports High Speed
  489. * in capabilities register
  490. * - MMC/SD clock coming out of controller > 25MHz
  491. */
  492. if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
  493. (ios->timing != MMC_TIMING_MMC_DDR52) &&
  494. (ios->timing != MMC_TIMING_UHS_DDR50) &&
  495. ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
  496. regval = OMAP_HSMMC_READ(host->base, HCTL);
  497. if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
  498. regval |= HSPE;
  499. else
  500. regval &= ~HSPE;
  501. OMAP_HSMMC_WRITE(host->base, HCTL, regval);
  502. }
  503. omap_hsmmc_start_clock(host);
  504. }
  505. static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
  506. {
  507. struct mmc_ios *ios = &host->mmc->ios;
  508. u32 con;
  509. con = OMAP_HSMMC_READ(host->base, CON);
  510. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  511. ios->timing == MMC_TIMING_UHS_DDR50)
  512. con |= DDR; /* configure in DDR mode */
  513. else
  514. con &= ~DDR;
  515. switch (ios->bus_width) {
  516. case MMC_BUS_WIDTH_8:
  517. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  518. break;
  519. case MMC_BUS_WIDTH_4:
  520. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  521. OMAP_HSMMC_WRITE(host->base, HCTL,
  522. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  523. break;
  524. case MMC_BUS_WIDTH_1:
  525. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  526. OMAP_HSMMC_WRITE(host->base, HCTL,
  527. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  528. break;
  529. }
  530. }
  531. static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
  532. {
  533. struct mmc_ios *ios = &host->mmc->ios;
  534. u32 con;
  535. con = OMAP_HSMMC_READ(host->base, CON);
  536. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  537. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  538. else
  539. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  540. }
  541. #ifdef CONFIG_PM
  542. /*
  543. * Restore the MMC host context, if it was lost as result of a
  544. * power state change.
  545. */
  546. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  547. {
  548. struct mmc_ios *ios = &host->mmc->ios;
  549. u32 hctl, capa;
  550. unsigned long timeout;
  551. if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
  552. host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
  553. host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
  554. host->capa == OMAP_HSMMC_READ(host->base, CAPA))
  555. return 0;
  556. host->context_loss++;
  557. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  558. if (host->power_mode != MMC_POWER_OFF &&
  559. (1 << ios->vdd) <= MMC_VDD_23_24)
  560. hctl = SDVS18;
  561. else
  562. hctl = SDVS30;
  563. capa = VS30 | VS18;
  564. } else {
  565. hctl = SDVS18;
  566. capa = VS18;
  567. }
  568. if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
  569. hctl |= IWE;
  570. OMAP_HSMMC_WRITE(host->base, HCTL,
  571. OMAP_HSMMC_READ(host->base, HCTL) | hctl);
  572. OMAP_HSMMC_WRITE(host->base, CAPA,
  573. OMAP_HSMMC_READ(host->base, CAPA) | capa);
  574. OMAP_HSMMC_WRITE(host->base, HCTL,
  575. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  576. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  577. while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
  578. && time_before(jiffies, timeout))
  579. ;
  580. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  581. OMAP_HSMMC_WRITE(host->base, IE, 0);
  582. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  583. /* Do not initialize card-specific things if the power is off */
  584. if (host->power_mode == MMC_POWER_OFF)
  585. goto out;
  586. omap_hsmmc_set_bus_width(host);
  587. omap_hsmmc_set_clock(host);
  588. omap_hsmmc_set_bus_mode(host);
  589. out:
  590. dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
  591. host->context_loss);
  592. return 0;
  593. }
  594. /*
  595. * Save the MMC host context (store the number of power state changes so far).
  596. */
  597. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  598. {
  599. host->con = OMAP_HSMMC_READ(host->base, CON);
  600. host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
  601. host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
  602. host->capa = OMAP_HSMMC_READ(host->base, CAPA);
  603. }
  604. #else
  605. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  606. {
  607. return 0;
  608. }
  609. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  610. {
  611. }
  612. #endif
  613. /*
  614. * Send init stream sequence to card
  615. * before sending IDLE command
  616. */
  617. static void send_init_stream(struct omap_hsmmc_host *host)
  618. {
  619. int reg = 0;
  620. unsigned long timeout;
  621. disable_irq(host->irq);
  622. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  623. OMAP_HSMMC_WRITE(host->base, CON,
  624. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  625. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  626. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  627. while ((reg != CC_EN) && time_before(jiffies, timeout))
  628. reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
  629. OMAP_HSMMC_WRITE(host->base, CON,
  630. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  631. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  632. OMAP_HSMMC_READ(host->base, STAT);
  633. enable_irq(host->irq);
  634. }
  635. static ssize_t
  636. omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
  637. char *buf)
  638. {
  639. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  640. struct omap_hsmmc_host *host = mmc_priv(mmc);
  641. return sprintf(buf, "%s\n", mmc_pdata(host)->name);
  642. }
  643. static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
  644. /*
  645. * Configure the response type and send the cmd.
  646. */
  647. static void
  648. omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
  649. struct mmc_data *data)
  650. {
  651. int cmdreg = 0, resptype = 0, cmdtype = 0;
  652. dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  653. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  654. host->cmd = cmd;
  655. omap_hsmmc_enable_irq(host, cmd);
  656. host->response_busy = 0;
  657. if (cmd->flags & MMC_RSP_PRESENT) {
  658. if (cmd->flags & MMC_RSP_136)
  659. resptype = 1;
  660. else if (cmd->flags & MMC_RSP_BUSY) {
  661. resptype = 3;
  662. host->response_busy = 1;
  663. } else
  664. resptype = 2;
  665. }
  666. /*
  667. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  668. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  669. * a val of 0x3, rest 0x0.
  670. */
  671. if (cmd == host->mrq->stop)
  672. cmdtype = 0x3;
  673. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  674. if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
  675. host->mrq->sbc) {
  676. cmdreg |= ACEN_ACMD23;
  677. OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
  678. }
  679. if (data) {
  680. cmdreg |= DP_SELECT | MSBS | BCE;
  681. if (data->flags & MMC_DATA_READ)
  682. cmdreg |= DDIR;
  683. else
  684. cmdreg &= ~(DDIR);
  685. }
  686. if (host->use_dma)
  687. cmdreg |= DMAE;
  688. host->req_in_progress = 1;
  689. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  690. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  691. }
  692. static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
  693. struct mmc_data *data)
  694. {
  695. return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
  696. }
  697. static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
  698. {
  699. int dma_ch;
  700. unsigned long flags;
  701. spin_lock_irqsave(&host->irq_lock, flags);
  702. host->req_in_progress = 0;
  703. dma_ch = host->dma_ch;
  704. spin_unlock_irqrestore(&host->irq_lock, flags);
  705. omap_hsmmc_disable_irq(host);
  706. /* Do not complete the request if DMA is still in progress */
  707. if (mrq->data && host->use_dma && dma_ch != -1)
  708. return;
  709. host->mrq = NULL;
  710. mmc_request_done(host->mmc, mrq);
  711. }
  712. /*
  713. * Notify the transfer complete to MMC core
  714. */
  715. static void
  716. omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
  717. {
  718. if (!data) {
  719. struct mmc_request *mrq = host->mrq;
  720. /* TC before CC from CMD6 - don't know why, but it happens */
  721. if (host->cmd && host->cmd->opcode == 6 &&
  722. host->response_busy) {
  723. host->response_busy = 0;
  724. return;
  725. }
  726. omap_hsmmc_request_done(host, mrq);
  727. return;
  728. }
  729. host->data = NULL;
  730. if (!data->error)
  731. data->bytes_xfered += data->blocks * (data->blksz);
  732. else
  733. data->bytes_xfered = 0;
  734. if (data->stop && (data->error || !host->mrq->sbc))
  735. omap_hsmmc_start_command(host, data->stop, NULL);
  736. else
  737. omap_hsmmc_request_done(host, data->mrq);
  738. }
  739. /*
  740. * Notify the core about command completion
  741. */
  742. static void
  743. omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
  744. {
  745. if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
  746. !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
  747. host->cmd = NULL;
  748. omap_hsmmc_start_dma_transfer(host);
  749. omap_hsmmc_start_command(host, host->mrq->cmd,
  750. host->mrq->data);
  751. return;
  752. }
  753. host->cmd = NULL;
  754. if (cmd->flags & MMC_RSP_PRESENT) {
  755. if (cmd->flags & MMC_RSP_136) {
  756. /* response type 2 */
  757. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  758. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  759. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  760. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  761. } else {
  762. /* response types 1, 1b, 3, 4, 5, 6 */
  763. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  764. }
  765. }
  766. if ((host->data == NULL && !host->response_busy) || cmd->error)
  767. omap_hsmmc_request_done(host, host->mrq);
  768. }
  769. /*
  770. * DMA clean up for command errors
  771. */
  772. static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
  773. {
  774. int dma_ch;
  775. unsigned long flags;
  776. host->data->error = errno;
  777. spin_lock_irqsave(&host->irq_lock, flags);
  778. dma_ch = host->dma_ch;
  779. host->dma_ch = -1;
  780. spin_unlock_irqrestore(&host->irq_lock, flags);
  781. if (host->use_dma && dma_ch != -1) {
  782. struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
  783. dmaengine_terminate_all(chan);
  784. dma_unmap_sg(chan->device->dev,
  785. host->data->sg, host->data->sg_len,
  786. mmc_get_dma_dir(host->data));
  787. host->data->host_cookie = 0;
  788. }
  789. host->data = NULL;
  790. }
  791. /*
  792. * Readable error output
  793. */
  794. #ifdef CONFIG_MMC_DEBUG
  795. static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
  796. {
  797. /* --- means reserved bit without definition at documentation */
  798. static const char *omap_hsmmc_status_bits[] = {
  799. "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
  800. "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
  801. "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
  802. "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
  803. };
  804. char res[256];
  805. char *buf = res;
  806. int len, i;
  807. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  808. buf += len;
  809. for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
  810. if (status & (1 << i)) {
  811. len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
  812. buf += len;
  813. }
  814. dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
  815. }
  816. #else
  817. static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
  818. u32 status)
  819. {
  820. }
  821. #endif /* CONFIG_MMC_DEBUG */
  822. /*
  823. * MMC controller internal state machines reset
  824. *
  825. * Used to reset command or data internal state machines, using respectively
  826. * SRC or SRD bit of SYSCTL register
  827. * Can be called from interrupt context
  828. */
  829. static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
  830. unsigned long bit)
  831. {
  832. unsigned long i = 0;
  833. unsigned long limit = MMC_TIMEOUT_US;
  834. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  835. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  836. /*
  837. * OMAP4 ES2 and greater has an updated reset logic.
  838. * Monitor a 0->1 transition first
  839. */
  840. if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
  841. while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
  842. && (i++ < limit))
  843. udelay(1);
  844. }
  845. i = 0;
  846. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  847. (i++ < limit))
  848. udelay(1);
  849. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  850. dev_err(mmc_dev(host->mmc),
  851. "Timeout waiting on controller reset in %s\n",
  852. __func__);
  853. }
  854. static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
  855. int err, int end_cmd)
  856. {
  857. if (end_cmd) {
  858. omap_hsmmc_reset_controller_fsm(host, SRC);
  859. if (host->cmd)
  860. host->cmd->error = err;
  861. }
  862. if (host->data) {
  863. omap_hsmmc_reset_controller_fsm(host, SRD);
  864. omap_hsmmc_dma_cleanup(host, err);
  865. } else if (host->mrq && host->mrq->cmd)
  866. host->mrq->cmd->error = err;
  867. }
  868. static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
  869. {
  870. struct mmc_data *data;
  871. int end_cmd = 0, end_trans = 0;
  872. int error = 0;
  873. data = host->data;
  874. dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  875. if (status & ERR_EN) {
  876. omap_hsmmc_dbg_report_irq(host, status);
  877. if (status & (CTO_EN | CCRC_EN | CEB_EN))
  878. end_cmd = 1;
  879. if (host->data || host->response_busy) {
  880. end_trans = !end_cmd;
  881. host->response_busy = 0;
  882. }
  883. if (status & (CTO_EN | DTO_EN))
  884. hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
  885. else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
  886. BADA_EN))
  887. hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
  888. if (status & ACE_EN) {
  889. u32 ac12;
  890. ac12 = OMAP_HSMMC_READ(host->base, AC12);
  891. if (!(ac12 & ACNE) && host->mrq->sbc) {
  892. end_cmd = 1;
  893. if (ac12 & ACTO)
  894. error = -ETIMEDOUT;
  895. else if (ac12 & (ACCE | ACEB | ACIE))
  896. error = -EILSEQ;
  897. host->mrq->sbc->error = error;
  898. hsmmc_command_incomplete(host, error, end_cmd);
  899. }
  900. dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
  901. }
  902. }
  903. OMAP_HSMMC_WRITE(host->base, STAT, status);
  904. if (end_cmd || ((status & CC_EN) && host->cmd))
  905. omap_hsmmc_cmd_done(host, host->cmd);
  906. if ((end_trans || (status & TC_EN)) && host->mrq)
  907. omap_hsmmc_xfer_done(host, data);
  908. }
  909. /*
  910. * MMC controller IRQ handler
  911. */
  912. static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
  913. {
  914. struct omap_hsmmc_host *host = dev_id;
  915. int status;
  916. status = OMAP_HSMMC_READ(host->base, STAT);
  917. while (status & (INT_EN_MASK | CIRQ_EN)) {
  918. if (host->req_in_progress)
  919. omap_hsmmc_do_irq(host, status);
  920. if (status & CIRQ_EN)
  921. mmc_signal_sdio_irq(host->mmc);
  922. /* Flush posted write */
  923. status = OMAP_HSMMC_READ(host->base, STAT);
  924. }
  925. return IRQ_HANDLED;
  926. }
  927. static void set_sd_bus_power(struct omap_hsmmc_host *host)
  928. {
  929. unsigned long i;
  930. OMAP_HSMMC_WRITE(host->base, HCTL,
  931. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  932. for (i = 0; i < loops_per_jiffy; i++) {
  933. if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
  934. break;
  935. cpu_relax();
  936. }
  937. }
  938. /*
  939. * Switch MMC interface voltage ... only relevant for MMC1.
  940. *
  941. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  942. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  943. * Some chips, like eMMC ones, use internal transceivers.
  944. */
  945. static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
  946. {
  947. u32 reg_val = 0;
  948. int ret;
  949. /* Disable the clocks */
  950. clk_disable_unprepare(host->dbclk);
  951. /* Turn the power off */
  952. ret = omap_hsmmc_set_power(host, 0);
  953. /* Turn the power ON with given VDD 1.8 or 3.0v */
  954. if (!ret)
  955. ret = omap_hsmmc_set_power(host, 1);
  956. clk_prepare_enable(host->dbclk);
  957. if (ret != 0)
  958. goto err;
  959. OMAP_HSMMC_WRITE(host->base, HCTL,
  960. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  961. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  962. /*
  963. * If a MMC dual voltage card is detected, the set_ios fn calls
  964. * this fn with VDD bit set for 1.8V. Upon card removal from the
  965. * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  966. *
  967. * Cope with a bit of slop in the range ... per data sheets:
  968. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  969. * but recommended values are 1.71V to 1.89V
  970. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  971. * but recommended values are 2.7V to 3.3V
  972. *
  973. * Board setup code shouldn't permit anything very out-of-range.
  974. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  975. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  976. */
  977. if ((1 << vdd) <= MMC_VDD_23_24)
  978. reg_val |= SDVS18;
  979. else
  980. reg_val |= SDVS30;
  981. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  982. set_sd_bus_power(host);
  983. return 0;
  984. err:
  985. dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  986. return ret;
  987. }
  988. static void omap_hsmmc_dma_callback(void *param)
  989. {
  990. struct omap_hsmmc_host *host = param;
  991. struct dma_chan *chan;
  992. struct mmc_data *data;
  993. int req_in_progress;
  994. spin_lock_irq(&host->irq_lock);
  995. if (host->dma_ch < 0) {
  996. spin_unlock_irq(&host->irq_lock);
  997. return;
  998. }
  999. data = host->mrq->data;
  1000. chan = omap_hsmmc_get_dma_chan(host, data);
  1001. if (!data->host_cookie)
  1002. dma_unmap_sg(chan->device->dev,
  1003. data->sg, data->sg_len,
  1004. mmc_get_dma_dir(data));
  1005. req_in_progress = host->req_in_progress;
  1006. host->dma_ch = -1;
  1007. spin_unlock_irq(&host->irq_lock);
  1008. /* If DMA has finished after TC, complete the request */
  1009. if (!req_in_progress) {
  1010. struct mmc_request *mrq = host->mrq;
  1011. host->mrq = NULL;
  1012. mmc_request_done(host->mmc, mrq);
  1013. }
  1014. }
  1015. static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
  1016. struct mmc_data *data,
  1017. struct omap_hsmmc_next *next,
  1018. struct dma_chan *chan)
  1019. {
  1020. int dma_len;
  1021. if (!next && data->host_cookie &&
  1022. data->host_cookie != host->next_data.cookie) {
  1023. dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
  1024. " host->next_data.cookie %d\n",
  1025. __func__, data->host_cookie, host->next_data.cookie);
  1026. data->host_cookie = 0;
  1027. }
  1028. /* Check if next job is already prepared */
  1029. if (next || data->host_cookie != host->next_data.cookie) {
  1030. dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
  1031. mmc_get_dma_dir(data));
  1032. } else {
  1033. dma_len = host->next_data.dma_len;
  1034. host->next_data.dma_len = 0;
  1035. }
  1036. if (dma_len == 0)
  1037. return -EINVAL;
  1038. if (next) {
  1039. next->dma_len = dma_len;
  1040. data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
  1041. } else
  1042. host->dma_len = dma_len;
  1043. return 0;
  1044. }
  1045. /*
  1046. * Routine to configure and start DMA for the MMC card
  1047. */
  1048. static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
  1049. struct mmc_request *req)
  1050. {
  1051. struct dma_async_tx_descriptor *tx;
  1052. int ret = 0, i;
  1053. struct mmc_data *data = req->data;
  1054. struct dma_chan *chan;
  1055. struct dma_slave_config cfg = {
  1056. .src_addr = host->mapbase + OMAP_HSMMC_DATA,
  1057. .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
  1058. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  1059. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  1060. .src_maxburst = data->blksz / 4,
  1061. .dst_maxburst = data->blksz / 4,
  1062. };
  1063. /* Sanity check: all the SG entries must be aligned by block size. */
  1064. for (i = 0; i < data->sg_len; i++) {
  1065. struct scatterlist *sgl;
  1066. sgl = data->sg + i;
  1067. if (sgl->length % data->blksz)
  1068. return -EINVAL;
  1069. }
  1070. if ((data->blksz % 4) != 0)
  1071. /* REVISIT: The MMC buffer increments only when MSB is written.
  1072. * Return error for blksz which is non multiple of four.
  1073. */
  1074. return -EINVAL;
  1075. BUG_ON(host->dma_ch != -1);
  1076. chan = omap_hsmmc_get_dma_chan(host, data);
  1077. ret = dmaengine_slave_config(chan, &cfg);
  1078. if (ret)
  1079. return ret;
  1080. ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
  1081. if (ret)
  1082. return ret;
  1083. tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
  1084. data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  1085. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1086. if (!tx) {
  1087. dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
  1088. /* FIXME: cleanup */
  1089. return -1;
  1090. }
  1091. tx->callback = omap_hsmmc_dma_callback;
  1092. tx->callback_param = host;
  1093. /* Does not fail */
  1094. dmaengine_submit(tx);
  1095. host->dma_ch = 1;
  1096. return 0;
  1097. }
  1098. static void set_data_timeout(struct omap_hsmmc_host *host,
  1099. unsigned long long timeout_ns,
  1100. unsigned int timeout_clks)
  1101. {
  1102. unsigned long long timeout = timeout_ns;
  1103. unsigned int cycle_ns;
  1104. uint32_t reg, clkd, dto = 0;
  1105. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  1106. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  1107. if (clkd == 0)
  1108. clkd = 1;
  1109. cycle_ns = 1000000000 / (host->clk_rate / clkd);
  1110. do_div(timeout, cycle_ns);
  1111. timeout += timeout_clks;
  1112. if (timeout) {
  1113. while ((timeout & 0x80000000) == 0) {
  1114. dto += 1;
  1115. timeout <<= 1;
  1116. }
  1117. dto = 31 - dto;
  1118. timeout <<= 1;
  1119. if (timeout && dto)
  1120. dto += 1;
  1121. if (dto >= 13)
  1122. dto -= 13;
  1123. else
  1124. dto = 0;
  1125. if (dto > 14)
  1126. dto = 14;
  1127. }
  1128. reg &= ~DTO_MASK;
  1129. reg |= dto << DTO_SHIFT;
  1130. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  1131. }
  1132. static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
  1133. {
  1134. struct mmc_request *req = host->mrq;
  1135. struct dma_chan *chan;
  1136. if (!req->data)
  1137. return;
  1138. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  1139. | (req->data->blocks << 16));
  1140. set_data_timeout(host, req->data->timeout_ns,
  1141. req->data->timeout_clks);
  1142. chan = omap_hsmmc_get_dma_chan(host, req->data);
  1143. dma_async_issue_pending(chan);
  1144. }
  1145. /*
  1146. * Configure block length for MMC/SD cards and initiate the transfer.
  1147. */
  1148. static int
  1149. omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
  1150. {
  1151. int ret;
  1152. unsigned long long timeout;
  1153. host->data = req->data;
  1154. if (req->data == NULL) {
  1155. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  1156. if (req->cmd->flags & MMC_RSP_BUSY) {
  1157. timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
  1158. /*
  1159. * Set an arbitrary 100ms data timeout for commands with
  1160. * busy signal and no indication of busy_timeout.
  1161. */
  1162. if (!timeout)
  1163. timeout = 100000000U;
  1164. set_data_timeout(host, timeout, 0);
  1165. }
  1166. return 0;
  1167. }
  1168. if (host->use_dma) {
  1169. ret = omap_hsmmc_setup_dma_transfer(host, req);
  1170. if (ret != 0) {
  1171. dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
  1172. return ret;
  1173. }
  1174. }
  1175. return 0;
  1176. }
  1177. static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1178. int err)
  1179. {
  1180. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1181. struct mmc_data *data = mrq->data;
  1182. if (host->use_dma && data->host_cookie) {
  1183. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
  1184. dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
  1185. mmc_get_dma_dir(data));
  1186. data->host_cookie = 0;
  1187. }
  1188. }
  1189. static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
  1190. {
  1191. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1192. if (mrq->data->host_cookie) {
  1193. mrq->data->host_cookie = 0;
  1194. return ;
  1195. }
  1196. if (host->use_dma) {
  1197. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
  1198. if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
  1199. &host->next_data, c))
  1200. mrq->data->host_cookie = 0;
  1201. }
  1202. }
  1203. /*
  1204. * Request function. for read/write operation
  1205. */
  1206. static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
  1207. {
  1208. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1209. int err;
  1210. BUG_ON(host->req_in_progress);
  1211. BUG_ON(host->dma_ch != -1);
  1212. if (host->reqs_blocked)
  1213. host->reqs_blocked = 0;
  1214. WARN_ON(host->mrq != NULL);
  1215. host->mrq = req;
  1216. host->clk_rate = clk_get_rate(host->fclk);
  1217. err = omap_hsmmc_prepare_data(host, req);
  1218. if (err) {
  1219. req->cmd->error = err;
  1220. if (req->data)
  1221. req->data->error = err;
  1222. host->mrq = NULL;
  1223. mmc_request_done(mmc, req);
  1224. return;
  1225. }
  1226. if (req->sbc && !(host->flags & AUTO_CMD23)) {
  1227. omap_hsmmc_start_command(host, req->sbc, NULL);
  1228. return;
  1229. }
  1230. omap_hsmmc_start_dma_transfer(host);
  1231. omap_hsmmc_start_command(host, req->cmd, req->data);
  1232. }
  1233. /* Routine to configure clock values. Exposed API to core */
  1234. static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1235. {
  1236. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1237. int do_send_init_stream = 0;
  1238. if (ios->power_mode != host->power_mode) {
  1239. switch (ios->power_mode) {
  1240. case MMC_POWER_OFF:
  1241. omap_hsmmc_set_power(host, 0);
  1242. break;
  1243. case MMC_POWER_UP:
  1244. omap_hsmmc_set_power(host, 1);
  1245. break;
  1246. case MMC_POWER_ON:
  1247. do_send_init_stream = 1;
  1248. break;
  1249. }
  1250. host->power_mode = ios->power_mode;
  1251. }
  1252. /* FIXME: set registers based only on changes to ios */
  1253. omap_hsmmc_set_bus_width(host);
  1254. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1255. /* Only MMC1 can interface at 3V without some flavor
  1256. * of external transceiver; but they all handle 1.8V.
  1257. */
  1258. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  1259. (ios->vdd == DUAL_VOLT_OCR_BIT)) {
  1260. /*
  1261. * The mmc_select_voltage fn of the core does
  1262. * not seem to set the power_mode to
  1263. * MMC_POWER_UP upon recalculating the voltage.
  1264. * vdd 1.8v.
  1265. */
  1266. if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
  1267. dev_dbg(mmc_dev(host->mmc),
  1268. "Switch operation failed\n");
  1269. }
  1270. }
  1271. omap_hsmmc_set_clock(host);
  1272. if (do_send_init_stream)
  1273. send_init_stream(host);
  1274. omap_hsmmc_set_bus_mode(host);
  1275. }
  1276. static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1277. {
  1278. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1279. if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) {
  1280. struct device_node *np = mmc_dev(mmc)->of_node;
  1281. /*
  1282. * REVISIT: should be moved to sdio core and made more
  1283. * general e.g. by expanding the DT bindings of child nodes
  1284. * to provide a mechanism to provide this information:
  1285. * Documentation/devicetree/bindings/mmc/mmc-card.txt
  1286. */
  1287. np = of_get_compatible_child(np, "ti,wl1251");
  1288. if (np) {
  1289. /*
  1290. * We have TI wl1251 attached to MMC3. Pass this
  1291. * information to the SDIO core because it can't be
  1292. * probed by normal methods.
  1293. */
  1294. dev_info(host->dev, "found wl1251\n");
  1295. card->quirks |= MMC_QUIRK_NONSTD_SDIO;
  1296. card->cccr.wide_bus = 1;
  1297. card->cis.vendor = 0x104c;
  1298. card->cis.device = 0x9066;
  1299. card->cis.blksize = 512;
  1300. card->cis.max_dtr = 24000000;
  1301. card->ocr = 0x80;
  1302. of_node_put(np);
  1303. }
  1304. }
  1305. }
  1306. static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  1307. {
  1308. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1309. u32 irq_mask, con;
  1310. unsigned long flags;
  1311. spin_lock_irqsave(&host->irq_lock, flags);
  1312. con = OMAP_HSMMC_READ(host->base, CON);
  1313. irq_mask = OMAP_HSMMC_READ(host->base, ISE);
  1314. if (enable) {
  1315. host->flags |= HSMMC_SDIO_IRQ_ENABLED;
  1316. irq_mask |= CIRQ_EN;
  1317. con |= CTPL | CLKEXTFREE;
  1318. } else {
  1319. host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
  1320. irq_mask &= ~CIRQ_EN;
  1321. con &= ~(CTPL | CLKEXTFREE);
  1322. }
  1323. OMAP_HSMMC_WRITE(host->base, CON, con);
  1324. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  1325. /*
  1326. * if enable, piggy back detection on current request
  1327. * but always disable immediately
  1328. */
  1329. if (!host->req_in_progress || !enable)
  1330. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  1331. /* flush posted write */
  1332. OMAP_HSMMC_READ(host->base, IE);
  1333. spin_unlock_irqrestore(&host->irq_lock, flags);
  1334. }
  1335. static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
  1336. {
  1337. int ret;
  1338. /*
  1339. * For omaps with wake-up path, wakeirq will be irq from pinctrl and
  1340. * for other omaps, wakeirq will be from GPIO (dat line remuxed to
  1341. * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
  1342. * with functional clock disabled.
  1343. */
  1344. if (!host->dev->of_node || !host->wake_irq)
  1345. return -ENODEV;
  1346. ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
  1347. if (ret) {
  1348. dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
  1349. goto err;
  1350. }
  1351. /*
  1352. * Some omaps don't have wake-up path from deeper idle states
  1353. * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
  1354. */
  1355. if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
  1356. struct pinctrl *p = devm_pinctrl_get(host->dev);
  1357. if (IS_ERR(p)) {
  1358. ret = PTR_ERR(p);
  1359. goto err_free_irq;
  1360. }
  1361. if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
  1362. dev_info(host->dev, "missing idle pinctrl state\n");
  1363. devm_pinctrl_put(p);
  1364. ret = -EINVAL;
  1365. goto err_free_irq;
  1366. }
  1367. devm_pinctrl_put(p);
  1368. }
  1369. OMAP_HSMMC_WRITE(host->base, HCTL,
  1370. OMAP_HSMMC_READ(host->base, HCTL) | IWE);
  1371. return 0;
  1372. err_free_irq:
  1373. dev_pm_clear_wake_irq(host->dev);
  1374. err:
  1375. dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
  1376. host->wake_irq = 0;
  1377. return ret;
  1378. }
  1379. static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
  1380. {
  1381. u32 hctl, capa, value;
  1382. /* Only MMC1 supports 3.0V */
  1383. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1384. hctl = SDVS30;
  1385. capa = VS30 | VS18;
  1386. } else {
  1387. hctl = SDVS18;
  1388. capa = VS18;
  1389. }
  1390. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  1391. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  1392. value = OMAP_HSMMC_READ(host->base, CAPA);
  1393. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  1394. /* Set SD bus power bit */
  1395. set_sd_bus_power(host);
  1396. }
  1397. static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
  1398. unsigned int direction, int blk_size)
  1399. {
  1400. /* This controller can't do multiblock reads due to hw bugs */
  1401. if (direction == MMC_DATA_READ)
  1402. return 1;
  1403. return blk_size;
  1404. }
  1405. static struct mmc_host_ops omap_hsmmc_ops = {
  1406. .post_req = omap_hsmmc_post_req,
  1407. .pre_req = omap_hsmmc_pre_req,
  1408. .request = omap_hsmmc_request,
  1409. .set_ios = omap_hsmmc_set_ios,
  1410. .get_cd = mmc_gpio_get_cd,
  1411. .get_ro = mmc_gpio_get_ro,
  1412. .init_card = omap_hsmmc_init_card,
  1413. .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
  1414. };
  1415. #ifdef CONFIG_DEBUG_FS
  1416. static int mmc_regs_show(struct seq_file *s, void *data)
  1417. {
  1418. struct mmc_host *mmc = s->private;
  1419. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1420. seq_printf(s, "mmc%d:\n", mmc->index);
  1421. seq_printf(s, "sdio irq mode\t%s\n",
  1422. (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
  1423. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  1424. seq_printf(s, "sdio irq \t%s\n",
  1425. (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
  1426. : "disabled");
  1427. }
  1428. seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
  1429. pm_runtime_get_sync(host->dev);
  1430. seq_puts(s, "\nregs:\n");
  1431. seq_printf(s, "CON:\t\t0x%08x\n",
  1432. OMAP_HSMMC_READ(host->base, CON));
  1433. seq_printf(s, "PSTATE:\t\t0x%08x\n",
  1434. OMAP_HSMMC_READ(host->base, PSTATE));
  1435. seq_printf(s, "HCTL:\t\t0x%08x\n",
  1436. OMAP_HSMMC_READ(host->base, HCTL));
  1437. seq_printf(s, "SYSCTL:\t\t0x%08x\n",
  1438. OMAP_HSMMC_READ(host->base, SYSCTL));
  1439. seq_printf(s, "IE:\t\t0x%08x\n",
  1440. OMAP_HSMMC_READ(host->base, IE));
  1441. seq_printf(s, "ISE:\t\t0x%08x\n",
  1442. OMAP_HSMMC_READ(host->base, ISE));
  1443. seq_printf(s, "CAPA:\t\t0x%08x\n",
  1444. OMAP_HSMMC_READ(host->base, CAPA));
  1445. pm_runtime_mark_last_busy(host->dev);
  1446. pm_runtime_put_autosuspend(host->dev);
  1447. return 0;
  1448. }
  1449. DEFINE_SHOW_ATTRIBUTE(mmc_regs);
  1450. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1451. {
  1452. if (mmc->debugfs_root)
  1453. debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
  1454. mmc, &mmc_regs_fops);
  1455. }
  1456. #else
  1457. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1458. {
  1459. }
  1460. #endif
  1461. #ifdef CONFIG_OF
  1462. static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
  1463. /* See 35xx errata 2.1.1.128 in SPRZ278F */
  1464. .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
  1465. };
  1466. static const struct omap_mmc_of_data omap4_mmc_of_data = {
  1467. .reg_offset = 0x100,
  1468. };
  1469. static const struct omap_mmc_of_data am33xx_mmc_of_data = {
  1470. .reg_offset = 0x100,
  1471. .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
  1472. };
  1473. static const struct of_device_id omap_mmc_of_match[] = {
  1474. {
  1475. .compatible = "ti,omap2-hsmmc",
  1476. },
  1477. {
  1478. .compatible = "ti,omap3-pre-es3-hsmmc",
  1479. .data = &omap3_pre_es3_mmc_of_data,
  1480. },
  1481. {
  1482. .compatible = "ti,omap3-hsmmc",
  1483. },
  1484. {
  1485. .compatible = "ti,omap4-hsmmc",
  1486. .data = &omap4_mmc_of_data,
  1487. },
  1488. {
  1489. .compatible = "ti,am33xx-hsmmc",
  1490. .data = &am33xx_mmc_of_data,
  1491. },
  1492. {},
  1493. };
  1494. MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
  1495. static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
  1496. {
  1497. struct omap_hsmmc_platform_data *pdata, *legacy;
  1498. struct device_node *np = dev->of_node;
  1499. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  1500. if (!pdata)
  1501. return ERR_PTR(-ENOMEM); /* out of memory */
  1502. legacy = dev_get_platdata(dev);
  1503. if (legacy && legacy->name)
  1504. pdata->name = legacy->name;
  1505. if (of_find_property(np, "ti,dual-volt", NULL))
  1506. pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1507. if (of_find_property(np, "ti,non-removable", NULL)) {
  1508. pdata->nonremovable = true;
  1509. pdata->no_regulator_off_init = true;
  1510. }
  1511. if (of_find_property(np, "ti,needs-special-reset", NULL))
  1512. pdata->features |= HSMMC_HAS_UPDATED_RESET;
  1513. if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
  1514. pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
  1515. return pdata;
  1516. }
  1517. #else
  1518. static inline struct omap_hsmmc_platform_data
  1519. *of_get_hsmmc_pdata(struct device *dev)
  1520. {
  1521. return ERR_PTR(-EINVAL);
  1522. }
  1523. #endif
  1524. static int omap_hsmmc_probe(struct platform_device *pdev)
  1525. {
  1526. struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
  1527. struct mmc_host *mmc;
  1528. struct omap_hsmmc_host *host = NULL;
  1529. struct resource *res;
  1530. int ret, irq;
  1531. const struct of_device_id *match;
  1532. const struct omap_mmc_of_data *data;
  1533. void __iomem *base;
  1534. match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
  1535. if (match) {
  1536. pdata = of_get_hsmmc_pdata(&pdev->dev);
  1537. if (IS_ERR(pdata))
  1538. return PTR_ERR(pdata);
  1539. if (match->data) {
  1540. data = match->data;
  1541. pdata->reg_offset = data->reg_offset;
  1542. pdata->controller_flags |= data->controller_flags;
  1543. }
  1544. }
  1545. if (pdata == NULL) {
  1546. dev_err(&pdev->dev, "Platform Data is missing\n");
  1547. return -ENXIO;
  1548. }
  1549. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1550. irq = platform_get_irq(pdev, 0);
  1551. if (res == NULL || irq < 0)
  1552. return -ENXIO;
  1553. base = devm_ioremap_resource(&pdev->dev, res);
  1554. if (IS_ERR(base))
  1555. return PTR_ERR(base);
  1556. mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
  1557. if (!mmc) {
  1558. ret = -ENOMEM;
  1559. goto err;
  1560. }
  1561. ret = mmc_of_parse(mmc);
  1562. if (ret)
  1563. goto err1;
  1564. host = mmc_priv(mmc);
  1565. host->mmc = mmc;
  1566. host->pdata = pdata;
  1567. host->dev = &pdev->dev;
  1568. host->use_dma = 1;
  1569. host->dma_ch = -1;
  1570. host->irq = irq;
  1571. host->mapbase = res->start + pdata->reg_offset;
  1572. host->base = base + pdata->reg_offset;
  1573. host->power_mode = MMC_POWER_OFF;
  1574. host->next_data.cookie = 1;
  1575. host->pbias_enabled = 0;
  1576. host->vqmmc_enabled = 0;
  1577. platform_set_drvdata(pdev, host);
  1578. if (pdev->dev.of_node)
  1579. host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
  1580. mmc->ops = &omap_hsmmc_ops;
  1581. mmc->f_min = OMAP_MMC_MIN_CLOCK;
  1582. if (pdata->max_freq > 0)
  1583. mmc->f_max = pdata->max_freq;
  1584. else if (mmc->f_max == 0)
  1585. mmc->f_max = OMAP_MMC_MAX_CLOCK;
  1586. spin_lock_init(&host->irq_lock);
  1587. host->fclk = devm_clk_get(&pdev->dev, "fck");
  1588. if (IS_ERR(host->fclk)) {
  1589. ret = PTR_ERR(host->fclk);
  1590. host->fclk = NULL;
  1591. goto err1;
  1592. }
  1593. if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
  1594. dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
  1595. omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
  1596. }
  1597. device_init_wakeup(&pdev->dev, true);
  1598. pm_runtime_enable(host->dev);
  1599. pm_runtime_get_sync(host->dev);
  1600. pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
  1601. pm_runtime_use_autosuspend(host->dev);
  1602. omap_hsmmc_context_save(host);
  1603. host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
  1604. /*
  1605. * MMC can still work without debounce clock.
  1606. */
  1607. if (IS_ERR(host->dbclk)) {
  1608. host->dbclk = NULL;
  1609. } else if (clk_prepare_enable(host->dbclk) != 0) {
  1610. dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
  1611. host->dbclk = NULL;
  1612. }
  1613. /* Set this to a value that allows allocating an entire descriptor
  1614. * list within a page (zero order allocation). */
  1615. mmc->max_segs = 64;
  1616. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  1617. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  1618. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1619. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1620. MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
  1621. mmc->caps |= mmc_pdata(host)->caps;
  1622. if (mmc->caps & MMC_CAP_8_BIT_DATA)
  1623. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1624. if (mmc_pdata(host)->nonremovable)
  1625. mmc->caps |= MMC_CAP_NONREMOVABLE;
  1626. mmc->pm_caps |= mmc_pdata(host)->pm_caps;
  1627. omap_hsmmc_conf_bus_power(host);
  1628. host->rx_chan = dma_request_chan(&pdev->dev, "rx");
  1629. if (IS_ERR(host->rx_chan)) {
  1630. dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
  1631. ret = PTR_ERR(host->rx_chan);
  1632. goto err_irq;
  1633. }
  1634. host->tx_chan = dma_request_chan(&pdev->dev, "tx");
  1635. if (IS_ERR(host->tx_chan)) {
  1636. dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
  1637. ret = PTR_ERR(host->tx_chan);
  1638. goto err_irq;
  1639. }
  1640. /*
  1641. * Limit the maximum segment size to the lower of the request size
  1642. * and the DMA engine device segment size limits. In reality, with
  1643. * 32-bit transfers, the DMA engine can do longer segments than this
  1644. * but there is no way to represent that in the DMA model - if we
  1645. * increase this figure here, we get warnings from the DMA API debug.
  1646. */
  1647. mmc->max_seg_size = min3(mmc->max_req_size,
  1648. dma_get_max_seg_size(host->rx_chan->device->dev),
  1649. dma_get_max_seg_size(host->tx_chan->device->dev));
  1650. /* Request IRQ for MMC operations */
  1651. ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
  1652. mmc_hostname(mmc), host);
  1653. if (ret) {
  1654. dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  1655. goto err_irq;
  1656. }
  1657. ret = omap_hsmmc_reg_get(host);
  1658. if (ret)
  1659. goto err_irq;
  1660. if (!mmc->ocr_avail)
  1661. mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
  1662. omap_hsmmc_disable_irq(host);
  1663. /*
  1664. * For now, only support SDIO interrupt if we have a separate
  1665. * wake-up interrupt configured from device tree. This is because
  1666. * the wake-up interrupt is needed for idle state and some
  1667. * platforms need special quirks. And we don't want to add new
  1668. * legacy mux platform init code callbacks any longer as we
  1669. * are moving to DT based booting anyways.
  1670. */
  1671. ret = omap_hsmmc_configure_wake_irq(host);
  1672. if (!ret)
  1673. mmc->caps |= MMC_CAP_SDIO_IRQ;
  1674. mmc_add_host(mmc);
  1675. if (mmc_pdata(host)->name != NULL) {
  1676. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  1677. if (ret < 0)
  1678. goto err_slot_name;
  1679. }
  1680. omap_hsmmc_debugfs(mmc);
  1681. pm_runtime_mark_last_busy(host->dev);
  1682. pm_runtime_put_autosuspend(host->dev);
  1683. return 0;
  1684. err_slot_name:
  1685. mmc_remove_host(mmc);
  1686. err_irq:
  1687. device_init_wakeup(&pdev->dev, false);
  1688. if (!IS_ERR_OR_NULL(host->tx_chan))
  1689. dma_release_channel(host->tx_chan);
  1690. if (!IS_ERR_OR_NULL(host->rx_chan))
  1691. dma_release_channel(host->rx_chan);
  1692. pm_runtime_dont_use_autosuspend(host->dev);
  1693. pm_runtime_put_sync(host->dev);
  1694. pm_runtime_disable(host->dev);
  1695. clk_disable_unprepare(host->dbclk);
  1696. err1:
  1697. mmc_free_host(mmc);
  1698. err:
  1699. return ret;
  1700. }
  1701. static int omap_hsmmc_remove(struct platform_device *pdev)
  1702. {
  1703. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1704. pm_runtime_get_sync(host->dev);
  1705. mmc_remove_host(host->mmc);
  1706. dma_release_channel(host->tx_chan);
  1707. dma_release_channel(host->rx_chan);
  1708. dev_pm_clear_wake_irq(host->dev);
  1709. pm_runtime_dont_use_autosuspend(host->dev);
  1710. pm_runtime_put_sync(host->dev);
  1711. pm_runtime_disable(host->dev);
  1712. device_init_wakeup(&pdev->dev, false);
  1713. clk_disable_unprepare(host->dbclk);
  1714. mmc_free_host(host->mmc);
  1715. return 0;
  1716. }
  1717. #ifdef CONFIG_PM_SLEEP
  1718. static int omap_hsmmc_suspend(struct device *dev)
  1719. {
  1720. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1721. if (!host)
  1722. return 0;
  1723. pm_runtime_get_sync(host->dev);
  1724. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
  1725. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  1726. OMAP_HSMMC_WRITE(host->base, IE, 0);
  1727. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1728. OMAP_HSMMC_WRITE(host->base, HCTL,
  1729. OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
  1730. }
  1731. clk_disable_unprepare(host->dbclk);
  1732. pm_runtime_put_sync(host->dev);
  1733. return 0;
  1734. }
  1735. /* Routine to resume the MMC device */
  1736. static int omap_hsmmc_resume(struct device *dev)
  1737. {
  1738. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1739. if (!host)
  1740. return 0;
  1741. pm_runtime_get_sync(host->dev);
  1742. clk_prepare_enable(host->dbclk);
  1743. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
  1744. omap_hsmmc_conf_bus_power(host);
  1745. pm_runtime_mark_last_busy(host->dev);
  1746. pm_runtime_put_autosuspend(host->dev);
  1747. return 0;
  1748. }
  1749. #endif
  1750. static int omap_hsmmc_runtime_suspend(struct device *dev)
  1751. {
  1752. struct omap_hsmmc_host *host;
  1753. unsigned long flags;
  1754. int ret = 0;
  1755. host = dev_get_drvdata(dev);
  1756. omap_hsmmc_context_save(host);
  1757. dev_dbg(dev, "disabled\n");
  1758. spin_lock_irqsave(&host->irq_lock, flags);
  1759. if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
  1760. (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
  1761. /* disable sdio irq handling to prevent race */
  1762. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  1763. OMAP_HSMMC_WRITE(host->base, IE, 0);
  1764. if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
  1765. /*
  1766. * dat1 line low, pending sdio irq
  1767. * race condition: possible irq handler running on
  1768. * multi-core, abort
  1769. */
  1770. dev_dbg(dev, "pending sdio irq, abort suspend\n");
  1771. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1772. OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
  1773. OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
  1774. pm_runtime_mark_last_busy(dev);
  1775. ret = -EBUSY;
  1776. goto abort;
  1777. }
  1778. pinctrl_pm_select_idle_state(dev);
  1779. } else {
  1780. pinctrl_pm_select_idle_state(dev);
  1781. }
  1782. abort:
  1783. spin_unlock_irqrestore(&host->irq_lock, flags);
  1784. return ret;
  1785. }
  1786. static int omap_hsmmc_runtime_resume(struct device *dev)
  1787. {
  1788. struct omap_hsmmc_host *host;
  1789. unsigned long flags;
  1790. host = dev_get_drvdata(dev);
  1791. omap_hsmmc_context_restore(host);
  1792. dev_dbg(dev, "enabled\n");
  1793. spin_lock_irqsave(&host->irq_lock, flags);
  1794. if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
  1795. (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
  1796. pinctrl_select_default_state(host->dev);
  1797. /* irq lost, if pinmux incorrect */
  1798. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  1799. OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
  1800. OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
  1801. } else {
  1802. pinctrl_select_default_state(host->dev);
  1803. }
  1804. spin_unlock_irqrestore(&host->irq_lock, flags);
  1805. return 0;
  1806. }
  1807. static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
  1808. SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
  1809. .runtime_suspend = omap_hsmmc_runtime_suspend,
  1810. .runtime_resume = omap_hsmmc_runtime_resume,
  1811. };
  1812. static struct platform_driver omap_hsmmc_driver = {
  1813. .probe = omap_hsmmc_probe,
  1814. .remove = omap_hsmmc_remove,
  1815. .driver = {
  1816. .name = DRIVER_NAME,
  1817. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1818. .pm = &omap_hsmmc_dev_pm_ops,
  1819. .of_match_table = of_match_ptr(omap_mmc_of_match),
  1820. },
  1821. };
  1822. module_platform_driver(omap_hsmmc_driver);
  1823. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  1824. MODULE_LICENSE("GPL");
  1825. MODULE_ALIAS("platform:" DRIVER_NAME);
  1826. MODULE_AUTHOR("Texas Instruments Inc");