mxcmmc.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
  4. *
  5. * This is a driver for the SDHC controller found in Freescale MX2/MX3
  6. * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
  7. * Unlike the hardware found on MX1, this hardware just works and does
  8. * not need all the quirks found in imxmmc.c, hence the separate driver.
  9. *
  10. * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  11. * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
  12. *
  13. * derived from pxamci.c by Russell King
  14. */
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/ioport.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/highmem.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/mmc/card.h>
  26. #include <linux/delay.h>
  27. #include <linux/clk.h>
  28. #include <linux/io.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <linux/dmaengine.h>
  31. #include <linux/types.h>
  32. #include <linux/of.h>
  33. #include <linux/of_device.h>
  34. #include <linux/of_dma.h>
  35. #include <linux/mmc/slot-gpio.h>
  36. #include <asm/dma.h>
  37. #include <asm/irq.h>
  38. #include <linux/platform_data/mmc-mxcmmc.h>
  39. #include <linux/platform_data/dma-imx.h>
  40. #define DRIVER_NAME "mxc-mmc"
  41. #define MXCMCI_TIMEOUT_MS 10000
  42. #define MMC_REG_STR_STP_CLK 0x00
  43. #define MMC_REG_STATUS 0x04
  44. #define MMC_REG_CLK_RATE 0x08
  45. #define MMC_REG_CMD_DAT_CONT 0x0C
  46. #define MMC_REG_RES_TO 0x10
  47. #define MMC_REG_READ_TO 0x14
  48. #define MMC_REG_BLK_LEN 0x18
  49. #define MMC_REG_NOB 0x1C
  50. #define MMC_REG_REV_NO 0x20
  51. #define MMC_REG_INT_CNTR 0x24
  52. #define MMC_REG_CMD 0x28
  53. #define MMC_REG_ARG 0x2C
  54. #define MMC_REG_RES_FIFO 0x34
  55. #define MMC_REG_BUFFER_ACCESS 0x38
  56. #define STR_STP_CLK_RESET (1 << 3)
  57. #define STR_STP_CLK_START_CLK (1 << 1)
  58. #define STR_STP_CLK_STOP_CLK (1 << 0)
  59. #define STATUS_CARD_INSERTION (1 << 31)
  60. #define STATUS_CARD_REMOVAL (1 << 30)
  61. #define STATUS_YBUF_EMPTY (1 << 29)
  62. #define STATUS_XBUF_EMPTY (1 << 28)
  63. #define STATUS_YBUF_FULL (1 << 27)
  64. #define STATUS_XBUF_FULL (1 << 26)
  65. #define STATUS_BUF_UND_RUN (1 << 25)
  66. #define STATUS_BUF_OVFL (1 << 24)
  67. #define STATUS_SDIO_INT_ACTIVE (1 << 14)
  68. #define STATUS_END_CMD_RESP (1 << 13)
  69. #define STATUS_WRITE_OP_DONE (1 << 12)
  70. #define STATUS_DATA_TRANS_DONE (1 << 11)
  71. #define STATUS_READ_OP_DONE (1 << 11)
  72. #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
  73. #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
  74. #define STATUS_BUF_READ_RDY (1 << 7)
  75. #define STATUS_BUF_WRITE_RDY (1 << 6)
  76. #define STATUS_RESP_CRC_ERR (1 << 5)
  77. #define STATUS_CRC_READ_ERR (1 << 3)
  78. #define STATUS_CRC_WRITE_ERR (1 << 2)
  79. #define STATUS_TIME_OUT_RESP (1 << 1)
  80. #define STATUS_TIME_OUT_READ (1 << 0)
  81. #define STATUS_ERR_MASK 0x2f
  82. #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
  83. #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
  84. #define CMD_DAT_CONT_START_READWAIT (1 << 10)
  85. #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
  86. #define CMD_DAT_CONT_INIT (1 << 7)
  87. #define CMD_DAT_CONT_WRITE (1 << 4)
  88. #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
  89. #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
  90. #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
  91. #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
  92. #define INT_SDIO_INT_WKP_EN (1 << 18)
  93. #define INT_CARD_INSERTION_WKP_EN (1 << 17)
  94. #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
  95. #define INT_CARD_INSERTION_EN (1 << 15)
  96. #define INT_CARD_REMOVAL_EN (1 << 14)
  97. #define INT_SDIO_IRQ_EN (1 << 13)
  98. #define INT_DAT0_EN (1 << 12)
  99. #define INT_BUF_READ_EN (1 << 4)
  100. #define INT_BUF_WRITE_EN (1 << 3)
  101. #define INT_END_CMD_RES_EN (1 << 2)
  102. #define INT_WRITE_OP_DONE_EN (1 << 1)
  103. #define INT_READ_OP_EN (1 << 0)
  104. enum mxcmci_type {
  105. IMX21_MMC,
  106. IMX31_MMC,
  107. MPC512X_MMC,
  108. };
  109. struct mxcmci_host {
  110. struct mmc_host *mmc;
  111. void __iomem *base;
  112. dma_addr_t phys_base;
  113. int detect_irq;
  114. struct dma_chan *dma;
  115. struct dma_async_tx_descriptor *desc;
  116. int do_dma;
  117. int default_irq_mask;
  118. int use_sdio;
  119. unsigned int power_mode;
  120. struct imxmmc_platform_data *pdata;
  121. struct mmc_request *req;
  122. struct mmc_command *cmd;
  123. struct mmc_data *data;
  124. unsigned int datasize;
  125. unsigned int dma_dir;
  126. u16 rev_no;
  127. unsigned int cmdat;
  128. struct clk *clk_ipg;
  129. struct clk *clk_per;
  130. int clock;
  131. struct work_struct datawork;
  132. spinlock_t lock;
  133. int burstlen;
  134. int dmareq;
  135. struct dma_slave_config dma_slave_config;
  136. struct imx_dma_data dma_data;
  137. struct timer_list watchdog;
  138. enum mxcmci_type devtype;
  139. };
  140. static const struct platform_device_id mxcmci_devtype[] = {
  141. {
  142. .name = "imx21-mmc",
  143. .driver_data = IMX21_MMC,
  144. }, {
  145. .name = "imx31-mmc",
  146. .driver_data = IMX31_MMC,
  147. }, {
  148. .name = "mpc512x-sdhc",
  149. .driver_data = MPC512X_MMC,
  150. }, {
  151. /* sentinel */
  152. }
  153. };
  154. MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
  155. static const struct of_device_id mxcmci_of_match[] = {
  156. {
  157. .compatible = "fsl,imx21-mmc",
  158. .data = &mxcmci_devtype[IMX21_MMC],
  159. }, {
  160. .compatible = "fsl,imx31-mmc",
  161. .data = &mxcmci_devtype[IMX31_MMC],
  162. }, {
  163. .compatible = "fsl,mpc5121-sdhc",
  164. .data = &mxcmci_devtype[MPC512X_MMC],
  165. }, {
  166. /* sentinel */
  167. }
  168. };
  169. MODULE_DEVICE_TABLE(of, mxcmci_of_match);
  170. static inline int is_imx31_mmc(struct mxcmci_host *host)
  171. {
  172. return host->devtype == IMX31_MMC;
  173. }
  174. static inline int is_mpc512x_mmc(struct mxcmci_host *host)
  175. {
  176. return host->devtype == MPC512X_MMC;
  177. }
  178. static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
  179. {
  180. if (IS_ENABLED(CONFIG_PPC_MPC512x))
  181. return ioread32be(host->base + reg);
  182. else
  183. return readl(host->base + reg);
  184. }
  185. static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
  186. {
  187. if (IS_ENABLED(CONFIG_PPC_MPC512x))
  188. iowrite32be(val, host->base + reg);
  189. else
  190. writel(val, host->base + reg);
  191. }
  192. static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
  193. {
  194. if (IS_ENABLED(CONFIG_PPC_MPC512x))
  195. return ioread32be(host->base + reg);
  196. else
  197. return readw(host->base + reg);
  198. }
  199. static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
  200. {
  201. if (IS_ENABLED(CONFIG_PPC_MPC512x))
  202. iowrite32be(val, host->base + reg);
  203. else
  204. writew(val, host->base + reg);
  205. }
  206. static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
  207. static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
  208. {
  209. if (!IS_ERR(host->mmc->supply.vmmc)) {
  210. if (host->power_mode == MMC_POWER_UP)
  211. mmc_regulator_set_ocr(host->mmc,
  212. host->mmc->supply.vmmc, vdd);
  213. else if (host->power_mode == MMC_POWER_OFF)
  214. mmc_regulator_set_ocr(host->mmc,
  215. host->mmc->supply.vmmc, 0);
  216. }
  217. if (host->pdata && host->pdata->setpower)
  218. host->pdata->setpower(mmc_dev(host->mmc), vdd);
  219. }
  220. static inline int mxcmci_use_dma(struct mxcmci_host *host)
  221. {
  222. return host->do_dma;
  223. }
  224. static void mxcmci_softreset(struct mxcmci_host *host)
  225. {
  226. int i;
  227. dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
  228. /* reset sequence */
  229. mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
  230. mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
  231. MMC_REG_STR_STP_CLK);
  232. for (i = 0; i < 8; i++)
  233. mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
  234. mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
  235. }
  236. #if IS_ENABLED(CONFIG_PPC_MPC512x)
  237. static inline void buffer_swap32(u32 *buf, int len)
  238. {
  239. int i;
  240. for (i = 0; i < ((len + 3) / 4); i++) {
  241. *buf = swab32(*buf);
  242. buf++;
  243. }
  244. }
  245. static void mxcmci_swap_buffers(struct mmc_data *data)
  246. {
  247. struct scatterlist *sg;
  248. int i;
  249. for_each_sg(data->sg, sg, data->sg_len, i)
  250. buffer_swap32(sg_virt(sg), sg->length);
  251. }
  252. #else
  253. static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
  254. #endif
  255. static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
  256. {
  257. unsigned int nob = data->blocks;
  258. unsigned int blksz = data->blksz;
  259. unsigned int datasize = nob * blksz;
  260. struct scatterlist *sg;
  261. enum dma_transfer_direction slave_dirn;
  262. int i, nents;
  263. host->data = data;
  264. data->bytes_xfered = 0;
  265. mxcmci_writew(host, nob, MMC_REG_NOB);
  266. mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
  267. host->datasize = datasize;
  268. if (!mxcmci_use_dma(host))
  269. return 0;
  270. for_each_sg(data->sg, sg, data->sg_len, i) {
  271. if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
  272. host->do_dma = 0;
  273. return 0;
  274. }
  275. }
  276. if (data->flags & MMC_DATA_READ) {
  277. host->dma_dir = DMA_FROM_DEVICE;
  278. slave_dirn = DMA_DEV_TO_MEM;
  279. } else {
  280. host->dma_dir = DMA_TO_DEVICE;
  281. slave_dirn = DMA_MEM_TO_DEV;
  282. mxcmci_swap_buffers(data);
  283. }
  284. nents = dma_map_sg(host->dma->device->dev, data->sg,
  285. data->sg_len, host->dma_dir);
  286. if (nents != data->sg_len)
  287. return -EINVAL;
  288. host->desc = dmaengine_prep_slave_sg(host->dma,
  289. data->sg, data->sg_len, slave_dirn,
  290. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  291. if (!host->desc) {
  292. dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
  293. host->dma_dir);
  294. host->do_dma = 0;
  295. return 0; /* Fall back to PIO */
  296. }
  297. wmb();
  298. dmaengine_submit(host->desc);
  299. dma_async_issue_pending(host->dma);
  300. mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
  301. return 0;
  302. }
  303. static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
  304. static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
  305. static void mxcmci_dma_callback(void *data)
  306. {
  307. struct mxcmci_host *host = data;
  308. u32 stat;
  309. del_timer(&host->watchdog);
  310. stat = mxcmci_readl(host, MMC_REG_STATUS);
  311. dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
  312. mxcmci_data_done(host, stat);
  313. }
  314. static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
  315. unsigned int cmdat)
  316. {
  317. u32 int_cntr = host->default_irq_mask;
  318. unsigned long flags;
  319. WARN_ON(host->cmd != NULL);
  320. host->cmd = cmd;
  321. switch (mmc_resp_type(cmd)) {
  322. case MMC_RSP_R1: /* short CRC, OPCODE */
  323. case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
  324. cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
  325. break;
  326. case MMC_RSP_R2: /* long 136 bit + CRC */
  327. cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
  328. break;
  329. case MMC_RSP_R3: /* short */
  330. cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
  331. break;
  332. case MMC_RSP_NONE:
  333. break;
  334. default:
  335. dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
  336. mmc_resp_type(cmd));
  337. cmd->error = -EINVAL;
  338. return -EINVAL;
  339. }
  340. int_cntr = INT_END_CMD_RES_EN;
  341. if (mxcmci_use_dma(host)) {
  342. if (host->dma_dir == DMA_FROM_DEVICE) {
  343. host->desc->callback = mxcmci_dma_callback;
  344. host->desc->callback_param = host;
  345. } else {
  346. int_cntr |= INT_WRITE_OP_DONE_EN;
  347. }
  348. }
  349. spin_lock_irqsave(&host->lock, flags);
  350. if (host->use_sdio)
  351. int_cntr |= INT_SDIO_IRQ_EN;
  352. mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
  353. spin_unlock_irqrestore(&host->lock, flags);
  354. mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
  355. mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
  356. mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
  357. return 0;
  358. }
  359. static void mxcmci_finish_request(struct mxcmci_host *host,
  360. struct mmc_request *req)
  361. {
  362. u32 int_cntr = host->default_irq_mask;
  363. unsigned long flags;
  364. spin_lock_irqsave(&host->lock, flags);
  365. if (host->use_sdio)
  366. int_cntr |= INT_SDIO_IRQ_EN;
  367. mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
  368. spin_unlock_irqrestore(&host->lock, flags);
  369. host->req = NULL;
  370. host->cmd = NULL;
  371. host->data = NULL;
  372. mmc_request_done(host->mmc, req);
  373. }
  374. static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
  375. {
  376. struct mmc_data *data = host->data;
  377. int data_error;
  378. if (mxcmci_use_dma(host)) {
  379. dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
  380. host->dma_dir);
  381. mxcmci_swap_buffers(data);
  382. }
  383. if (stat & STATUS_ERR_MASK) {
  384. dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
  385. stat);
  386. if (stat & STATUS_CRC_READ_ERR) {
  387. dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
  388. data->error = -EILSEQ;
  389. } else if (stat & STATUS_CRC_WRITE_ERR) {
  390. u32 err_code = (stat >> 9) & 0x3;
  391. if (err_code == 2) { /* No CRC response */
  392. dev_err(mmc_dev(host->mmc),
  393. "%s: No CRC -ETIMEDOUT\n", __func__);
  394. data->error = -ETIMEDOUT;
  395. } else {
  396. dev_err(mmc_dev(host->mmc),
  397. "%s: -EILSEQ\n", __func__);
  398. data->error = -EILSEQ;
  399. }
  400. } else if (stat & STATUS_TIME_OUT_READ) {
  401. dev_err(mmc_dev(host->mmc),
  402. "%s: read -ETIMEDOUT\n", __func__);
  403. data->error = -ETIMEDOUT;
  404. } else {
  405. dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
  406. data->error = -EIO;
  407. }
  408. } else {
  409. data->bytes_xfered = host->datasize;
  410. }
  411. data_error = data->error;
  412. host->data = NULL;
  413. return data_error;
  414. }
  415. static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
  416. {
  417. struct mmc_command *cmd = host->cmd;
  418. int i;
  419. u32 a, b, c;
  420. if (!cmd)
  421. return;
  422. if (stat & STATUS_TIME_OUT_RESP) {
  423. dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
  424. cmd->error = -ETIMEDOUT;
  425. } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
  426. dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
  427. cmd->error = -EILSEQ;
  428. }
  429. if (cmd->flags & MMC_RSP_PRESENT) {
  430. if (cmd->flags & MMC_RSP_136) {
  431. for (i = 0; i < 4; i++) {
  432. a = mxcmci_readw(host, MMC_REG_RES_FIFO);
  433. b = mxcmci_readw(host, MMC_REG_RES_FIFO);
  434. cmd->resp[i] = a << 16 | b;
  435. }
  436. } else {
  437. a = mxcmci_readw(host, MMC_REG_RES_FIFO);
  438. b = mxcmci_readw(host, MMC_REG_RES_FIFO);
  439. c = mxcmci_readw(host, MMC_REG_RES_FIFO);
  440. cmd->resp[0] = a << 24 | b << 8 | c >> 8;
  441. }
  442. }
  443. }
  444. static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
  445. {
  446. u32 stat;
  447. unsigned long timeout = jiffies + HZ;
  448. do {
  449. stat = mxcmci_readl(host, MMC_REG_STATUS);
  450. if (stat & STATUS_ERR_MASK)
  451. return stat;
  452. if (time_after(jiffies, timeout)) {
  453. mxcmci_softreset(host);
  454. mxcmci_set_clk_rate(host, host->clock);
  455. return STATUS_TIME_OUT_READ;
  456. }
  457. if (stat & mask)
  458. return 0;
  459. cpu_relax();
  460. } while (1);
  461. }
  462. static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
  463. {
  464. unsigned int stat;
  465. u32 *buf = _buf;
  466. while (bytes > 3) {
  467. stat = mxcmci_poll_status(host,
  468. STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
  469. if (stat)
  470. return stat;
  471. *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
  472. bytes -= 4;
  473. }
  474. if (bytes) {
  475. u8 *b = (u8 *)buf;
  476. u32 tmp;
  477. stat = mxcmci_poll_status(host,
  478. STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
  479. if (stat)
  480. return stat;
  481. tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
  482. memcpy(b, &tmp, bytes);
  483. }
  484. return 0;
  485. }
  486. static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
  487. {
  488. unsigned int stat;
  489. u32 *buf = _buf;
  490. while (bytes > 3) {
  491. stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  492. if (stat)
  493. return stat;
  494. mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
  495. bytes -= 4;
  496. }
  497. if (bytes) {
  498. u8 *b = (u8 *)buf;
  499. u32 tmp;
  500. stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  501. if (stat)
  502. return stat;
  503. memcpy(&tmp, b, bytes);
  504. mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
  505. }
  506. return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  507. }
  508. static int mxcmci_transfer_data(struct mxcmci_host *host)
  509. {
  510. struct mmc_data *data = host->req->data;
  511. struct scatterlist *sg;
  512. int stat, i;
  513. host->data = data;
  514. host->datasize = 0;
  515. if (data->flags & MMC_DATA_READ) {
  516. for_each_sg(data->sg, sg, data->sg_len, i) {
  517. stat = mxcmci_pull(host, sg_virt(sg), sg->length);
  518. if (stat)
  519. return stat;
  520. host->datasize += sg->length;
  521. }
  522. } else {
  523. for_each_sg(data->sg, sg, data->sg_len, i) {
  524. stat = mxcmci_push(host, sg_virt(sg), sg->length);
  525. if (stat)
  526. return stat;
  527. host->datasize += sg->length;
  528. }
  529. stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
  530. if (stat)
  531. return stat;
  532. }
  533. return 0;
  534. }
  535. static void mxcmci_datawork(struct work_struct *work)
  536. {
  537. struct mxcmci_host *host = container_of(work, struct mxcmci_host,
  538. datawork);
  539. int datastat = mxcmci_transfer_data(host);
  540. mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
  541. MMC_REG_STATUS);
  542. mxcmci_finish_data(host, datastat);
  543. if (host->req->stop) {
  544. if (mxcmci_start_cmd(host, host->req->stop, 0)) {
  545. mxcmci_finish_request(host, host->req);
  546. return;
  547. }
  548. } else {
  549. mxcmci_finish_request(host, host->req);
  550. }
  551. }
  552. static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
  553. {
  554. struct mmc_request *req;
  555. int data_error;
  556. unsigned long flags;
  557. spin_lock_irqsave(&host->lock, flags);
  558. if (!host->data) {
  559. spin_unlock_irqrestore(&host->lock, flags);
  560. return;
  561. }
  562. if (!host->req) {
  563. spin_unlock_irqrestore(&host->lock, flags);
  564. return;
  565. }
  566. req = host->req;
  567. if (!req->stop)
  568. host->req = NULL; /* we will handle finish req below */
  569. data_error = mxcmci_finish_data(host, stat);
  570. spin_unlock_irqrestore(&host->lock, flags);
  571. if (data_error)
  572. return;
  573. mxcmci_read_response(host, stat);
  574. host->cmd = NULL;
  575. if (req->stop) {
  576. if (mxcmci_start_cmd(host, req->stop, 0)) {
  577. mxcmci_finish_request(host, req);
  578. return;
  579. }
  580. } else {
  581. mxcmci_finish_request(host, req);
  582. }
  583. }
  584. static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
  585. {
  586. mxcmci_read_response(host, stat);
  587. host->cmd = NULL;
  588. if (!host->data && host->req) {
  589. mxcmci_finish_request(host, host->req);
  590. return;
  591. }
  592. /* For the DMA case the DMA engine handles the data transfer
  593. * automatically. For non DMA we have to do it ourselves.
  594. * Don't do it in interrupt context though.
  595. */
  596. if (!mxcmci_use_dma(host) && host->data)
  597. schedule_work(&host->datawork);
  598. }
  599. static irqreturn_t mxcmci_irq(int irq, void *devid)
  600. {
  601. struct mxcmci_host *host = devid;
  602. bool sdio_irq;
  603. u32 stat;
  604. stat = mxcmci_readl(host, MMC_REG_STATUS);
  605. mxcmci_writel(host,
  606. stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
  607. STATUS_WRITE_OP_DONE),
  608. MMC_REG_STATUS);
  609. dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
  610. spin_lock(&host->lock);
  611. sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
  612. spin_unlock(&host->lock);
  613. if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
  614. mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
  615. if (sdio_irq) {
  616. mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
  617. mmc_signal_sdio_irq(host->mmc);
  618. }
  619. if (stat & STATUS_END_CMD_RESP)
  620. mxcmci_cmd_done(host, stat);
  621. if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
  622. del_timer(&host->watchdog);
  623. mxcmci_data_done(host, stat);
  624. }
  625. if (host->default_irq_mask &&
  626. (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
  627. mmc_detect_change(host->mmc, msecs_to_jiffies(200));
  628. return IRQ_HANDLED;
  629. }
  630. static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
  631. {
  632. struct mxcmci_host *host = mmc_priv(mmc);
  633. unsigned int cmdat = host->cmdat;
  634. int error;
  635. WARN_ON(host->req != NULL);
  636. host->req = req;
  637. host->cmdat &= ~CMD_DAT_CONT_INIT;
  638. if (host->dma)
  639. host->do_dma = 1;
  640. if (req->data) {
  641. error = mxcmci_setup_data(host, req->data);
  642. if (error) {
  643. req->cmd->error = error;
  644. goto out;
  645. }
  646. cmdat |= CMD_DAT_CONT_DATA_ENABLE;
  647. if (req->data->flags & MMC_DATA_WRITE)
  648. cmdat |= CMD_DAT_CONT_WRITE;
  649. }
  650. error = mxcmci_start_cmd(host, req->cmd, cmdat);
  651. out:
  652. if (error)
  653. mxcmci_finish_request(host, req);
  654. }
  655. static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
  656. {
  657. unsigned int divider;
  658. int prescaler = 0;
  659. unsigned int clk_in = clk_get_rate(host->clk_per);
  660. while (prescaler <= 0x800) {
  661. for (divider = 1; divider <= 0xF; divider++) {
  662. int x;
  663. x = (clk_in / (divider + 1));
  664. if (prescaler)
  665. x /= (prescaler * 2);
  666. if (x <= clk_ios)
  667. break;
  668. }
  669. if (divider < 0x10)
  670. break;
  671. if (prescaler == 0)
  672. prescaler = 1;
  673. else
  674. prescaler <<= 1;
  675. }
  676. mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
  677. dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
  678. prescaler, divider, clk_in, clk_ios);
  679. }
  680. static int mxcmci_setup_dma(struct mmc_host *mmc)
  681. {
  682. struct mxcmci_host *host = mmc_priv(mmc);
  683. struct dma_slave_config *config = &host->dma_slave_config;
  684. config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
  685. config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
  686. config->dst_addr_width = 4;
  687. config->src_addr_width = 4;
  688. config->dst_maxburst = host->burstlen;
  689. config->src_maxburst = host->burstlen;
  690. config->device_fc = false;
  691. return dmaengine_slave_config(host->dma, config);
  692. }
  693. static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  694. {
  695. struct mxcmci_host *host = mmc_priv(mmc);
  696. int burstlen, ret;
  697. /*
  698. * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
  699. * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
  700. */
  701. if (ios->bus_width == MMC_BUS_WIDTH_4)
  702. burstlen = 16;
  703. else
  704. burstlen = 4;
  705. if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
  706. host->burstlen = burstlen;
  707. ret = mxcmci_setup_dma(mmc);
  708. if (ret) {
  709. dev_err(mmc_dev(host->mmc),
  710. "failed to config DMA channel. Falling back to PIO\n");
  711. dma_release_channel(host->dma);
  712. host->do_dma = 0;
  713. host->dma = NULL;
  714. }
  715. }
  716. if (ios->bus_width == MMC_BUS_WIDTH_4)
  717. host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
  718. else
  719. host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
  720. if (host->power_mode != ios->power_mode) {
  721. host->power_mode = ios->power_mode;
  722. mxcmci_set_power(host, ios->vdd);
  723. if (ios->power_mode == MMC_POWER_ON)
  724. host->cmdat |= CMD_DAT_CONT_INIT;
  725. }
  726. if (ios->clock) {
  727. mxcmci_set_clk_rate(host, ios->clock);
  728. mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
  729. } else {
  730. mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
  731. }
  732. host->clock = ios->clock;
  733. }
  734. static irqreturn_t mxcmci_detect_irq(int irq, void *data)
  735. {
  736. struct mmc_host *mmc = data;
  737. dev_dbg(mmc_dev(mmc), "%s\n", __func__);
  738. mmc_detect_change(mmc, msecs_to_jiffies(250));
  739. return IRQ_HANDLED;
  740. }
  741. static int mxcmci_get_ro(struct mmc_host *mmc)
  742. {
  743. struct mxcmci_host *host = mmc_priv(mmc);
  744. if (host->pdata && host->pdata->get_ro)
  745. return !!host->pdata->get_ro(mmc_dev(mmc));
  746. /*
  747. * If board doesn't support read only detection (no mmc_gpio
  748. * context or gpio is invalid), then let the mmc core decide
  749. * what to do.
  750. */
  751. return mmc_gpio_get_ro(mmc);
  752. }
  753. static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
  754. {
  755. struct mxcmci_host *host = mmc_priv(mmc);
  756. unsigned long flags;
  757. u32 int_cntr;
  758. spin_lock_irqsave(&host->lock, flags);
  759. host->use_sdio = enable;
  760. int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
  761. if (enable)
  762. int_cntr |= INT_SDIO_IRQ_EN;
  763. else
  764. int_cntr &= ~INT_SDIO_IRQ_EN;
  765. mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
  766. spin_unlock_irqrestore(&host->lock, flags);
  767. }
  768. static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
  769. {
  770. struct mxcmci_host *mxcmci = mmc_priv(host);
  771. /*
  772. * MX3 SoCs have a silicon bug which corrupts CRC calculation of
  773. * multi-block transfers when connected SDIO peripheral doesn't
  774. * drive the BUSY line as required by the specs.
  775. * One way to prevent this is to only allow 1-bit transfers.
  776. */
  777. if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
  778. host->caps &= ~MMC_CAP_4_BIT_DATA;
  779. else
  780. host->caps |= MMC_CAP_4_BIT_DATA;
  781. }
  782. static bool filter(struct dma_chan *chan, void *param)
  783. {
  784. struct mxcmci_host *host = param;
  785. if (!imx_dma_is_general_purpose(chan))
  786. return false;
  787. chan->private = &host->dma_data;
  788. return true;
  789. }
  790. static void mxcmci_watchdog(struct timer_list *t)
  791. {
  792. struct mxcmci_host *host = from_timer(host, t, watchdog);
  793. struct mmc_request *req = host->req;
  794. unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
  795. if (host->dma_dir == DMA_FROM_DEVICE) {
  796. dmaengine_terminate_all(host->dma);
  797. dev_err(mmc_dev(host->mmc),
  798. "%s: read time out (status = 0x%08x)\n",
  799. __func__, stat);
  800. } else {
  801. dev_err(mmc_dev(host->mmc),
  802. "%s: write time out (status = 0x%08x)\n",
  803. __func__, stat);
  804. mxcmci_softreset(host);
  805. }
  806. /* Mark transfer as erroneus and inform the upper layers */
  807. if (host->data)
  808. host->data->error = -ETIMEDOUT;
  809. host->req = NULL;
  810. host->cmd = NULL;
  811. host->data = NULL;
  812. mmc_request_done(host->mmc, req);
  813. }
  814. static const struct mmc_host_ops mxcmci_ops = {
  815. .request = mxcmci_request,
  816. .set_ios = mxcmci_set_ios,
  817. .get_ro = mxcmci_get_ro,
  818. .enable_sdio_irq = mxcmci_enable_sdio_irq,
  819. .init_card = mxcmci_init_card,
  820. };
  821. static int mxcmci_probe(struct platform_device *pdev)
  822. {
  823. struct mmc_host *mmc;
  824. struct mxcmci_host *host;
  825. struct resource *res;
  826. int ret = 0, irq;
  827. bool dat3_card_detect = false;
  828. dma_cap_mask_t mask;
  829. const struct of_device_id *of_id;
  830. struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
  831. pr_info("i.MX/MPC512x SDHC driver\n");
  832. of_id = of_match_device(mxcmci_of_match, &pdev->dev);
  833. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  834. irq = platform_get_irq(pdev, 0);
  835. if (irq < 0)
  836. return irq;
  837. mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
  838. if (!mmc)
  839. return -ENOMEM;
  840. host = mmc_priv(mmc);
  841. host->base = devm_ioremap_resource(&pdev->dev, res);
  842. if (IS_ERR(host->base)) {
  843. ret = PTR_ERR(host->base);
  844. goto out_free;
  845. }
  846. host->phys_base = res->start;
  847. ret = mmc_of_parse(mmc);
  848. if (ret)
  849. goto out_free;
  850. mmc->ops = &mxcmci_ops;
  851. /* For devicetree parsing, the bus width is read from devicetree */
  852. if (pdata)
  853. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  854. else
  855. mmc->caps |= MMC_CAP_SDIO_IRQ;
  856. /* MMC core transfer sizes tunable parameters */
  857. mmc->max_blk_size = 2048;
  858. mmc->max_blk_count = 65535;
  859. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  860. mmc->max_seg_size = mmc->max_req_size;
  861. if (of_id) {
  862. const struct platform_device_id *id_entry = of_id->data;
  863. host->devtype = id_entry->driver_data;
  864. } else {
  865. host->devtype = pdev->id_entry->driver_data;
  866. }
  867. /* adjust max_segs after devtype detection */
  868. if (!is_mpc512x_mmc(host))
  869. mmc->max_segs = 64;
  870. host->mmc = mmc;
  871. host->pdata = pdata;
  872. spin_lock_init(&host->lock);
  873. if (pdata)
  874. dat3_card_detect = pdata->dat3_card_detect;
  875. else if (mmc_card_is_removable(mmc)
  876. && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
  877. dat3_card_detect = true;
  878. ret = mmc_regulator_get_supply(mmc);
  879. if (ret)
  880. goto out_free;
  881. if (!mmc->ocr_avail) {
  882. if (pdata && pdata->ocr_avail)
  883. mmc->ocr_avail = pdata->ocr_avail;
  884. else
  885. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  886. }
  887. if (dat3_card_detect)
  888. host->default_irq_mask =
  889. INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
  890. else
  891. host->default_irq_mask = 0;
  892. host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  893. if (IS_ERR(host->clk_ipg)) {
  894. ret = PTR_ERR(host->clk_ipg);
  895. goto out_free;
  896. }
  897. host->clk_per = devm_clk_get(&pdev->dev, "per");
  898. if (IS_ERR(host->clk_per)) {
  899. ret = PTR_ERR(host->clk_per);
  900. goto out_free;
  901. }
  902. ret = clk_prepare_enable(host->clk_per);
  903. if (ret)
  904. goto out_free;
  905. ret = clk_prepare_enable(host->clk_ipg);
  906. if (ret)
  907. goto out_clk_per_put;
  908. mxcmci_softreset(host);
  909. host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
  910. if (host->rev_no != 0x400) {
  911. ret = -ENODEV;
  912. dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
  913. host->rev_no);
  914. goto out_clk_put;
  915. }
  916. mmc->f_min = clk_get_rate(host->clk_per) >> 16;
  917. mmc->f_max = clk_get_rate(host->clk_per) >> 1;
  918. /* recommended in data sheet */
  919. mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
  920. mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
  921. if (!host->pdata) {
  922. host->dma = dma_request_chan(&pdev->dev, "rx-tx");
  923. if (IS_ERR(host->dma)) {
  924. if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
  925. ret = -EPROBE_DEFER;
  926. goto out_clk_put;
  927. }
  928. /* Ignore errors to fall back to PIO mode */
  929. host->dma = NULL;
  930. }
  931. } else {
  932. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  933. if (res) {
  934. host->dmareq = res->start;
  935. host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
  936. host->dma_data.priority = DMA_PRIO_LOW;
  937. host->dma_data.dma_request = host->dmareq;
  938. dma_cap_zero(mask);
  939. dma_cap_set(DMA_SLAVE, mask);
  940. host->dma = dma_request_channel(mask, filter, host);
  941. }
  942. }
  943. if (host->dma)
  944. mmc->max_seg_size = dma_get_max_seg_size(
  945. host->dma->device->dev);
  946. else
  947. dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
  948. INIT_WORK(&host->datawork, mxcmci_datawork);
  949. ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
  950. dev_name(&pdev->dev), host);
  951. if (ret)
  952. goto out_free_dma;
  953. platform_set_drvdata(pdev, mmc);
  954. if (host->pdata && host->pdata->init) {
  955. ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
  956. host->mmc);
  957. if (ret)
  958. goto out_free_dma;
  959. }
  960. timer_setup(&host->watchdog, mxcmci_watchdog, 0);
  961. mmc_add_host(mmc);
  962. return 0;
  963. out_free_dma:
  964. if (host->dma)
  965. dma_release_channel(host->dma);
  966. out_clk_put:
  967. clk_disable_unprepare(host->clk_ipg);
  968. out_clk_per_put:
  969. clk_disable_unprepare(host->clk_per);
  970. out_free:
  971. mmc_free_host(mmc);
  972. return ret;
  973. }
  974. static int mxcmci_remove(struct platform_device *pdev)
  975. {
  976. struct mmc_host *mmc = platform_get_drvdata(pdev);
  977. struct mxcmci_host *host = mmc_priv(mmc);
  978. mmc_remove_host(mmc);
  979. if (host->pdata && host->pdata->exit)
  980. host->pdata->exit(&pdev->dev, mmc);
  981. if (host->dma)
  982. dma_release_channel(host->dma);
  983. clk_disable_unprepare(host->clk_per);
  984. clk_disable_unprepare(host->clk_ipg);
  985. mmc_free_host(mmc);
  986. return 0;
  987. }
  988. #ifdef CONFIG_PM_SLEEP
  989. static int mxcmci_suspend(struct device *dev)
  990. {
  991. struct mmc_host *mmc = dev_get_drvdata(dev);
  992. struct mxcmci_host *host = mmc_priv(mmc);
  993. clk_disable_unprepare(host->clk_per);
  994. clk_disable_unprepare(host->clk_ipg);
  995. return 0;
  996. }
  997. static int mxcmci_resume(struct device *dev)
  998. {
  999. struct mmc_host *mmc = dev_get_drvdata(dev);
  1000. struct mxcmci_host *host = mmc_priv(mmc);
  1001. int ret;
  1002. ret = clk_prepare_enable(host->clk_per);
  1003. if (ret)
  1004. return ret;
  1005. ret = clk_prepare_enable(host->clk_ipg);
  1006. if (ret)
  1007. clk_disable_unprepare(host->clk_per);
  1008. return ret;
  1009. }
  1010. #endif
  1011. static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
  1012. static struct platform_driver mxcmci_driver = {
  1013. .probe = mxcmci_probe,
  1014. .remove = mxcmci_remove,
  1015. .id_table = mxcmci_devtype,
  1016. .driver = {
  1017. .name = DRIVER_NAME,
  1018. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1019. .pm = &mxcmci_pm_ops,
  1020. .of_match_table = mxcmci_of_match,
  1021. }
  1022. };
  1023. module_platform_driver(mxcmci_driver);
  1024. MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
  1025. MODULE_AUTHOR("Sascha Hauer, Pengutronix");
  1026. MODULE_LICENSE("GPL");
  1027. MODULE_ALIAS("platform:mxc-mmc");