mtk-sd.c 79 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2015 MediaTek Inc.
  4. * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
  5. */
  6. #include <linux/module.h>
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/ioport.h>
  12. #include <linux/irq.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/pinctrl/consumer.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/reset.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/mmc/core.h>
  28. #include <linux/mmc/host.h>
  29. #include <linux/mmc/mmc.h>
  30. #include <linux/mmc/sd.h>
  31. #include <linux/mmc/sdio.h>
  32. #include <linux/mmc/slot-gpio.h>
  33. #include "cqhci.h"
  34. #define MAX_BD_NUM 1024
  35. /*--------------------------------------------------------------------------*/
  36. /* Common Definition */
  37. /*--------------------------------------------------------------------------*/
  38. #define MSDC_BUS_1BITS 0x0
  39. #define MSDC_BUS_4BITS 0x1
  40. #define MSDC_BUS_8BITS 0x2
  41. #define MSDC_BURST_64B 0x6
  42. /*--------------------------------------------------------------------------*/
  43. /* Register Offset */
  44. /*--------------------------------------------------------------------------*/
  45. #define MSDC_CFG 0x0
  46. #define MSDC_IOCON 0x04
  47. #define MSDC_PS 0x08
  48. #define MSDC_INT 0x0c
  49. #define MSDC_INTEN 0x10
  50. #define MSDC_FIFOCS 0x14
  51. #define SDC_CFG 0x30
  52. #define SDC_CMD 0x34
  53. #define SDC_ARG 0x38
  54. #define SDC_STS 0x3c
  55. #define SDC_RESP0 0x40
  56. #define SDC_RESP1 0x44
  57. #define SDC_RESP2 0x48
  58. #define SDC_RESP3 0x4c
  59. #define SDC_BLK_NUM 0x50
  60. #define SDC_ADV_CFG0 0x64
  61. #define EMMC_IOCON 0x7c
  62. #define SDC_ACMD_RESP 0x80
  63. #define DMA_SA_H4BIT 0x8c
  64. #define MSDC_DMA_SA 0x90
  65. #define MSDC_DMA_CTRL 0x98
  66. #define MSDC_DMA_CFG 0x9c
  67. #define MSDC_PATCH_BIT 0xb0
  68. #define MSDC_PATCH_BIT1 0xb4
  69. #define MSDC_PATCH_BIT2 0xb8
  70. #define MSDC_PAD_TUNE 0xec
  71. #define MSDC_PAD_TUNE0 0xf0
  72. #define PAD_DS_TUNE 0x188
  73. #define PAD_CMD_TUNE 0x18c
  74. #define EMMC50_CFG0 0x208
  75. #define EMMC50_CFG3 0x220
  76. #define SDC_FIFO_CFG 0x228
  77. /*--------------------------------------------------------------------------*/
  78. /* Top Pad Register Offset */
  79. /*--------------------------------------------------------------------------*/
  80. #define EMMC_TOP_CONTROL 0x00
  81. #define EMMC_TOP_CMD 0x04
  82. #define EMMC50_PAD_DS_TUNE 0x0c
  83. /*--------------------------------------------------------------------------*/
  84. /* Register Mask */
  85. /*--------------------------------------------------------------------------*/
  86. /* MSDC_CFG mask */
  87. #define MSDC_CFG_MODE (0x1 << 0) /* RW */
  88. #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
  89. #define MSDC_CFG_RST (0x1 << 2) /* RW */
  90. #define MSDC_CFG_PIO (0x1 << 3) /* RW */
  91. #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
  92. #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
  93. #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
  94. #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
  95. #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
  96. #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
  97. #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
  98. #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
  99. #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
  100. #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
  101. /* MSDC_IOCON mask */
  102. #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
  103. #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
  104. #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
  105. #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
  106. #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
  107. #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
  108. #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
  109. #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
  110. #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
  111. #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
  112. #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
  113. #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
  114. #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
  115. #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
  116. #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
  117. #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
  118. /* MSDC_PS mask */
  119. #define MSDC_PS_CDEN (0x1 << 0) /* RW */
  120. #define MSDC_PS_CDSTS (0x1 << 1) /* R */
  121. #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
  122. #define MSDC_PS_DAT (0xff << 16) /* R */
  123. #define MSDC_PS_DATA1 (0x1 << 17) /* R */
  124. #define MSDC_PS_CMD (0x1 << 24) /* R */
  125. #define MSDC_PS_WP (0x1 << 31) /* R */
  126. /* MSDC_INT mask */
  127. #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
  128. #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
  129. #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
  130. #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
  131. #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
  132. #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
  133. #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
  134. #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
  135. #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
  136. #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
  137. #define MSDC_INT_CSTA (0x1 << 11) /* R */
  138. #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
  139. #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
  140. #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
  141. #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
  142. #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
  143. #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
  144. #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
  145. #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
  146. #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
  147. /* MSDC_INTEN mask */
  148. #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
  149. #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
  150. #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
  151. #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
  152. #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
  153. #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
  154. #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
  155. #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
  156. #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
  157. #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
  158. #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
  159. #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
  160. #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
  161. #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
  162. #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
  163. #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
  164. #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
  165. #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
  166. #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
  167. /* MSDC_FIFOCS mask */
  168. #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
  169. #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
  170. #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
  171. /* SDC_CFG mask */
  172. #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
  173. #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
  174. #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
  175. #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
  176. #define SDC_CFG_SDIO (0x1 << 19) /* RW */
  177. #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
  178. #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
  179. #define SDC_CFG_DTOC (0xff << 24) /* RW */
  180. /* SDC_STS mask */
  181. #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
  182. #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
  183. #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
  184. #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
  185. /* SDC_ADV_CFG0 mask */
  186. #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
  187. /* DMA_SA_H4BIT mask */
  188. #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
  189. /* MSDC_DMA_CTRL mask */
  190. #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
  191. #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
  192. #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
  193. #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
  194. #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
  195. #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
  196. /* MSDC_DMA_CFG mask */
  197. #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
  198. #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
  199. #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
  200. #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
  201. #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
  202. /* MSDC_PATCH_BIT mask */
  203. #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
  204. #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
  205. #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
  206. #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
  207. #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
  208. #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
  209. #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
  210. #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
  211. #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
  212. #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
  213. #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
  214. #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
  215. #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
  216. #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
  217. #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
  218. #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
  219. #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
  220. #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
  221. #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
  222. #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
  223. #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
  224. #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
  225. #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
  226. #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
  227. #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
  228. #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
  229. #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
  230. #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
  231. #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
  232. #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
  233. #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
  234. #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
  235. #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
  236. #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
  237. #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
  238. #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
  239. #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
  240. #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
  241. #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
  242. /* EMMC_TOP_CONTROL mask */
  243. #define PAD_RXDLY_SEL (0x1 << 0) /* RW */
  244. #define DELAY_EN (0x1 << 1) /* RW */
  245. #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
  246. #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
  247. #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
  248. #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
  249. #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
  250. #define SDC_RX_ENH_EN (0x1 << 15) /* TW */
  251. /* EMMC_TOP_CMD mask */
  252. #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
  253. #define PAD_CMD_RXDLY (0x1f << 5) /* RW */
  254. #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
  255. #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
  256. #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
  257. #define REQ_CMD_EIO (0x1 << 0)
  258. #define REQ_CMD_TMO (0x1 << 1)
  259. #define REQ_DAT_ERR (0x1 << 2)
  260. #define REQ_STOP_EIO (0x1 << 3)
  261. #define REQ_STOP_TMO (0x1 << 4)
  262. #define REQ_CMD_BUSY (0x1 << 5)
  263. #define MSDC_PREPARE_FLAG (0x1 << 0)
  264. #define MSDC_ASYNC_FLAG (0x1 << 1)
  265. #define MSDC_MMAP_FLAG (0x1 << 2)
  266. #define MTK_MMC_AUTOSUSPEND_DELAY 50
  267. #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
  268. #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
  269. #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
  270. #define PAD_DELAY_MAX 32 /* PAD delay cells */
  271. /*--------------------------------------------------------------------------*/
  272. /* Descriptor Structure */
  273. /*--------------------------------------------------------------------------*/
  274. struct mt_gpdma_desc {
  275. u32 gpd_info;
  276. #define GPDMA_DESC_HWO (0x1 << 0)
  277. #define GPDMA_DESC_BDP (0x1 << 1)
  278. #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
  279. #define GPDMA_DESC_INT (0x1 << 16)
  280. #define GPDMA_DESC_NEXT_H4 (0xf << 24)
  281. #define GPDMA_DESC_PTR_H4 (0xf << 28)
  282. u32 next;
  283. u32 ptr;
  284. u32 gpd_data_len;
  285. #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
  286. #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
  287. u32 arg;
  288. u32 blknum;
  289. u32 cmd;
  290. };
  291. struct mt_bdma_desc {
  292. u32 bd_info;
  293. #define BDMA_DESC_EOL (0x1 << 0)
  294. #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
  295. #define BDMA_DESC_BLKPAD (0x1 << 17)
  296. #define BDMA_DESC_DWPAD (0x1 << 18)
  297. #define BDMA_DESC_NEXT_H4 (0xf << 24)
  298. #define BDMA_DESC_PTR_H4 (0xf << 28)
  299. u32 next;
  300. u32 ptr;
  301. u32 bd_data_len;
  302. #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
  303. #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */
  304. };
  305. struct msdc_dma {
  306. struct scatterlist *sg; /* I/O scatter list */
  307. struct mt_gpdma_desc *gpd; /* pointer to gpd array */
  308. struct mt_bdma_desc *bd; /* pointer to bd array */
  309. dma_addr_t gpd_addr; /* the physical address of gpd array */
  310. dma_addr_t bd_addr; /* the physical address of bd array */
  311. };
  312. struct msdc_save_para {
  313. u32 msdc_cfg;
  314. u32 iocon;
  315. u32 sdc_cfg;
  316. u32 pad_tune;
  317. u32 patch_bit0;
  318. u32 patch_bit1;
  319. u32 patch_bit2;
  320. u32 pad_ds_tune;
  321. u32 pad_cmd_tune;
  322. u32 emmc50_cfg0;
  323. u32 emmc50_cfg3;
  324. u32 sdc_fifo_cfg;
  325. u32 emmc_top_control;
  326. u32 emmc_top_cmd;
  327. u32 emmc50_pad_ds_tune;
  328. };
  329. struct mtk_mmc_compatible {
  330. u8 clk_div_bits;
  331. bool recheck_sdio_irq;
  332. bool hs400_tune; /* only used for MT8173 */
  333. u32 pad_tune_reg;
  334. bool async_fifo;
  335. bool data_tune;
  336. bool busy_check;
  337. bool stop_clk_fix;
  338. bool enhance_rx;
  339. bool support_64g;
  340. bool use_internal_cd;
  341. };
  342. struct msdc_tune_para {
  343. u32 iocon;
  344. u32 pad_tune;
  345. u32 pad_cmd_tune;
  346. u32 emmc_top_control;
  347. u32 emmc_top_cmd;
  348. };
  349. struct msdc_delay_phase {
  350. u8 maxlen;
  351. u8 start;
  352. u8 final_phase;
  353. };
  354. struct msdc_host {
  355. struct device *dev;
  356. const struct mtk_mmc_compatible *dev_comp;
  357. int cmd_rsp;
  358. spinlock_t lock;
  359. struct mmc_request *mrq;
  360. struct mmc_command *cmd;
  361. struct mmc_data *data;
  362. int error;
  363. void __iomem *base; /* host base address */
  364. void __iomem *top_base; /* host top register base address */
  365. struct msdc_dma dma; /* dma channel */
  366. u64 dma_mask;
  367. u32 timeout_ns; /* data timeout ns */
  368. u32 timeout_clks; /* data timeout clks */
  369. struct pinctrl *pinctrl;
  370. struct pinctrl_state *pins_default;
  371. struct pinctrl_state *pins_uhs;
  372. struct delayed_work req_timeout;
  373. int irq; /* host interrupt */
  374. struct reset_control *reset;
  375. struct clk *src_clk; /* msdc source clock */
  376. struct clk *h_clk; /* msdc h_clk */
  377. struct clk *bus_clk; /* bus clock which used to access register */
  378. struct clk *src_clk_cg; /* msdc source clock control gate */
  379. u32 mclk; /* mmc subsystem clock frequency */
  380. u32 src_clk_freq; /* source clock frequency */
  381. unsigned char timing;
  382. bool vqmmc_enabled;
  383. u32 latch_ck;
  384. u32 hs400_ds_delay;
  385. u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
  386. u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
  387. bool hs400_cmd_resp_sel_rising;
  388. /* cmd response sample selection for HS400 */
  389. bool hs400_mode; /* current eMMC will run at hs400 mode */
  390. bool internal_cd; /* Use internal card-detect logic */
  391. bool cqhci; /* support eMMC hw cmdq */
  392. struct msdc_save_para save_para; /* used when gate HCLK */
  393. struct msdc_tune_para def_tune_para; /* default tune setting */
  394. struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
  395. struct cqhci_host *cq_host;
  396. };
  397. static const struct mtk_mmc_compatible mt8135_compat = {
  398. .clk_div_bits = 8,
  399. .recheck_sdio_irq = true,
  400. .hs400_tune = false,
  401. .pad_tune_reg = MSDC_PAD_TUNE,
  402. .async_fifo = false,
  403. .data_tune = false,
  404. .busy_check = false,
  405. .stop_clk_fix = false,
  406. .enhance_rx = false,
  407. .support_64g = false,
  408. };
  409. static const struct mtk_mmc_compatible mt8173_compat = {
  410. .clk_div_bits = 8,
  411. .recheck_sdio_irq = true,
  412. .hs400_tune = true,
  413. .pad_tune_reg = MSDC_PAD_TUNE,
  414. .async_fifo = false,
  415. .data_tune = false,
  416. .busy_check = false,
  417. .stop_clk_fix = false,
  418. .enhance_rx = false,
  419. .support_64g = false,
  420. };
  421. static const struct mtk_mmc_compatible mt8183_compat = {
  422. .clk_div_bits = 12,
  423. .recheck_sdio_irq = false,
  424. .hs400_tune = false,
  425. .pad_tune_reg = MSDC_PAD_TUNE0,
  426. .async_fifo = true,
  427. .data_tune = true,
  428. .busy_check = true,
  429. .stop_clk_fix = true,
  430. .enhance_rx = true,
  431. .support_64g = true,
  432. };
  433. static const struct mtk_mmc_compatible mt2701_compat = {
  434. .clk_div_bits = 12,
  435. .recheck_sdio_irq = true,
  436. .hs400_tune = false,
  437. .pad_tune_reg = MSDC_PAD_TUNE0,
  438. .async_fifo = true,
  439. .data_tune = true,
  440. .busy_check = false,
  441. .stop_clk_fix = false,
  442. .enhance_rx = false,
  443. .support_64g = false,
  444. };
  445. static const struct mtk_mmc_compatible mt2712_compat = {
  446. .clk_div_bits = 12,
  447. .recheck_sdio_irq = false,
  448. .hs400_tune = false,
  449. .pad_tune_reg = MSDC_PAD_TUNE0,
  450. .async_fifo = true,
  451. .data_tune = true,
  452. .busy_check = true,
  453. .stop_clk_fix = true,
  454. .enhance_rx = true,
  455. .support_64g = true,
  456. };
  457. static const struct mtk_mmc_compatible mt7622_compat = {
  458. .clk_div_bits = 12,
  459. .recheck_sdio_irq = true,
  460. .hs400_tune = false,
  461. .pad_tune_reg = MSDC_PAD_TUNE0,
  462. .async_fifo = true,
  463. .data_tune = true,
  464. .busy_check = true,
  465. .stop_clk_fix = true,
  466. .enhance_rx = true,
  467. .support_64g = false,
  468. };
  469. static const struct mtk_mmc_compatible mt8516_compat = {
  470. .clk_div_bits = 12,
  471. .recheck_sdio_irq = true,
  472. .hs400_tune = false,
  473. .pad_tune_reg = MSDC_PAD_TUNE0,
  474. .async_fifo = true,
  475. .data_tune = true,
  476. .busy_check = true,
  477. .stop_clk_fix = true,
  478. };
  479. static const struct mtk_mmc_compatible mt7620_compat = {
  480. .clk_div_bits = 8,
  481. .recheck_sdio_irq = true,
  482. .hs400_tune = false,
  483. .pad_tune_reg = MSDC_PAD_TUNE,
  484. .async_fifo = false,
  485. .data_tune = false,
  486. .busy_check = false,
  487. .stop_clk_fix = false,
  488. .enhance_rx = false,
  489. .use_internal_cd = true,
  490. };
  491. static const struct mtk_mmc_compatible mt6779_compat = {
  492. .clk_div_bits = 12,
  493. .recheck_sdio_irq = false,
  494. .hs400_tune = false,
  495. .pad_tune_reg = MSDC_PAD_TUNE0,
  496. .async_fifo = true,
  497. .data_tune = true,
  498. .busy_check = true,
  499. .stop_clk_fix = true,
  500. .enhance_rx = true,
  501. .support_64g = true,
  502. };
  503. static const struct of_device_id msdc_of_ids[] = {
  504. { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
  505. { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
  506. { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
  507. { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
  508. { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
  509. { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
  510. { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
  511. { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
  512. { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
  513. {}
  514. };
  515. MODULE_DEVICE_TABLE(of, msdc_of_ids);
  516. static void sdr_set_bits(void __iomem *reg, u32 bs)
  517. {
  518. u32 val = readl(reg);
  519. val |= bs;
  520. writel(val, reg);
  521. }
  522. static void sdr_clr_bits(void __iomem *reg, u32 bs)
  523. {
  524. u32 val = readl(reg);
  525. val &= ~bs;
  526. writel(val, reg);
  527. }
  528. static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
  529. {
  530. unsigned int tv = readl(reg);
  531. tv &= ~field;
  532. tv |= ((val) << (ffs((unsigned int)field) - 1));
  533. writel(tv, reg);
  534. }
  535. static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
  536. {
  537. unsigned int tv = readl(reg);
  538. *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
  539. }
  540. static void msdc_reset_hw(struct msdc_host *host)
  541. {
  542. u32 val;
  543. sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
  544. while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
  545. cpu_relax();
  546. sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
  547. while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
  548. cpu_relax();
  549. val = readl(host->base + MSDC_INT);
  550. writel(val, host->base + MSDC_INT);
  551. }
  552. static void msdc_cmd_next(struct msdc_host *host,
  553. struct mmc_request *mrq, struct mmc_command *cmd);
  554. static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
  555. static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
  556. MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
  557. MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
  558. static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
  559. MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
  560. MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
  561. static u8 msdc_dma_calcs(u8 *buf, u32 len)
  562. {
  563. u32 i, sum = 0;
  564. for (i = 0; i < len; i++)
  565. sum += buf[i];
  566. return 0xff - (u8) sum;
  567. }
  568. static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
  569. struct mmc_data *data)
  570. {
  571. unsigned int j, dma_len;
  572. dma_addr_t dma_address;
  573. u32 dma_ctrl;
  574. struct scatterlist *sg;
  575. struct mt_gpdma_desc *gpd;
  576. struct mt_bdma_desc *bd;
  577. sg = data->sg;
  578. gpd = dma->gpd;
  579. bd = dma->bd;
  580. /* modify gpd */
  581. gpd->gpd_info |= GPDMA_DESC_HWO;
  582. gpd->gpd_info |= GPDMA_DESC_BDP;
  583. /* need to clear first. use these bits to calc checksum */
  584. gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
  585. gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
  586. /* modify bd */
  587. for_each_sg(data->sg, sg, data->sg_count, j) {
  588. dma_address = sg_dma_address(sg);
  589. dma_len = sg_dma_len(sg);
  590. /* init bd */
  591. bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
  592. bd[j].bd_info &= ~BDMA_DESC_DWPAD;
  593. bd[j].ptr = lower_32_bits(dma_address);
  594. if (host->dev_comp->support_64g) {
  595. bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
  596. bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
  597. << 28;
  598. }
  599. if (host->dev_comp->support_64g) {
  600. bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
  601. bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
  602. } else {
  603. bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
  604. bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
  605. }
  606. if (j == data->sg_count - 1) /* the last bd */
  607. bd[j].bd_info |= BDMA_DESC_EOL;
  608. else
  609. bd[j].bd_info &= ~BDMA_DESC_EOL;
  610. /* checksume need to clear first */
  611. bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
  612. bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
  613. }
  614. sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
  615. dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
  616. dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
  617. dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
  618. writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
  619. if (host->dev_comp->support_64g)
  620. sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
  621. upper_32_bits(dma->gpd_addr) & 0xf);
  622. writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
  623. }
  624. static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
  625. {
  626. struct mmc_data *data = mrq->data;
  627. if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
  628. data->host_cookie |= MSDC_PREPARE_FLAG;
  629. data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
  630. mmc_get_dma_dir(data));
  631. }
  632. }
  633. static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
  634. {
  635. struct mmc_data *data = mrq->data;
  636. if (data->host_cookie & MSDC_ASYNC_FLAG)
  637. return;
  638. if (data->host_cookie & MSDC_PREPARE_FLAG) {
  639. dma_unmap_sg(host->dev, data->sg, data->sg_len,
  640. mmc_get_dma_dir(data));
  641. data->host_cookie &= ~MSDC_PREPARE_FLAG;
  642. }
  643. }
  644. static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
  645. {
  646. struct mmc_host *mmc = mmc_from_priv(host);
  647. u64 timeout, clk_ns;
  648. u32 mode = 0;
  649. if (mmc->actual_clock == 0) {
  650. timeout = 0;
  651. } else {
  652. clk_ns = 1000000000ULL;
  653. do_div(clk_ns, mmc->actual_clock);
  654. timeout = ns + clk_ns - 1;
  655. do_div(timeout, clk_ns);
  656. timeout += clks;
  657. /* in 1048576 sclk cycle unit */
  658. timeout = DIV_ROUND_UP(timeout, (0x1 << 20));
  659. if (host->dev_comp->clk_div_bits == 8)
  660. sdr_get_field(host->base + MSDC_CFG,
  661. MSDC_CFG_CKMOD, &mode);
  662. else
  663. sdr_get_field(host->base + MSDC_CFG,
  664. MSDC_CFG_CKMOD_EXTRA, &mode);
  665. /*DDR mode will double the clk cycles for data timeout */
  666. timeout = mode >= 2 ? timeout * 2 : timeout;
  667. timeout = timeout > 1 ? timeout - 1 : 0;
  668. }
  669. return timeout;
  670. }
  671. /* clock control primitives */
  672. static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
  673. {
  674. u64 timeout;
  675. host->timeout_ns = ns;
  676. host->timeout_clks = clks;
  677. timeout = msdc_timeout_cal(host, ns, clks);
  678. sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
  679. (u32)(timeout > 255 ? 255 : timeout));
  680. }
  681. static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
  682. {
  683. u64 timeout;
  684. timeout = msdc_timeout_cal(host, ns, clks);
  685. sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
  686. (u32)(timeout > 8191 ? 8191 : timeout));
  687. }
  688. static void msdc_gate_clock(struct msdc_host *host)
  689. {
  690. clk_disable_unprepare(host->src_clk_cg);
  691. clk_disable_unprepare(host->src_clk);
  692. clk_disable_unprepare(host->bus_clk);
  693. clk_disable_unprepare(host->h_clk);
  694. }
  695. static void msdc_ungate_clock(struct msdc_host *host)
  696. {
  697. clk_prepare_enable(host->h_clk);
  698. clk_prepare_enable(host->bus_clk);
  699. clk_prepare_enable(host->src_clk);
  700. clk_prepare_enable(host->src_clk_cg);
  701. while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
  702. cpu_relax();
  703. }
  704. static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
  705. {
  706. struct mmc_host *mmc = mmc_from_priv(host);
  707. u32 mode;
  708. u32 flags;
  709. u32 div;
  710. u32 sclk;
  711. u32 tune_reg = host->dev_comp->pad_tune_reg;
  712. if (!hz) {
  713. dev_dbg(host->dev, "set mclk to 0\n");
  714. host->mclk = 0;
  715. mmc->actual_clock = 0;
  716. sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
  717. return;
  718. }
  719. flags = readl(host->base + MSDC_INTEN);
  720. sdr_clr_bits(host->base + MSDC_INTEN, flags);
  721. if (host->dev_comp->clk_div_bits == 8)
  722. sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
  723. else
  724. sdr_clr_bits(host->base + MSDC_CFG,
  725. MSDC_CFG_HS400_CK_MODE_EXTRA);
  726. if (timing == MMC_TIMING_UHS_DDR50 ||
  727. timing == MMC_TIMING_MMC_DDR52 ||
  728. timing == MMC_TIMING_MMC_HS400) {
  729. if (timing == MMC_TIMING_MMC_HS400)
  730. mode = 0x3;
  731. else
  732. mode = 0x2; /* ddr mode and use divisor */
  733. if (hz >= (host->src_clk_freq >> 2)) {
  734. div = 0; /* mean div = 1/4 */
  735. sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
  736. } else {
  737. div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
  738. sclk = (host->src_clk_freq >> 2) / div;
  739. div = (div >> 1);
  740. }
  741. if (timing == MMC_TIMING_MMC_HS400 &&
  742. hz >= (host->src_clk_freq >> 1)) {
  743. if (host->dev_comp->clk_div_bits == 8)
  744. sdr_set_bits(host->base + MSDC_CFG,
  745. MSDC_CFG_HS400_CK_MODE);
  746. else
  747. sdr_set_bits(host->base + MSDC_CFG,
  748. MSDC_CFG_HS400_CK_MODE_EXTRA);
  749. sclk = host->src_clk_freq >> 1;
  750. div = 0; /* div is ignore when bit18 is set */
  751. }
  752. } else if (hz >= host->src_clk_freq) {
  753. mode = 0x1; /* no divisor */
  754. div = 0;
  755. sclk = host->src_clk_freq;
  756. } else {
  757. mode = 0x0; /* use divisor */
  758. if (hz >= (host->src_clk_freq >> 1)) {
  759. div = 0; /* mean div = 1/2 */
  760. sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
  761. } else {
  762. div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
  763. sclk = (host->src_clk_freq >> 2) / div;
  764. }
  765. }
  766. sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
  767. /*
  768. * As src_clk/HCLK use the same bit to gate/ungate,
  769. * So if want to only gate src_clk, need gate its parent(mux).
  770. */
  771. if (host->src_clk_cg)
  772. clk_disable_unprepare(host->src_clk_cg);
  773. else
  774. clk_disable_unprepare(clk_get_parent(host->src_clk));
  775. if (host->dev_comp->clk_div_bits == 8)
  776. sdr_set_field(host->base + MSDC_CFG,
  777. MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
  778. (mode << 8) | div);
  779. else
  780. sdr_set_field(host->base + MSDC_CFG,
  781. MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
  782. (mode << 12) | div);
  783. if (host->src_clk_cg)
  784. clk_prepare_enable(host->src_clk_cg);
  785. else
  786. clk_prepare_enable(clk_get_parent(host->src_clk));
  787. while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
  788. cpu_relax();
  789. sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
  790. mmc->actual_clock = sclk;
  791. host->mclk = hz;
  792. host->timing = timing;
  793. /* need because clk changed. */
  794. msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
  795. sdr_set_bits(host->base + MSDC_INTEN, flags);
  796. /*
  797. * mmc_select_hs400() will drop to 50Mhz and High speed mode,
  798. * tune result of hs200/200Mhz is not suitable for 50Mhz
  799. */
  800. if (mmc->actual_clock <= 52000000) {
  801. writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
  802. if (host->top_base) {
  803. writel(host->def_tune_para.emmc_top_control,
  804. host->top_base + EMMC_TOP_CONTROL);
  805. writel(host->def_tune_para.emmc_top_cmd,
  806. host->top_base + EMMC_TOP_CMD);
  807. } else {
  808. writel(host->def_tune_para.pad_tune,
  809. host->base + tune_reg);
  810. }
  811. } else {
  812. writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
  813. writel(host->saved_tune_para.pad_cmd_tune,
  814. host->base + PAD_CMD_TUNE);
  815. if (host->top_base) {
  816. writel(host->saved_tune_para.emmc_top_control,
  817. host->top_base + EMMC_TOP_CONTROL);
  818. writel(host->saved_tune_para.emmc_top_cmd,
  819. host->top_base + EMMC_TOP_CMD);
  820. } else {
  821. writel(host->saved_tune_para.pad_tune,
  822. host->base + tune_reg);
  823. }
  824. }
  825. if (timing == MMC_TIMING_MMC_HS400 &&
  826. host->dev_comp->hs400_tune)
  827. sdr_set_field(host->base + tune_reg,
  828. MSDC_PAD_TUNE_CMDRRDLY,
  829. host->hs400_cmd_int_delay);
  830. dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
  831. timing);
  832. }
  833. static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
  834. struct mmc_request *mrq, struct mmc_command *cmd)
  835. {
  836. u32 resp;
  837. switch (mmc_resp_type(cmd)) {
  838. /* Actually, R1, R5, R6, R7 are the same */
  839. case MMC_RSP_R1:
  840. resp = 0x1;
  841. break;
  842. case MMC_RSP_R1B:
  843. resp = 0x7;
  844. break;
  845. case MMC_RSP_R2:
  846. resp = 0x2;
  847. break;
  848. case MMC_RSP_R3:
  849. resp = 0x3;
  850. break;
  851. case MMC_RSP_NONE:
  852. default:
  853. resp = 0x0;
  854. break;
  855. }
  856. return resp;
  857. }
  858. static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
  859. struct mmc_request *mrq, struct mmc_command *cmd)
  860. {
  861. struct mmc_host *mmc = mmc_from_priv(host);
  862. /* rawcmd :
  863. * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
  864. * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
  865. */
  866. u32 opcode = cmd->opcode;
  867. u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
  868. u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
  869. host->cmd_rsp = resp;
  870. if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
  871. opcode == MMC_STOP_TRANSMISSION)
  872. rawcmd |= (0x1 << 14);
  873. else if (opcode == SD_SWITCH_VOLTAGE)
  874. rawcmd |= (0x1 << 30);
  875. else if (opcode == SD_APP_SEND_SCR ||
  876. opcode == SD_APP_SEND_NUM_WR_BLKS ||
  877. (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
  878. (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
  879. (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
  880. rawcmd |= (0x1 << 11);
  881. if (cmd->data) {
  882. struct mmc_data *data = cmd->data;
  883. if (mmc_op_multi(opcode)) {
  884. if (mmc_card_mmc(mmc->card) && mrq->sbc &&
  885. !(mrq->sbc->arg & 0xFFFF0000))
  886. rawcmd |= 0x2 << 28; /* AutoCMD23 */
  887. }
  888. rawcmd |= ((data->blksz & 0xFFF) << 16);
  889. if (data->flags & MMC_DATA_WRITE)
  890. rawcmd |= (0x1 << 13);
  891. if (data->blocks > 1)
  892. rawcmd |= (0x2 << 11);
  893. else
  894. rawcmd |= (0x1 << 11);
  895. /* Always use dma mode */
  896. sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
  897. if (host->timeout_ns != data->timeout_ns ||
  898. host->timeout_clks != data->timeout_clks)
  899. msdc_set_timeout(host, data->timeout_ns,
  900. data->timeout_clks);
  901. writel(data->blocks, host->base + SDC_BLK_NUM);
  902. }
  903. return rawcmd;
  904. }
  905. static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
  906. struct mmc_command *cmd, struct mmc_data *data)
  907. {
  908. bool read;
  909. WARN_ON(host->data);
  910. host->data = data;
  911. read = data->flags & MMC_DATA_READ;
  912. mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
  913. msdc_dma_setup(host, &host->dma, data);
  914. sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
  915. sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
  916. dev_dbg(host->dev, "DMA start\n");
  917. dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
  918. __func__, cmd->opcode, data->blocks, read);
  919. }
  920. static int msdc_auto_cmd_done(struct msdc_host *host, int events,
  921. struct mmc_command *cmd)
  922. {
  923. u32 *rsp = cmd->resp;
  924. rsp[0] = readl(host->base + SDC_ACMD_RESP);
  925. if (events & MSDC_INT_ACMDRDY) {
  926. cmd->error = 0;
  927. } else {
  928. msdc_reset_hw(host);
  929. if (events & MSDC_INT_ACMDCRCERR) {
  930. cmd->error = -EILSEQ;
  931. host->error |= REQ_STOP_EIO;
  932. } else if (events & MSDC_INT_ACMDTMO) {
  933. cmd->error = -ETIMEDOUT;
  934. host->error |= REQ_STOP_TMO;
  935. }
  936. dev_err(host->dev,
  937. "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
  938. __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
  939. }
  940. return cmd->error;
  941. }
  942. /*
  943. * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
  944. *
  945. * Host controller may lost interrupt in some special case.
  946. * Add SDIO irq recheck mechanism to make sure all interrupts
  947. * can be processed immediately
  948. */
  949. static void msdc_recheck_sdio_irq(struct msdc_host *host)
  950. {
  951. struct mmc_host *mmc = mmc_from_priv(host);
  952. u32 reg_int, reg_inten, reg_ps;
  953. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  954. reg_inten = readl(host->base + MSDC_INTEN);
  955. if (reg_inten & MSDC_INTEN_SDIOIRQ) {
  956. reg_int = readl(host->base + MSDC_INT);
  957. reg_ps = readl(host->base + MSDC_PS);
  958. if (!(reg_int & MSDC_INT_SDIOIRQ ||
  959. reg_ps & MSDC_PS_DATA1)) {
  960. __msdc_enable_sdio_irq(host, 0);
  961. sdio_signal_irq(mmc);
  962. }
  963. }
  964. }
  965. }
  966. static void msdc_track_cmd_data(struct msdc_host *host,
  967. struct mmc_command *cmd, struct mmc_data *data)
  968. {
  969. if (host->error)
  970. dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
  971. __func__, cmd->opcode, cmd->arg, host->error);
  972. }
  973. static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
  974. {
  975. unsigned long flags;
  976. /*
  977. * No need check the return value of cancel_delayed_work, as only ONE
  978. * path will go here!
  979. */
  980. cancel_delayed_work(&host->req_timeout);
  981. spin_lock_irqsave(&host->lock, flags);
  982. host->mrq = NULL;
  983. spin_unlock_irqrestore(&host->lock, flags);
  984. msdc_track_cmd_data(host, mrq->cmd, mrq->data);
  985. if (mrq->data)
  986. msdc_unprepare_data(host, mrq);
  987. if (host->error)
  988. msdc_reset_hw(host);
  989. mmc_request_done(mmc_from_priv(host), mrq);
  990. if (host->dev_comp->recheck_sdio_irq)
  991. msdc_recheck_sdio_irq(host);
  992. }
  993. /* returns true if command is fully handled; returns false otherwise */
  994. static bool msdc_cmd_done(struct msdc_host *host, int events,
  995. struct mmc_request *mrq, struct mmc_command *cmd)
  996. {
  997. bool done = false;
  998. bool sbc_error;
  999. unsigned long flags;
  1000. u32 *rsp;
  1001. if (mrq->sbc && cmd == mrq->cmd &&
  1002. (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
  1003. | MSDC_INT_ACMDTMO)))
  1004. msdc_auto_cmd_done(host, events, mrq->sbc);
  1005. sbc_error = mrq->sbc && mrq->sbc->error;
  1006. if (!sbc_error && !(events & (MSDC_INT_CMDRDY
  1007. | MSDC_INT_RSPCRCERR
  1008. | MSDC_INT_CMDTMO)))
  1009. return done;
  1010. spin_lock_irqsave(&host->lock, flags);
  1011. done = !host->cmd;
  1012. host->cmd = NULL;
  1013. spin_unlock_irqrestore(&host->lock, flags);
  1014. if (done)
  1015. return true;
  1016. rsp = cmd->resp;
  1017. sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
  1018. if (cmd->flags & MMC_RSP_PRESENT) {
  1019. if (cmd->flags & MMC_RSP_136) {
  1020. rsp[0] = readl(host->base + SDC_RESP3);
  1021. rsp[1] = readl(host->base + SDC_RESP2);
  1022. rsp[2] = readl(host->base + SDC_RESP1);
  1023. rsp[3] = readl(host->base + SDC_RESP0);
  1024. } else {
  1025. rsp[0] = readl(host->base + SDC_RESP0);
  1026. }
  1027. }
  1028. if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
  1029. if (events & MSDC_INT_CMDTMO ||
  1030. (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
  1031. cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
  1032. /*
  1033. * should not clear fifo/interrupt as the tune data
  1034. * may have alreay come when cmd19/cmd21 gets response
  1035. * CRC error.
  1036. */
  1037. msdc_reset_hw(host);
  1038. if (events & MSDC_INT_RSPCRCERR) {
  1039. cmd->error = -EILSEQ;
  1040. host->error |= REQ_CMD_EIO;
  1041. } else if (events & MSDC_INT_CMDTMO) {
  1042. cmd->error = -ETIMEDOUT;
  1043. host->error |= REQ_CMD_TMO;
  1044. }
  1045. }
  1046. if (cmd->error)
  1047. dev_dbg(host->dev,
  1048. "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
  1049. __func__, cmd->opcode, cmd->arg, rsp[0],
  1050. cmd->error);
  1051. msdc_cmd_next(host, mrq, cmd);
  1052. return true;
  1053. }
  1054. /* It is the core layer's responsibility to ensure card status
  1055. * is correct before issue a request. but host design do below
  1056. * checks recommended.
  1057. */
  1058. static inline bool msdc_cmd_is_ready(struct msdc_host *host,
  1059. struct mmc_request *mrq, struct mmc_command *cmd)
  1060. {
  1061. /* The max busy time we can endure is 20ms */
  1062. unsigned long tmo = jiffies + msecs_to_jiffies(20);
  1063. while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
  1064. time_before(jiffies, tmo))
  1065. cpu_relax();
  1066. if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
  1067. dev_err(host->dev, "CMD bus busy detected\n");
  1068. host->error |= REQ_CMD_BUSY;
  1069. msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
  1070. return false;
  1071. }
  1072. if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
  1073. tmo = jiffies + msecs_to_jiffies(20);
  1074. /* R1B or with data, should check SDCBUSY */
  1075. while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
  1076. time_before(jiffies, tmo))
  1077. cpu_relax();
  1078. if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
  1079. dev_err(host->dev, "Controller busy detected\n");
  1080. host->error |= REQ_CMD_BUSY;
  1081. msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
  1082. return false;
  1083. }
  1084. }
  1085. return true;
  1086. }
  1087. static void msdc_start_command(struct msdc_host *host,
  1088. struct mmc_request *mrq, struct mmc_command *cmd)
  1089. {
  1090. u32 rawcmd;
  1091. unsigned long flags;
  1092. WARN_ON(host->cmd);
  1093. host->cmd = cmd;
  1094. mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
  1095. if (!msdc_cmd_is_ready(host, mrq, cmd))
  1096. return;
  1097. if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
  1098. readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
  1099. dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
  1100. msdc_reset_hw(host);
  1101. }
  1102. cmd->error = 0;
  1103. rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
  1104. spin_lock_irqsave(&host->lock, flags);
  1105. sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
  1106. spin_unlock_irqrestore(&host->lock, flags);
  1107. writel(cmd->arg, host->base + SDC_ARG);
  1108. writel(rawcmd, host->base + SDC_CMD);
  1109. }
  1110. static void msdc_cmd_next(struct msdc_host *host,
  1111. struct mmc_request *mrq, struct mmc_command *cmd)
  1112. {
  1113. if ((cmd->error &&
  1114. !(cmd->error == -EILSEQ &&
  1115. (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
  1116. cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
  1117. (mrq->sbc && mrq->sbc->error))
  1118. msdc_request_done(host, mrq);
  1119. else if (cmd == mrq->sbc)
  1120. msdc_start_command(host, mrq, mrq->cmd);
  1121. else if (!cmd->data)
  1122. msdc_request_done(host, mrq);
  1123. else
  1124. msdc_start_data(host, mrq, cmd, cmd->data);
  1125. }
  1126. static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
  1127. {
  1128. struct msdc_host *host = mmc_priv(mmc);
  1129. host->error = 0;
  1130. WARN_ON(host->mrq);
  1131. host->mrq = mrq;
  1132. if (mrq->data)
  1133. msdc_prepare_data(host, mrq);
  1134. /* if SBC is required, we have HW option and SW option.
  1135. * if HW option is enabled, and SBC does not have "special" flags,
  1136. * use HW option, otherwise use SW option
  1137. */
  1138. if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
  1139. (mrq->sbc->arg & 0xFFFF0000)))
  1140. msdc_start_command(host, mrq, mrq->sbc);
  1141. else
  1142. msdc_start_command(host, mrq, mrq->cmd);
  1143. }
  1144. static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
  1145. {
  1146. struct msdc_host *host = mmc_priv(mmc);
  1147. struct mmc_data *data = mrq->data;
  1148. if (!data)
  1149. return;
  1150. msdc_prepare_data(host, mrq);
  1151. data->host_cookie |= MSDC_ASYNC_FLAG;
  1152. }
  1153. static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1154. int err)
  1155. {
  1156. struct msdc_host *host = mmc_priv(mmc);
  1157. struct mmc_data *data;
  1158. data = mrq->data;
  1159. if (!data)
  1160. return;
  1161. if (data->host_cookie) {
  1162. data->host_cookie &= ~MSDC_ASYNC_FLAG;
  1163. msdc_unprepare_data(host, mrq);
  1164. }
  1165. }
  1166. static void msdc_data_xfer_next(struct msdc_host *host,
  1167. struct mmc_request *mrq, struct mmc_data *data)
  1168. {
  1169. if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
  1170. !mrq->sbc)
  1171. msdc_start_command(host, mrq, mrq->stop);
  1172. else
  1173. msdc_request_done(host, mrq);
  1174. }
  1175. static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
  1176. struct mmc_request *mrq, struct mmc_data *data)
  1177. {
  1178. struct mmc_command *stop;
  1179. unsigned long flags;
  1180. bool done;
  1181. unsigned int check_data = events &
  1182. (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
  1183. | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
  1184. | MSDC_INT_DMA_PROTECT);
  1185. spin_lock_irqsave(&host->lock, flags);
  1186. done = !host->data;
  1187. if (check_data)
  1188. host->data = NULL;
  1189. spin_unlock_irqrestore(&host->lock, flags);
  1190. if (done)
  1191. return true;
  1192. stop = data->stop;
  1193. if (check_data || (stop && stop->error)) {
  1194. dev_dbg(host->dev, "DMA status: 0x%8X\n",
  1195. readl(host->base + MSDC_DMA_CFG));
  1196. sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
  1197. 1);
  1198. while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
  1199. cpu_relax();
  1200. sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
  1201. dev_dbg(host->dev, "DMA stop\n");
  1202. if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
  1203. data->bytes_xfered = data->blocks * data->blksz;
  1204. } else {
  1205. dev_dbg(host->dev, "interrupt events: %x\n", events);
  1206. msdc_reset_hw(host);
  1207. host->error |= REQ_DAT_ERR;
  1208. data->bytes_xfered = 0;
  1209. if (events & MSDC_INT_DATTMO)
  1210. data->error = -ETIMEDOUT;
  1211. else if (events & MSDC_INT_DATCRCERR)
  1212. data->error = -EILSEQ;
  1213. dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
  1214. __func__, mrq->cmd->opcode, data->blocks);
  1215. dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
  1216. (int)data->error, data->bytes_xfered);
  1217. }
  1218. msdc_data_xfer_next(host, mrq, data);
  1219. done = true;
  1220. }
  1221. return done;
  1222. }
  1223. static void msdc_set_buswidth(struct msdc_host *host, u32 width)
  1224. {
  1225. u32 val = readl(host->base + SDC_CFG);
  1226. val &= ~SDC_CFG_BUSWIDTH;
  1227. switch (width) {
  1228. default:
  1229. case MMC_BUS_WIDTH_1:
  1230. val |= (MSDC_BUS_1BITS << 16);
  1231. break;
  1232. case MMC_BUS_WIDTH_4:
  1233. val |= (MSDC_BUS_4BITS << 16);
  1234. break;
  1235. case MMC_BUS_WIDTH_8:
  1236. val |= (MSDC_BUS_8BITS << 16);
  1237. break;
  1238. }
  1239. writel(val, host->base + SDC_CFG);
  1240. dev_dbg(host->dev, "Bus Width = %d", width);
  1241. }
  1242. static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
  1243. {
  1244. struct msdc_host *host = mmc_priv(mmc);
  1245. int ret;
  1246. if (!IS_ERR(mmc->supply.vqmmc)) {
  1247. if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
  1248. ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
  1249. dev_err(host->dev, "Unsupported signal voltage!\n");
  1250. return -EINVAL;
  1251. }
  1252. ret = mmc_regulator_set_vqmmc(mmc, ios);
  1253. if (ret < 0) {
  1254. dev_dbg(host->dev, "Regulator set error %d (%d)\n",
  1255. ret, ios->signal_voltage);
  1256. return ret;
  1257. }
  1258. /* Apply different pinctrl settings for different signal voltage */
  1259. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  1260. pinctrl_select_state(host->pinctrl, host->pins_uhs);
  1261. else
  1262. pinctrl_select_state(host->pinctrl, host->pins_default);
  1263. }
  1264. return 0;
  1265. }
  1266. static int msdc_card_busy(struct mmc_host *mmc)
  1267. {
  1268. struct msdc_host *host = mmc_priv(mmc);
  1269. u32 status = readl(host->base + MSDC_PS);
  1270. /* only check if data0 is low */
  1271. return !(status & BIT(16));
  1272. }
  1273. static void msdc_request_timeout(struct work_struct *work)
  1274. {
  1275. struct msdc_host *host = container_of(work, struct msdc_host,
  1276. req_timeout.work);
  1277. /* simulate HW timeout status */
  1278. dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
  1279. if (host->mrq) {
  1280. dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
  1281. host->mrq, host->mrq->cmd->opcode);
  1282. if (host->cmd) {
  1283. dev_err(host->dev, "%s: aborting cmd=%d\n",
  1284. __func__, host->cmd->opcode);
  1285. msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
  1286. host->cmd);
  1287. } else if (host->data) {
  1288. dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
  1289. __func__, host->mrq->cmd->opcode,
  1290. host->data->blocks);
  1291. msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
  1292. host->data);
  1293. }
  1294. }
  1295. }
  1296. static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
  1297. {
  1298. if (enb) {
  1299. sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
  1300. sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
  1301. if (host->dev_comp->recheck_sdio_irq)
  1302. msdc_recheck_sdio_irq(host);
  1303. } else {
  1304. sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
  1305. sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
  1306. }
  1307. }
  1308. static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
  1309. {
  1310. unsigned long flags;
  1311. struct msdc_host *host = mmc_priv(mmc);
  1312. spin_lock_irqsave(&host->lock, flags);
  1313. __msdc_enable_sdio_irq(host, enb);
  1314. spin_unlock_irqrestore(&host->lock, flags);
  1315. if (enb)
  1316. pm_runtime_get_noresume(host->dev);
  1317. else
  1318. pm_runtime_put_noidle(host->dev);
  1319. }
  1320. static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
  1321. {
  1322. struct mmc_host *mmc = mmc_from_priv(host);
  1323. int cmd_err = 0, dat_err = 0;
  1324. if (intsts & MSDC_INT_RSPCRCERR) {
  1325. cmd_err = -EILSEQ;
  1326. dev_err(host->dev, "%s: CMD CRC ERR", __func__);
  1327. } else if (intsts & MSDC_INT_CMDTMO) {
  1328. cmd_err = -ETIMEDOUT;
  1329. dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
  1330. }
  1331. if (intsts & MSDC_INT_DATCRCERR) {
  1332. dat_err = -EILSEQ;
  1333. dev_err(host->dev, "%s: DATA CRC ERR", __func__);
  1334. } else if (intsts & MSDC_INT_DATTMO) {
  1335. dat_err = -ETIMEDOUT;
  1336. dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
  1337. }
  1338. if (cmd_err || dat_err) {
  1339. dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
  1340. cmd_err, dat_err, intsts);
  1341. }
  1342. return cqhci_irq(mmc, 0, cmd_err, dat_err);
  1343. }
  1344. static irqreturn_t msdc_irq(int irq, void *dev_id)
  1345. {
  1346. struct msdc_host *host = (struct msdc_host *) dev_id;
  1347. struct mmc_host *mmc = mmc_from_priv(host);
  1348. while (true) {
  1349. unsigned long flags;
  1350. struct mmc_request *mrq;
  1351. struct mmc_command *cmd;
  1352. struct mmc_data *data;
  1353. u32 events, event_mask;
  1354. spin_lock_irqsave(&host->lock, flags);
  1355. events = readl(host->base + MSDC_INT);
  1356. event_mask = readl(host->base + MSDC_INTEN);
  1357. if ((events & event_mask) & MSDC_INT_SDIOIRQ)
  1358. __msdc_enable_sdio_irq(host, 0);
  1359. /* clear interrupts */
  1360. writel(events & event_mask, host->base + MSDC_INT);
  1361. mrq = host->mrq;
  1362. cmd = host->cmd;
  1363. data = host->data;
  1364. spin_unlock_irqrestore(&host->lock, flags);
  1365. if ((events & event_mask) & MSDC_INT_SDIOIRQ)
  1366. sdio_signal_irq(mmc);
  1367. if ((events & event_mask) & MSDC_INT_CDSC) {
  1368. if (host->internal_cd)
  1369. mmc_detect_change(mmc, msecs_to_jiffies(20));
  1370. events &= ~MSDC_INT_CDSC;
  1371. }
  1372. if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
  1373. break;
  1374. if ((mmc->caps2 & MMC_CAP2_CQE) &&
  1375. (events & MSDC_INT_CMDQ)) {
  1376. msdc_cmdq_irq(host, events);
  1377. /* clear interrupts */
  1378. writel(events, host->base + MSDC_INT);
  1379. return IRQ_HANDLED;
  1380. }
  1381. if (!mrq) {
  1382. dev_err(host->dev,
  1383. "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
  1384. __func__, events, event_mask);
  1385. WARN_ON(1);
  1386. break;
  1387. }
  1388. dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
  1389. if (cmd)
  1390. msdc_cmd_done(host, events, mrq, cmd);
  1391. else if (data)
  1392. msdc_data_xfer_done(host, events, mrq, data);
  1393. }
  1394. return IRQ_HANDLED;
  1395. }
  1396. static void msdc_init_hw(struct msdc_host *host)
  1397. {
  1398. u32 val;
  1399. u32 tune_reg = host->dev_comp->pad_tune_reg;
  1400. if (host->reset) {
  1401. reset_control_assert(host->reset);
  1402. usleep_range(10, 50);
  1403. reset_control_deassert(host->reset);
  1404. }
  1405. /* Configure to MMC/SD mode, clock free running */
  1406. sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
  1407. /* Reset */
  1408. msdc_reset_hw(host);
  1409. /* Disable and clear all interrupts */
  1410. writel(0, host->base + MSDC_INTEN);
  1411. val = readl(host->base + MSDC_INT);
  1412. writel(val, host->base + MSDC_INT);
  1413. /* Configure card detection */
  1414. if (host->internal_cd) {
  1415. sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
  1416. DEFAULT_DEBOUNCE);
  1417. sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
  1418. sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
  1419. sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
  1420. } else {
  1421. sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
  1422. sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
  1423. sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
  1424. }
  1425. if (host->top_base) {
  1426. writel(0, host->top_base + EMMC_TOP_CONTROL);
  1427. writel(0, host->top_base + EMMC_TOP_CMD);
  1428. } else {
  1429. writel(0, host->base + tune_reg);
  1430. }
  1431. writel(0, host->base + MSDC_IOCON);
  1432. sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
  1433. writel(0x403c0046, host->base + MSDC_PATCH_BIT);
  1434. sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
  1435. writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
  1436. sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
  1437. if (host->dev_comp->stop_clk_fix) {
  1438. sdr_set_field(host->base + MSDC_PATCH_BIT1,
  1439. MSDC_PATCH_BIT1_STOP_DLY, 3);
  1440. sdr_clr_bits(host->base + SDC_FIFO_CFG,
  1441. SDC_FIFO_CFG_WRVALIDSEL);
  1442. sdr_clr_bits(host->base + SDC_FIFO_CFG,
  1443. SDC_FIFO_CFG_RDVALIDSEL);
  1444. }
  1445. if (host->dev_comp->busy_check)
  1446. sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
  1447. if (host->dev_comp->async_fifo) {
  1448. sdr_set_field(host->base + MSDC_PATCH_BIT2,
  1449. MSDC_PB2_RESPWAIT, 3);
  1450. if (host->dev_comp->enhance_rx) {
  1451. if (host->top_base)
  1452. sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
  1453. SDC_RX_ENH_EN);
  1454. else
  1455. sdr_set_bits(host->base + SDC_ADV_CFG0,
  1456. SDC_RX_ENHANCE_EN);
  1457. } else {
  1458. sdr_set_field(host->base + MSDC_PATCH_BIT2,
  1459. MSDC_PB2_RESPSTSENSEL, 2);
  1460. sdr_set_field(host->base + MSDC_PATCH_BIT2,
  1461. MSDC_PB2_CRCSTSENSEL, 2);
  1462. }
  1463. /* use async fifo, then no need tune internal delay */
  1464. sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
  1465. MSDC_PATCH_BIT2_CFGRESP);
  1466. sdr_set_bits(host->base + MSDC_PATCH_BIT2,
  1467. MSDC_PATCH_BIT2_CFGCRCSTS);
  1468. }
  1469. if (host->dev_comp->support_64g)
  1470. sdr_set_bits(host->base + MSDC_PATCH_BIT2,
  1471. MSDC_PB2_SUPPORT_64G);
  1472. if (host->dev_comp->data_tune) {
  1473. if (host->top_base) {
  1474. sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
  1475. PAD_DAT_RD_RXDLY_SEL);
  1476. sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
  1477. DATA_K_VALUE_SEL);
  1478. sdr_set_bits(host->top_base + EMMC_TOP_CMD,
  1479. PAD_CMD_RD_RXDLY_SEL);
  1480. } else {
  1481. sdr_set_bits(host->base + tune_reg,
  1482. MSDC_PAD_TUNE_RD_SEL |
  1483. MSDC_PAD_TUNE_CMD_SEL);
  1484. }
  1485. } else {
  1486. /* choose clock tune */
  1487. if (host->top_base)
  1488. sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
  1489. PAD_RXDLY_SEL);
  1490. else
  1491. sdr_set_bits(host->base + tune_reg,
  1492. MSDC_PAD_TUNE_RXDLYSEL);
  1493. }
  1494. /* Configure to enable SDIO mode.
  1495. * it's must otherwise sdio cmd5 failed
  1496. */
  1497. sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
  1498. /* Config SDIO device detect interrupt function */
  1499. sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
  1500. sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
  1501. /* Configure to default data timeout */
  1502. sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
  1503. host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
  1504. host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
  1505. if (host->top_base) {
  1506. host->def_tune_para.emmc_top_control =
  1507. readl(host->top_base + EMMC_TOP_CONTROL);
  1508. host->def_tune_para.emmc_top_cmd =
  1509. readl(host->top_base + EMMC_TOP_CMD);
  1510. host->saved_tune_para.emmc_top_control =
  1511. readl(host->top_base + EMMC_TOP_CONTROL);
  1512. host->saved_tune_para.emmc_top_cmd =
  1513. readl(host->top_base + EMMC_TOP_CMD);
  1514. } else {
  1515. host->def_tune_para.pad_tune = readl(host->base + tune_reg);
  1516. host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
  1517. }
  1518. dev_dbg(host->dev, "init hardware done!");
  1519. }
  1520. static void msdc_deinit_hw(struct msdc_host *host)
  1521. {
  1522. u32 val;
  1523. if (host->internal_cd) {
  1524. /* Disabled card-detect */
  1525. sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
  1526. sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
  1527. }
  1528. /* Disable and clear all interrupts */
  1529. writel(0, host->base + MSDC_INTEN);
  1530. val = readl(host->base + MSDC_INT);
  1531. writel(val, host->base + MSDC_INT);
  1532. }
  1533. /* init gpd and bd list in msdc_drv_probe */
  1534. static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
  1535. {
  1536. struct mt_gpdma_desc *gpd = dma->gpd;
  1537. struct mt_bdma_desc *bd = dma->bd;
  1538. dma_addr_t dma_addr;
  1539. int i;
  1540. memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
  1541. dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
  1542. gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
  1543. /* gpd->next is must set for desc DMA
  1544. * That's why must alloc 2 gpd structure.
  1545. */
  1546. gpd->next = lower_32_bits(dma_addr);
  1547. if (host->dev_comp->support_64g)
  1548. gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
  1549. dma_addr = dma->bd_addr;
  1550. gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
  1551. if (host->dev_comp->support_64g)
  1552. gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
  1553. memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
  1554. for (i = 0; i < (MAX_BD_NUM - 1); i++) {
  1555. dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
  1556. bd[i].next = lower_32_bits(dma_addr);
  1557. if (host->dev_comp->support_64g)
  1558. bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
  1559. }
  1560. }
  1561. static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1562. {
  1563. struct msdc_host *host = mmc_priv(mmc);
  1564. int ret;
  1565. msdc_set_buswidth(host, ios->bus_width);
  1566. /* Suspend/Resume will do power off/on */
  1567. switch (ios->power_mode) {
  1568. case MMC_POWER_UP:
  1569. if (!IS_ERR(mmc->supply.vmmc)) {
  1570. msdc_init_hw(host);
  1571. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
  1572. ios->vdd);
  1573. if (ret) {
  1574. dev_err(host->dev, "Failed to set vmmc power!\n");
  1575. return;
  1576. }
  1577. }
  1578. break;
  1579. case MMC_POWER_ON:
  1580. if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
  1581. ret = regulator_enable(mmc->supply.vqmmc);
  1582. if (ret)
  1583. dev_err(host->dev, "Failed to set vqmmc power!\n");
  1584. else
  1585. host->vqmmc_enabled = true;
  1586. }
  1587. break;
  1588. case MMC_POWER_OFF:
  1589. if (!IS_ERR(mmc->supply.vmmc))
  1590. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  1591. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
  1592. regulator_disable(mmc->supply.vqmmc);
  1593. host->vqmmc_enabled = false;
  1594. }
  1595. break;
  1596. default:
  1597. break;
  1598. }
  1599. if (host->mclk != ios->clock || host->timing != ios->timing)
  1600. msdc_set_mclk(host, ios->timing, ios->clock);
  1601. }
  1602. static u32 test_delay_bit(u32 delay, u32 bit)
  1603. {
  1604. bit %= PAD_DELAY_MAX;
  1605. return delay & (1 << bit);
  1606. }
  1607. static int get_delay_len(u32 delay, u32 start_bit)
  1608. {
  1609. int i;
  1610. for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
  1611. if (test_delay_bit(delay, start_bit + i) == 0)
  1612. return i;
  1613. }
  1614. return PAD_DELAY_MAX - start_bit;
  1615. }
  1616. static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
  1617. {
  1618. int start = 0, len = 0;
  1619. int start_final = 0, len_final = 0;
  1620. u8 final_phase = 0xff;
  1621. struct msdc_delay_phase delay_phase = { 0, };
  1622. if (delay == 0) {
  1623. dev_err(host->dev, "phase error: [map:%x]\n", delay);
  1624. delay_phase.final_phase = final_phase;
  1625. return delay_phase;
  1626. }
  1627. while (start < PAD_DELAY_MAX) {
  1628. len = get_delay_len(delay, start);
  1629. if (len_final < len) {
  1630. start_final = start;
  1631. len_final = len;
  1632. }
  1633. start += len ? len : 1;
  1634. if (len >= 12 && start_final < 4)
  1635. break;
  1636. }
  1637. /* The rule is that to find the smallest delay cell */
  1638. if (start_final == 0)
  1639. final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
  1640. else
  1641. final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
  1642. dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
  1643. delay, len_final, final_phase);
  1644. delay_phase.maxlen = len_final;
  1645. delay_phase.start = start_final;
  1646. delay_phase.final_phase = final_phase;
  1647. return delay_phase;
  1648. }
  1649. static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
  1650. {
  1651. u32 tune_reg = host->dev_comp->pad_tune_reg;
  1652. if (host->top_base)
  1653. sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
  1654. value);
  1655. else
  1656. sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
  1657. value);
  1658. }
  1659. static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
  1660. {
  1661. u32 tune_reg = host->dev_comp->pad_tune_reg;
  1662. if (host->top_base)
  1663. sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
  1664. PAD_DAT_RD_RXDLY, value);
  1665. else
  1666. sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
  1667. value);
  1668. }
  1669. static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
  1670. {
  1671. struct msdc_host *host = mmc_priv(mmc);
  1672. u32 rise_delay = 0, fall_delay = 0;
  1673. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
  1674. struct msdc_delay_phase internal_delay_phase;
  1675. u8 final_delay, final_maxlen;
  1676. u32 internal_delay = 0;
  1677. u32 tune_reg = host->dev_comp->pad_tune_reg;
  1678. int cmd_err;
  1679. int i, j;
  1680. if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
  1681. mmc->ios.timing == MMC_TIMING_UHS_SDR104)
  1682. sdr_set_field(host->base + tune_reg,
  1683. MSDC_PAD_TUNE_CMDRRDLY,
  1684. host->hs200_cmd_int_delay);
  1685. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1686. for (i = 0 ; i < PAD_DELAY_MAX; i++) {
  1687. msdc_set_cmd_delay(host, i);
  1688. /*
  1689. * Using the same parameters, it may sometimes pass the test,
  1690. * but sometimes it may fail. To make sure the parameters are
  1691. * more stable, we test each set of parameters 3 times.
  1692. */
  1693. for (j = 0; j < 3; j++) {
  1694. mmc_send_tuning(mmc, opcode, &cmd_err);
  1695. if (!cmd_err) {
  1696. rise_delay |= (1 << i);
  1697. } else {
  1698. rise_delay &= ~(1 << i);
  1699. break;
  1700. }
  1701. }
  1702. }
  1703. final_rise_delay = get_best_delay(host, rise_delay);
  1704. /* if rising edge has enough margin, then do not scan falling edge */
  1705. if (final_rise_delay.maxlen >= 12 ||
  1706. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1707. goto skip_fall;
  1708. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1709. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1710. msdc_set_cmd_delay(host, i);
  1711. /*
  1712. * Using the same parameters, it may sometimes pass the test,
  1713. * but sometimes it may fail. To make sure the parameters are
  1714. * more stable, we test each set of parameters 3 times.
  1715. */
  1716. for (j = 0; j < 3; j++) {
  1717. mmc_send_tuning(mmc, opcode, &cmd_err);
  1718. if (!cmd_err) {
  1719. fall_delay |= (1 << i);
  1720. } else {
  1721. fall_delay &= ~(1 << i);
  1722. break;
  1723. }
  1724. }
  1725. }
  1726. final_fall_delay = get_best_delay(host, fall_delay);
  1727. skip_fall:
  1728. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1729. if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
  1730. final_maxlen = final_fall_delay.maxlen;
  1731. if (final_maxlen == final_rise_delay.maxlen) {
  1732. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1733. final_delay = final_rise_delay.final_phase;
  1734. } else {
  1735. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1736. final_delay = final_fall_delay.final_phase;
  1737. }
  1738. msdc_set_cmd_delay(host, final_delay);
  1739. if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
  1740. goto skip_internal;
  1741. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1742. sdr_set_field(host->base + tune_reg,
  1743. MSDC_PAD_TUNE_CMDRRDLY, i);
  1744. mmc_send_tuning(mmc, opcode, &cmd_err);
  1745. if (!cmd_err)
  1746. internal_delay |= (1 << i);
  1747. }
  1748. dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
  1749. internal_delay_phase = get_best_delay(host, internal_delay);
  1750. sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
  1751. internal_delay_phase.final_phase);
  1752. skip_internal:
  1753. dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
  1754. return final_delay == 0xff ? -EIO : 0;
  1755. }
  1756. static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
  1757. {
  1758. struct msdc_host *host = mmc_priv(mmc);
  1759. u32 cmd_delay = 0;
  1760. struct msdc_delay_phase final_cmd_delay = { 0,};
  1761. u8 final_delay;
  1762. int cmd_err;
  1763. int i, j;
  1764. /* select EMMC50 PAD CMD tune */
  1765. sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
  1766. sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
  1767. if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
  1768. mmc->ios.timing == MMC_TIMING_UHS_SDR104)
  1769. sdr_set_field(host->base + MSDC_PAD_TUNE,
  1770. MSDC_PAD_TUNE_CMDRRDLY,
  1771. host->hs200_cmd_int_delay);
  1772. if (host->hs400_cmd_resp_sel_rising)
  1773. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1774. else
  1775. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1776. for (i = 0 ; i < PAD_DELAY_MAX; i++) {
  1777. sdr_set_field(host->base + PAD_CMD_TUNE,
  1778. PAD_CMD_TUNE_RX_DLY3, i);
  1779. /*
  1780. * Using the same parameters, it may sometimes pass the test,
  1781. * but sometimes it may fail. To make sure the parameters are
  1782. * more stable, we test each set of parameters 3 times.
  1783. */
  1784. for (j = 0; j < 3; j++) {
  1785. mmc_send_tuning(mmc, opcode, &cmd_err);
  1786. if (!cmd_err) {
  1787. cmd_delay |= (1 << i);
  1788. } else {
  1789. cmd_delay &= ~(1 << i);
  1790. break;
  1791. }
  1792. }
  1793. }
  1794. final_cmd_delay = get_best_delay(host, cmd_delay);
  1795. sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
  1796. final_cmd_delay.final_phase);
  1797. final_delay = final_cmd_delay.final_phase;
  1798. dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
  1799. return final_delay == 0xff ? -EIO : 0;
  1800. }
  1801. static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
  1802. {
  1803. struct msdc_host *host = mmc_priv(mmc);
  1804. u32 rise_delay = 0, fall_delay = 0;
  1805. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
  1806. u8 final_delay, final_maxlen;
  1807. int i, ret;
  1808. sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
  1809. host->latch_ck);
  1810. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
  1811. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
  1812. for (i = 0 ; i < PAD_DELAY_MAX; i++) {
  1813. msdc_set_data_delay(host, i);
  1814. ret = mmc_send_tuning(mmc, opcode, NULL);
  1815. if (!ret)
  1816. rise_delay |= (1 << i);
  1817. }
  1818. final_rise_delay = get_best_delay(host, rise_delay);
  1819. /* if rising edge has enough margin, then do not scan falling edge */
  1820. if (final_rise_delay.maxlen >= 12 ||
  1821. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1822. goto skip_fall;
  1823. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
  1824. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
  1825. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1826. msdc_set_data_delay(host, i);
  1827. ret = mmc_send_tuning(mmc, opcode, NULL);
  1828. if (!ret)
  1829. fall_delay |= (1 << i);
  1830. }
  1831. final_fall_delay = get_best_delay(host, fall_delay);
  1832. skip_fall:
  1833. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1834. if (final_maxlen == final_rise_delay.maxlen) {
  1835. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
  1836. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
  1837. final_delay = final_rise_delay.final_phase;
  1838. } else {
  1839. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
  1840. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
  1841. final_delay = final_fall_delay.final_phase;
  1842. }
  1843. msdc_set_data_delay(host, final_delay);
  1844. dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
  1845. return final_delay == 0xff ? -EIO : 0;
  1846. }
  1847. /*
  1848. * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
  1849. * together, which can save the tuning time.
  1850. */
  1851. static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
  1852. {
  1853. struct msdc_host *host = mmc_priv(mmc);
  1854. u32 rise_delay = 0, fall_delay = 0;
  1855. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
  1856. u8 final_delay, final_maxlen;
  1857. int i, ret;
  1858. sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
  1859. host->latch_ck);
  1860. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1861. sdr_clr_bits(host->base + MSDC_IOCON,
  1862. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1863. for (i = 0 ; i < PAD_DELAY_MAX; i++) {
  1864. msdc_set_cmd_delay(host, i);
  1865. msdc_set_data_delay(host, i);
  1866. ret = mmc_send_tuning(mmc, opcode, NULL);
  1867. if (!ret)
  1868. rise_delay |= (1 << i);
  1869. }
  1870. final_rise_delay = get_best_delay(host, rise_delay);
  1871. /* if rising edge has enough margin, then do not scan falling edge */
  1872. if (final_rise_delay.maxlen >= 12 ||
  1873. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1874. goto skip_fall;
  1875. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1876. sdr_set_bits(host->base + MSDC_IOCON,
  1877. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1878. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1879. msdc_set_cmd_delay(host, i);
  1880. msdc_set_data_delay(host, i);
  1881. ret = mmc_send_tuning(mmc, opcode, NULL);
  1882. if (!ret)
  1883. fall_delay |= (1 << i);
  1884. }
  1885. final_fall_delay = get_best_delay(host, fall_delay);
  1886. skip_fall:
  1887. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1888. if (final_maxlen == final_rise_delay.maxlen) {
  1889. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1890. sdr_clr_bits(host->base + MSDC_IOCON,
  1891. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1892. final_delay = final_rise_delay.final_phase;
  1893. } else {
  1894. sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
  1895. sdr_set_bits(host->base + MSDC_IOCON,
  1896. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1897. final_delay = final_fall_delay.final_phase;
  1898. }
  1899. msdc_set_cmd_delay(host, final_delay);
  1900. msdc_set_data_delay(host, final_delay);
  1901. dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
  1902. return final_delay == 0xff ? -EIO : 0;
  1903. }
  1904. static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
  1905. {
  1906. struct msdc_host *host = mmc_priv(mmc);
  1907. int ret;
  1908. u32 tune_reg = host->dev_comp->pad_tune_reg;
  1909. if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
  1910. ret = msdc_tune_together(mmc, opcode);
  1911. if (host->hs400_mode) {
  1912. sdr_clr_bits(host->base + MSDC_IOCON,
  1913. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1914. msdc_set_data_delay(host, 0);
  1915. }
  1916. goto tune_done;
  1917. }
  1918. if (host->hs400_mode &&
  1919. host->dev_comp->hs400_tune)
  1920. ret = hs400_tune_response(mmc, opcode);
  1921. else
  1922. ret = msdc_tune_response(mmc, opcode);
  1923. if (ret == -EIO) {
  1924. dev_err(host->dev, "Tune response fail!\n");
  1925. return ret;
  1926. }
  1927. if (host->hs400_mode == false) {
  1928. ret = msdc_tune_data(mmc, opcode);
  1929. if (ret == -EIO)
  1930. dev_err(host->dev, "Tune data fail!\n");
  1931. }
  1932. tune_done:
  1933. host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
  1934. host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
  1935. host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
  1936. if (host->top_base) {
  1937. host->saved_tune_para.emmc_top_control = readl(host->top_base +
  1938. EMMC_TOP_CONTROL);
  1939. host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
  1940. EMMC_TOP_CMD);
  1941. }
  1942. return ret;
  1943. }
  1944. static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
  1945. {
  1946. struct msdc_host *host = mmc_priv(mmc);
  1947. host->hs400_mode = true;
  1948. if (host->top_base)
  1949. writel(host->hs400_ds_delay,
  1950. host->top_base + EMMC50_PAD_DS_TUNE);
  1951. else
  1952. writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
  1953. /* hs400 mode must set it to 0 */
  1954. sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
  1955. /* to improve read performance, set outstanding to 2 */
  1956. sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
  1957. return 0;
  1958. }
  1959. static void msdc_hw_reset(struct mmc_host *mmc)
  1960. {
  1961. struct msdc_host *host = mmc_priv(mmc);
  1962. sdr_set_bits(host->base + EMMC_IOCON, 1);
  1963. udelay(10); /* 10us is enough */
  1964. sdr_clr_bits(host->base + EMMC_IOCON, 1);
  1965. }
  1966. static void msdc_ack_sdio_irq(struct mmc_host *mmc)
  1967. {
  1968. unsigned long flags;
  1969. struct msdc_host *host = mmc_priv(mmc);
  1970. spin_lock_irqsave(&host->lock, flags);
  1971. __msdc_enable_sdio_irq(host, 1);
  1972. spin_unlock_irqrestore(&host->lock, flags);
  1973. }
  1974. static int msdc_get_cd(struct mmc_host *mmc)
  1975. {
  1976. struct msdc_host *host = mmc_priv(mmc);
  1977. int val;
  1978. if (mmc->caps & MMC_CAP_NONREMOVABLE)
  1979. return 1;
  1980. if (!host->internal_cd)
  1981. return mmc_gpio_get_cd(mmc);
  1982. val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
  1983. if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
  1984. return !!val;
  1985. else
  1986. return !val;
  1987. }
  1988. static void msdc_cqe_enable(struct mmc_host *mmc)
  1989. {
  1990. struct msdc_host *host = mmc_priv(mmc);
  1991. /* enable cmdq irq */
  1992. writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
  1993. /* enable busy check */
  1994. sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
  1995. /* default write data / busy timeout 20s */
  1996. msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
  1997. /* default read data timeout 1s */
  1998. msdc_set_timeout(host, 1000000000ULL, 0);
  1999. }
  2000. static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
  2001. {
  2002. struct msdc_host *host = mmc_priv(mmc);
  2003. unsigned int val = 0;
  2004. /* disable cmdq irq */
  2005. sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
  2006. /* disable busy check */
  2007. sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
  2008. if (recovery) {
  2009. sdr_set_field(host->base + MSDC_DMA_CTRL,
  2010. MSDC_DMA_CTRL_STOP, 1);
  2011. if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
  2012. !(val & MSDC_DMA_CFG_STS), 1, 3000)))
  2013. return;
  2014. msdc_reset_hw(host);
  2015. }
  2016. }
  2017. static void msdc_cqe_pre_enable(struct mmc_host *mmc)
  2018. {
  2019. struct cqhci_host *cq_host = mmc->cqe_private;
  2020. u32 reg;
  2021. reg = cqhci_readl(cq_host, CQHCI_CFG);
  2022. reg |= CQHCI_ENABLE;
  2023. cqhci_writel(cq_host, reg, CQHCI_CFG);
  2024. }
  2025. static void msdc_cqe_post_disable(struct mmc_host *mmc)
  2026. {
  2027. struct cqhci_host *cq_host = mmc->cqe_private;
  2028. u32 reg;
  2029. reg = cqhci_readl(cq_host, CQHCI_CFG);
  2030. reg &= ~CQHCI_ENABLE;
  2031. cqhci_writel(cq_host, reg, CQHCI_CFG);
  2032. }
  2033. static const struct mmc_host_ops mt_msdc_ops = {
  2034. .post_req = msdc_post_req,
  2035. .pre_req = msdc_pre_req,
  2036. .request = msdc_ops_request,
  2037. .set_ios = msdc_ops_set_ios,
  2038. .get_ro = mmc_gpio_get_ro,
  2039. .get_cd = msdc_get_cd,
  2040. .enable_sdio_irq = msdc_enable_sdio_irq,
  2041. .ack_sdio_irq = msdc_ack_sdio_irq,
  2042. .start_signal_voltage_switch = msdc_ops_switch_volt,
  2043. .card_busy = msdc_card_busy,
  2044. .execute_tuning = msdc_execute_tuning,
  2045. .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
  2046. .hw_reset = msdc_hw_reset,
  2047. };
  2048. static const struct cqhci_host_ops msdc_cmdq_ops = {
  2049. .enable = msdc_cqe_enable,
  2050. .disable = msdc_cqe_disable,
  2051. .pre_enable = msdc_cqe_pre_enable,
  2052. .post_disable = msdc_cqe_post_disable,
  2053. };
  2054. static void msdc_of_property_parse(struct platform_device *pdev,
  2055. struct msdc_host *host)
  2056. {
  2057. of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
  2058. &host->latch_ck);
  2059. of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
  2060. &host->hs400_ds_delay);
  2061. of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
  2062. &host->hs200_cmd_int_delay);
  2063. of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
  2064. &host->hs400_cmd_int_delay);
  2065. if (of_property_read_bool(pdev->dev.of_node,
  2066. "mediatek,hs400-cmd-resp-sel-rising"))
  2067. host->hs400_cmd_resp_sel_rising = true;
  2068. else
  2069. host->hs400_cmd_resp_sel_rising = false;
  2070. if (of_property_read_bool(pdev->dev.of_node,
  2071. "supports-cqe"))
  2072. host->cqhci = true;
  2073. else
  2074. host->cqhci = false;
  2075. }
  2076. static int msdc_drv_probe(struct platform_device *pdev)
  2077. {
  2078. struct mmc_host *mmc;
  2079. struct msdc_host *host;
  2080. struct resource *res;
  2081. int ret;
  2082. if (!pdev->dev.of_node) {
  2083. dev_err(&pdev->dev, "No DT found\n");
  2084. return -EINVAL;
  2085. }
  2086. /* Allocate MMC host for this device */
  2087. mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
  2088. if (!mmc)
  2089. return -ENOMEM;
  2090. host = mmc_priv(mmc);
  2091. ret = mmc_of_parse(mmc);
  2092. if (ret)
  2093. goto host_free;
  2094. host->base = devm_platform_ioremap_resource(pdev, 0);
  2095. if (IS_ERR(host->base)) {
  2096. ret = PTR_ERR(host->base);
  2097. goto host_free;
  2098. }
  2099. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  2100. if (res) {
  2101. host->top_base = devm_ioremap_resource(&pdev->dev, res);
  2102. if (IS_ERR(host->top_base))
  2103. host->top_base = NULL;
  2104. }
  2105. ret = mmc_regulator_get_supply(mmc);
  2106. if (ret)
  2107. goto host_free;
  2108. host->src_clk = devm_clk_get(&pdev->dev, "source");
  2109. if (IS_ERR(host->src_clk)) {
  2110. ret = PTR_ERR(host->src_clk);
  2111. goto host_free;
  2112. }
  2113. host->h_clk = devm_clk_get(&pdev->dev, "hclk");
  2114. if (IS_ERR(host->h_clk)) {
  2115. ret = PTR_ERR(host->h_clk);
  2116. goto host_free;
  2117. }
  2118. host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
  2119. if (IS_ERR(host->bus_clk))
  2120. host->bus_clk = NULL;
  2121. /*source clock control gate is optional clock*/
  2122. host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
  2123. if (IS_ERR(host->src_clk_cg))
  2124. host->src_clk_cg = NULL;
  2125. host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
  2126. "hrst");
  2127. if (IS_ERR(host->reset))
  2128. return PTR_ERR(host->reset);
  2129. host->irq = platform_get_irq(pdev, 0);
  2130. if (host->irq < 0) {
  2131. ret = -EINVAL;
  2132. goto host_free;
  2133. }
  2134. host->pinctrl = devm_pinctrl_get(&pdev->dev);
  2135. if (IS_ERR(host->pinctrl)) {
  2136. ret = PTR_ERR(host->pinctrl);
  2137. dev_err(&pdev->dev, "Cannot find pinctrl!\n");
  2138. goto host_free;
  2139. }
  2140. host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
  2141. if (IS_ERR(host->pins_default)) {
  2142. ret = PTR_ERR(host->pins_default);
  2143. dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
  2144. goto host_free;
  2145. }
  2146. host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
  2147. if (IS_ERR(host->pins_uhs)) {
  2148. ret = PTR_ERR(host->pins_uhs);
  2149. dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
  2150. goto host_free;
  2151. }
  2152. msdc_of_property_parse(pdev, host);
  2153. host->dev = &pdev->dev;
  2154. host->dev_comp = of_device_get_match_data(&pdev->dev);
  2155. host->src_clk_freq = clk_get_rate(host->src_clk);
  2156. /* Set host parameters to mmc */
  2157. mmc->ops = &mt_msdc_ops;
  2158. if (host->dev_comp->clk_div_bits == 8)
  2159. mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
  2160. else
  2161. mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
  2162. if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
  2163. !mmc_can_gpio_cd(mmc) &&
  2164. host->dev_comp->use_internal_cd) {
  2165. /*
  2166. * Is removable but no GPIO declared, so
  2167. * use internal functionality.
  2168. */
  2169. host->internal_cd = true;
  2170. }
  2171. if (mmc->caps & MMC_CAP_SDIO_IRQ)
  2172. mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
  2173. mmc->caps |= MMC_CAP_CMD23;
  2174. if (host->cqhci)
  2175. mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
  2176. /* MMC core transfer sizes tunable parameters */
  2177. mmc->max_segs = MAX_BD_NUM;
  2178. if (host->dev_comp->support_64g)
  2179. mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
  2180. else
  2181. mmc->max_seg_size = BDMA_DESC_BUFLEN;
  2182. mmc->max_blk_size = 2048;
  2183. mmc->max_req_size = 512 * 1024;
  2184. mmc->max_blk_count = mmc->max_req_size / 512;
  2185. if (host->dev_comp->support_64g)
  2186. host->dma_mask = DMA_BIT_MASK(36);
  2187. else
  2188. host->dma_mask = DMA_BIT_MASK(32);
  2189. mmc_dev(mmc)->dma_mask = &host->dma_mask;
  2190. host->timeout_clks = 3 * 1048576;
  2191. host->dma.gpd = dma_alloc_coherent(&pdev->dev,
  2192. 2 * sizeof(struct mt_gpdma_desc),
  2193. &host->dma.gpd_addr, GFP_KERNEL);
  2194. host->dma.bd = dma_alloc_coherent(&pdev->dev,
  2195. MAX_BD_NUM * sizeof(struct mt_bdma_desc),
  2196. &host->dma.bd_addr, GFP_KERNEL);
  2197. if (!host->dma.gpd || !host->dma.bd) {
  2198. ret = -ENOMEM;
  2199. goto release_mem;
  2200. }
  2201. msdc_init_gpd_bd(host, &host->dma);
  2202. INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
  2203. spin_lock_init(&host->lock);
  2204. platform_set_drvdata(pdev, mmc);
  2205. msdc_ungate_clock(host);
  2206. msdc_init_hw(host);
  2207. if (mmc->caps2 & MMC_CAP2_CQE) {
  2208. host->cq_host = devm_kzalloc(mmc->parent,
  2209. sizeof(*host->cq_host),
  2210. GFP_KERNEL);
  2211. if (!host->cq_host) {
  2212. ret = -ENOMEM;
  2213. goto host_free;
  2214. }
  2215. host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  2216. host->cq_host->mmio = host->base + 0x800;
  2217. host->cq_host->ops = &msdc_cmdq_ops;
  2218. ret = cqhci_init(host->cq_host, mmc, true);
  2219. if (ret)
  2220. goto host_free;
  2221. mmc->max_segs = 128;
  2222. /* cqhci 16bit length */
  2223. /* 0 size, means 65536 so we don't have to -1 here */
  2224. mmc->max_seg_size = 64 * 1024;
  2225. }
  2226. ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
  2227. IRQF_TRIGGER_NONE, pdev->name, host);
  2228. if (ret)
  2229. goto release;
  2230. pm_runtime_set_active(host->dev);
  2231. pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
  2232. pm_runtime_use_autosuspend(host->dev);
  2233. pm_runtime_enable(host->dev);
  2234. ret = mmc_add_host(mmc);
  2235. if (ret)
  2236. goto end;
  2237. return 0;
  2238. end:
  2239. pm_runtime_disable(host->dev);
  2240. release:
  2241. platform_set_drvdata(pdev, NULL);
  2242. msdc_deinit_hw(host);
  2243. msdc_gate_clock(host);
  2244. release_mem:
  2245. if (host->dma.gpd)
  2246. dma_free_coherent(&pdev->dev,
  2247. 2 * sizeof(struct mt_gpdma_desc),
  2248. host->dma.gpd, host->dma.gpd_addr);
  2249. if (host->dma.bd)
  2250. dma_free_coherent(&pdev->dev,
  2251. MAX_BD_NUM * sizeof(struct mt_bdma_desc),
  2252. host->dma.bd, host->dma.bd_addr);
  2253. host_free:
  2254. mmc_free_host(mmc);
  2255. return ret;
  2256. }
  2257. static int msdc_drv_remove(struct platform_device *pdev)
  2258. {
  2259. struct mmc_host *mmc;
  2260. struct msdc_host *host;
  2261. mmc = platform_get_drvdata(pdev);
  2262. host = mmc_priv(mmc);
  2263. pm_runtime_get_sync(host->dev);
  2264. platform_set_drvdata(pdev, NULL);
  2265. mmc_remove_host(mmc);
  2266. msdc_deinit_hw(host);
  2267. msdc_gate_clock(host);
  2268. pm_runtime_disable(host->dev);
  2269. pm_runtime_put_noidle(host->dev);
  2270. dma_free_coherent(&pdev->dev,
  2271. 2 * sizeof(struct mt_gpdma_desc),
  2272. host->dma.gpd, host->dma.gpd_addr);
  2273. dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
  2274. host->dma.bd, host->dma.bd_addr);
  2275. mmc_free_host(mmc);
  2276. return 0;
  2277. }
  2278. static void msdc_save_reg(struct msdc_host *host)
  2279. {
  2280. u32 tune_reg = host->dev_comp->pad_tune_reg;
  2281. host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
  2282. host->save_para.iocon = readl(host->base + MSDC_IOCON);
  2283. host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
  2284. host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
  2285. host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
  2286. host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
  2287. host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
  2288. host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
  2289. host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
  2290. host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
  2291. host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
  2292. if (host->top_base) {
  2293. host->save_para.emmc_top_control =
  2294. readl(host->top_base + EMMC_TOP_CONTROL);
  2295. host->save_para.emmc_top_cmd =
  2296. readl(host->top_base + EMMC_TOP_CMD);
  2297. host->save_para.emmc50_pad_ds_tune =
  2298. readl(host->top_base + EMMC50_PAD_DS_TUNE);
  2299. } else {
  2300. host->save_para.pad_tune = readl(host->base + tune_reg);
  2301. }
  2302. }
  2303. static void msdc_restore_reg(struct msdc_host *host)
  2304. {
  2305. struct mmc_host *mmc = mmc_from_priv(host);
  2306. u32 tune_reg = host->dev_comp->pad_tune_reg;
  2307. writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
  2308. writel(host->save_para.iocon, host->base + MSDC_IOCON);
  2309. writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
  2310. writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
  2311. writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
  2312. writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
  2313. writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
  2314. writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
  2315. writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
  2316. writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
  2317. writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
  2318. if (host->top_base) {
  2319. writel(host->save_para.emmc_top_control,
  2320. host->top_base + EMMC_TOP_CONTROL);
  2321. writel(host->save_para.emmc_top_cmd,
  2322. host->top_base + EMMC_TOP_CMD);
  2323. writel(host->save_para.emmc50_pad_ds_tune,
  2324. host->top_base + EMMC50_PAD_DS_TUNE);
  2325. } else {
  2326. writel(host->save_para.pad_tune, host->base + tune_reg);
  2327. }
  2328. if (sdio_irq_claimed(mmc))
  2329. __msdc_enable_sdio_irq(host, 1);
  2330. }
  2331. static int __maybe_unused msdc_runtime_suspend(struct device *dev)
  2332. {
  2333. struct mmc_host *mmc = dev_get_drvdata(dev);
  2334. struct msdc_host *host = mmc_priv(mmc);
  2335. msdc_save_reg(host);
  2336. msdc_gate_clock(host);
  2337. return 0;
  2338. }
  2339. static int __maybe_unused msdc_runtime_resume(struct device *dev)
  2340. {
  2341. struct mmc_host *mmc = dev_get_drvdata(dev);
  2342. struct msdc_host *host = mmc_priv(mmc);
  2343. msdc_ungate_clock(host);
  2344. msdc_restore_reg(host);
  2345. return 0;
  2346. }
  2347. static int __maybe_unused msdc_suspend(struct device *dev)
  2348. {
  2349. struct mmc_host *mmc = dev_get_drvdata(dev);
  2350. int ret;
  2351. if (mmc->caps2 & MMC_CAP2_CQE) {
  2352. ret = cqhci_suspend(mmc);
  2353. if (ret)
  2354. return ret;
  2355. }
  2356. return pm_runtime_force_suspend(dev);
  2357. }
  2358. static int __maybe_unused msdc_resume(struct device *dev)
  2359. {
  2360. return pm_runtime_force_resume(dev);
  2361. }
  2362. static const struct dev_pm_ops msdc_dev_pm_ops = {
  2363. SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
  2364. SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
  2365. };
  2366. static struct platform_driver mt_msdc_driver = {
  2367. .probe = msdc_drv_probe,
  2368. .remove = msdc_drv_remove,
  2369. .driver = {
  2370. .name = "mtk-msdc",
  2371. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  2372. .of_match_table = msdc_of_ids,
  2373. .pm = &msdc_dev_pm_ops,
  2374. },
  2375. };
  2376. module_platform_driver(mt_msdc_driver);
  2377. MODULE_LICENSE("GPL v2");
  2378. MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");