mmci.c 60 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
  4. *
  5. * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  6. * Copyright (C) 2010 ST-Ericsson SA
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/ioport.h>
  12. #include <linux/device.h>
  13. #include <linux/io.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel.h>
  16. #include <linux/slab.h>
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. #include <linux/highmem.h>
  20. #include <linux/log2.h>
  21. #include <linux/mmc/mmc.h>
  22. #include <linux/mmc/pm.h>
  23. #include <linux/mmc/host.h>
  24. #include <linux/mmc/card.h>
  25. #include <linux/mmc/sd.h>
  26. #include <linux/mmc/slot-gpio.h>
  27. #include <linux/amba/bus.h>
  28. #include <linux/clk.h>
  29. #include <linux/scatterlist.h>
  30. #include <linux/of.h>
  31. #include <linux/regulator/consumer.h>
  32. #include <linux/dmaengine.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/amba/mmci.h>
  35. #include <linux/pm_runtime.h>
  36. #include <linux/types.h>
  37. #include <linux/pinctrl/consumer.h>
  38. #include <linux/reset.h>
  39. #include <asm/div64.h>
  40. #include <asm/io.h>
  41. #include "mmci.h"
  42. #define DRIVER_NAME "mmci-pl18x"
  43. static void mmci_variant_init(struct mmci_host *host);
  44. static void ux500_variant_init(struct mmci_host *host);
  45. static void ux500v2_variant_init(struct mmci_host *host);
  46. static unsigned int fmax = 515633;
  47. static struct variant_data variant_arm = {
  48. .fifosize = 16 * 4,
  49. .fifohalfsize = 8 * 4,
  50. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  51. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  52. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  53. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  54. .datalength_bits = 16,
  55. .datactrl_blocksz = 11,
  56. .pwrreg_powerup = MCI_PWR_UP,
  57. .f_max = 100000000,
  58. .reversed_irq_handling = true,
  59. .mmcimask1 = true,
  60. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  61. .start_err = MCI_STARTBITERR,
  62. .opendrain = MCI_ROD,
  63. .init = mmci_variant_init,
  64. };
  65. static struct variant_data variant_arm_extended_fifo = {
  66. .fifosize = 128 * 4,
  67. .fifohalfsize = 64 * 4,
  68. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  69. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  70. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  71. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  72. .datalength_bits = 16,
  73. .datactrl_blocksz = 11,
  74. .pwrreg_powerup = MCI_PWR_UP,
  75. .f_max = 100000000,
  76. .mmcimask1 = true,
  77. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  78. .start_err = MCI_STARTBITERR,
  79. .opendrain = MCI_ROD,
  80. .init = mmci_variant_init,
  81. };
  82. static struct variant_data variant_arm_extended_fifo_hwfc = {
  83. .fifosize = 128 * 4,
  84. .fifohalfsize = 64 * 4,
  85. .clkreg_enable = MCI_ARM_HWFCEN,
  86. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  87. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  88. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  89. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  90. .datalength_bits = 16,
  91. .datactrl_blocksz = 11,
  92. .pwrreg_powerup = MCI_PWR_UP,
  93. .f_max = 100000000,
  94. .mmcimask1 = true,
  95. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  96. .start_err = MCI_STARTBITERR,
  97. .opendrain = MCI_ROD,
  98. .init = mmci_variant_init,
  99. };
  100. static struct variant_data variant_u300 = {
  101. .fifosize = 16 * 4,
  102. .fifohalfsize = 8 * 4,
  103. .clkreg_enable = MCI_ST_U300_HWFCEN,
  104. .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  105. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  106. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  107. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  108. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  109. .datalength_bits = 16,
  110. .datactrl_blocksz = 11,
  111. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  112. .st_sdio = true,
  113. .pwrreg_powerup = MCI_PWR_ON,
  114. .f_max = 100000000,
  115. .signal_direction = true,
  116. .pwrreg_clkgate = true,
  117. .pwrreg_nopower = true,
  118. .mmcimask1 = true,
  119. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  120. .start_err = MCI_STARTBITERR,
  121. .opendrain = MCI_OD,
  122. .init = mmci_variant_init,
  123. };
  124. static struct variant_data variant_nomadik = {
  125. .fifosize = 16 * 4,
  126. .fifohalfsize = 8 * 4,
  127. .clkreg = MCI_CLK_ENABLE,
  128. .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  129. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  130. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  131. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  132. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  133. .datalength_bits = 24,
  134. .datactrl_blocksz = 11,
  135. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  136. .st_sdio = true,
  137. .st_clkdiv = true,
  138. .pwrreg_powerup = MCI_PWR_ON,
  139. .f_max = 100000000,
  140. .signal_direction = true,
  141. .pwrreg_clkgate = true,
  142. .pwrreg_nopower = true,
  143. .mmcimask1 = true,
  144. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  145. .start_err = MCI_STARTBITERR,
  146. .opendrain = MCI_OD,
  147. .init = mmci_variant_init,
  148. };
  149. static struct variant_data variant_ux500 = {
  150. .fifosize = 30 * 4,
  151. .fifohalfsize = 8 * 4,
  152. .clkreg = MCI_CLK_ENABLE,
  153. .clkreg_enable = MCI_ST_UX500_HWFCEN,
  154. .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  155. .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
  156. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  157. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  158. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  159. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  160. .datalength_bits = 24,
  161. .datactrl_blocksz = 11,
  162. .datactrl_any_blocksz = true,
  163. .dma_power_of_2 = true,
  164. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  165. .st_sdio = true,
  166. .st_clkdiv = true,
  167. .pwrreg_powerup = MCI_PWR_ON,
  168. .f_max = 100000000,
  169. .signal_direction = true,
  170. .pwrreg_clkgate = true,
  171. .busy_detect = true,
  172. .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
  173. .busy_detect_flag = MCI_ST_CARDBUSY,
  174. .busy_detect_mask = MCI_ST_BUSYENDMASK,
  175. .pwrreg_nopower = true,
  176. .mmcimask1 = true,
  177. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  178. .start_err = MCI_STARTBITERR,
  179. .opendrain = MCI_OD,
  180. .init = ux500_variant_init,
  181. };
  182. static struct variant_data variant_ux500v2 = {
  183. .fifosize = 30 * 4,
  184. .fifohalfsize = 8 * 4,
  185. .clkreg = MCI_CLK_ENABLE,
  186. .clkreg_enable = MCI_ST_UX500_HWFCEN,
  187. .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  188. .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
  189. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  190. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  191. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  192. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  193. .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
  194. .datalength_bits = 24,
  195. .datactrl_blocksz = 11,
  196. .datactrl_any_blocksz = true,
  197. .dma_power_of_2 = true,
  198. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  199. .st_sdio = true,
  200. .st_clkdiv = true,
  201. .pwrreg_powerup = MCI_PWR_ON,
  202. .f_max = 100000000,
  203. .signal_direction = true,
  204. .pwrreg_clkgate = true,
  205. .busy_detect = true,
  206. .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
  207. .busy_detect_flag = MCI_ST_CARDBUSY,
  208. .busy_detect_mask = MCI_ST_BUSYENDMASK,
  209. .pwrreg_nopower = true,
  210. .mmcimask1 = true,
  211. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  212. .start_err = MCI_STARTBITERR,
  213. .opendrain = MCI_OD,
  214. .init = ux500v2_variant_init,
  215. };
  216. static struct variant_data variant_stm32 = {
  217. .fifosize = 32 * 4,
  218. .fifohalfsize = 8 * 4,
  219. .clkreg = MCI_CLK_ENABLE,
  220. .clkreg_enable = MCI_ST_UX500_HWFCEN,
  221. .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
  222. .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
  223. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  224. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  225. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  226. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  227. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  228. .datalength_bits = 24,
  229. .datactrl_blocksz = 11,
  230. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  231. .st_sdio = true,
  232. .st_clkdiv = true,
  233. .pwrreg_powerup = MCI_PWR_ON,
  234. .f_max = 48000000,
  235. .pwrreg_clkgate = true,
  236. .pwrreg_nopower = true,
  237. .init = mmci_variant_init,
  238. };
  239. static struct variant_data variant_stm32_sdmmc = {
  240. .fifosize = 16 * 4,
  241. .fifohalfsize = 8 * 4,
  242. .f_max = 208000000,
  243. .stm32_clkdiv = true,
  244. .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
  245. .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
  246. .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
  247. .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
  248. .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
  249. .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
  250. .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
  251. .datactrl_first = true,
  252. .datacnt_useless = true,
  253. .datalength_bits = 25,
  254. .datactrl_blocksz = 14,
  255. .datactrl_any_blocksz = true,
  256. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  257. .stm32_idmabsize_mask = GENMASK(12, 5),
  258. .busy_timeout = true,
  259. .busy_detect = true,
  260. .busy_detect_flag = MCI_STM32_BUSYD0,
  261. .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK,
  262. .init = sdmmc_variant_init,
  263. };
  264. static struct variant_data variant_stm32_sdmmcv2 = {
  265. .fifosize = 16 * 4,
  266. .fifohalfsize = 8 * 4,
  267. .f_max = 208000000,
  268. .stm32_clkdiv = true,
  269. .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
  270. .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
  271. .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
  272. .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
  273. .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
  274. .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
  275. .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
  276. .datactrl_first = true,
  277. .datacnt_useless = true,
  278. .datalength_bits = 25,
  279. .datactrl_blocksz = 14,
  280. .datactrl_any_blocksz = true,
  281. .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
  282. .stm32_idmabsize_mask = GENMASK(16, 5),
  283. .dma_lli = true,
  284. .busy_timeout = true,
  285. .busy_detect = true,
  286. .busy_detect_flag = MCI_STM32_BUSYD0,
  287. .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK,
  288. .init = sdmmc_variant_init,
  289. };
  290. static struct variant_data variant_qcom = {
  291. .fifosize = 16 * 4,
  292. .fifohalfsize = 8 * 4,
  293. .clkreg = MCI_CLK_ENABLE,
  294. .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
  295. MCI_QCOM_CLK_SELECT_IN_FBCLK,
  296. .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
  297. .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
  298. .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
  299. .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  300. .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
  301. .cmdreg_srsp = MCI_CPSM_RESPONSE,
  302. .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
  303. .datalength_bits = 24,
  304. .datactrl_blocksz = 11,
  305. .datactrl_any_blocksz = true,
  306. .pwrreg_powerup = MCI_PWR_UP,
  307. .f_max = 208000000,
  308. .explicit_mclk_control = true,
  309. .qcom_fifo = true,
  310. .qcom_dml = true,
  311. .mmcimask1 = true,
  312. .irq_pio_mask = MCI_IRQ_PIO_MASK,
  313. .start_err = MCI_STARTBITERR,
  314. .opendrain = MCI_ROD,
  315. .init = qcom_variant_init,
  316. };
  317. /* Busy detection for the ST Micro variant */
  318. static int mmci_card_busy(struct mmc_host *mmc)
  319. {
  320. struct mmci_host *host = mmc_priv(mmc);
  321. unsigned long flags;
  322. int busy = 0;
  323. spin_lock_irqsave(&host->lock, flags);
  324. if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
  325. busy = 1;
  326. spin_unlock_irqrestore(&host->lock, flags);
  327. return busy;
  328. }
  329. static void mmci_reg_delay(struct mmci_host *host)
  330. {
  331. /*
  332. * According to the spec, at least three feedback clock cycles
  333. * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
  334. * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
  335. * Worst delay time during card init is at 100 kHz => 30 us.
  336. * Worst delay time when up and running is at 25 MHz => 120 ns.
  337. */
  338. if (host->cclk < 25000000)
  339. udelay(30);
  340. else
  341. ndelay(120);
  342. }
  343. /*
  344. * This must be called with host->lock held
  345. */
  346. void mmci_write_clkreg(struct mmci_host *host, u32 clk)
  347. {
  348. if (host->clk_reg != clk) {
  349. host->clk_reg = clk;
  350. writel(clk, host->base + MMCICLOCK);
  351. }
  352. }
  353. /*
  354. * This must be called with host->lock held
  355. */
  356. void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
  357. {
  358. if (host->pwr_reg != pwr) {
  359. host->pwr_reg = pwr;
  360. writel(pwr, host->base + MMCIPOWER);
  361. }
  362. }
  363. /*
  364. * This must be called with host->lock held
  365. */
  366. static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
  367. {
  368. /* Keep busy mode in DPSM if enabled */
  369. datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
  370. if (host->datactrl_reg != datactrl) {
  371. host->datactrl_reg = datactrl;
  372. writel(datactrl, host->base + MMCIDATACTRL);
  373. }
  374. }
  375. /*
  376. * This must be called with host->lock held
  377. */
  378. static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
  379. {
  380. struct variant_data *variant = host->variant;
  381. u32 clk = variant->clkreg;
  382. /* Make sure cclk reflects the current calculated clock */
  383. host->cclk = 0;
  384. if (desired) {
  385. if (variant->explicit_mclk_control) {
  386. host->cclk = host->mclk;
  387. } else if (desired >= host->mclk) {
  388. clk = MCI_CLK_BYPASS;
  389. if (variant->st_clkdiv)
  390. clk |= MCI_ST_UX500_NEG_EDGE;
  391. host->cclk = host->mclk;
  392. } else if (variant->st_clkdiv) {
  393. /*
  394. * DB8500 TRM says f = mclk / (clkdiv + 2)
  395. * => clkdiv = (mclk / f) - 2
  396. * Round the divider up so we don't exceed the max
  397. * frequency
  398. */
  399. clk = DIV_ROUND_UP(host->mclk, desired) - 2;
  400. if (clk >= 256)
  401. clk = 255;
  402. host->cclk = host->mclk / (clk + 2);
  403. } else {
  404. /*
  405. * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
  406. * => clkdiv = mclk / (2 * f) - 1
  407. */
  408. clk = host->mclk / (2 * desired) - 1;
  409. if (clk >= 256)
  410. clk = 255;
  411. host->cclk = host->mclk / (2 * (clk + 1));
  412. }
  413. clk |= variant->clkreg_enable;
  414. clk |= MCI_CLK_ENABLE;
  415. /* This hasn't proven to be worthwhile */
  416. /* clk |= MCI_CLK_PWRSAVE; */
  417. }
  418. /* Set actual clock for debug */
  419. host->mmc->actual_clock = host->cclk;
  420. if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
  421. clk |= MCI_4BIT_BUS;
  422. if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
  423. clk |= variant->clkreg_8bit_bus_enable;
  424. if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
  425. host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
  426. clk |= variant->clkreg_neg_edge_enable;
  427. mmci_write_clkreg(host, clk);
  428. }
  429. static void mmci_dma_release(struct mmci_host *host)
  430. {
  431. if (host->ops && host->ops->dma_release)
  432. host->ops->dma_release(host);
  433. host->use_dma = false;
  434. }
  435. static void mmci_dma_setup(struct mmci_host *host)
  436. {
  437. if (!host->ops || !host->ops->dma_setup)
  438. return;
  439. if (host->ops->dma_setup(host))
  440. return;
  441. /* initialize pre request cookie */
  442. host->next_cookie = 1;
  443. host->use_dma = true;
  444. }
  445. /*
  446. * Validate mmc prerequisites
  447. */
  448. static int mmci_validate_data(struct mmci_host *host,
  449. struct mmc_data *data)
  450. {
  451. struct variant_data *variant = host->variant;
  452. if (!data)
  453. return 0;
  454. if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) {
  455. dev_err(mmc_dev(host->mmc),
  456. "unsupported block size (%d bytes)\n", data->blksz);
  457. return -EINVAL;
  458. }
  459. if (host->ops && host->ops->validate_data)
  460. return host->ops->validate_data(host, data);
  461. return 0;
  462. }
  463. static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
  464. {
  465. int err;
  466. if (!host->ops || !host->ops->prep_data)
  467. return 0;
  468. err = host->ops->prep_data(host, data, next);
  469. if (next && !err)
  470. data->host_cookie = ++host->next_cookie < 0 ?
  471. 1 : host->next_cookie;
  472. return err;
  473. }
  474. static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
  475. int err)
  476. {
  477. if (host->ops && host->ops->unprep_data)
  478. host->ops->unprep_data(host, data, err);
  479. data->host_cookie = 0;
  480. }
  481. static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
  482. {
  483. WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
  484. if (host->ops && host->ops->get_next_data)
  485. host->ops->get_next_data(host, data);
  486. }
  487. static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
  488. {
  489. struct mmc_data *data = host->data;
  490. int ret;
  491. if (!host->use_dma)
  492. return -EINVAL;
  493. ret = mmci_prep_data(host, data, false);
  494. if (ret)
  495. return ret;
  496. if (!host->ops || !host->ops->dma_start)
  497. return -EINVAL;
  498. /* Okay, go for it. */
  499. dev_vdbg(mmc_dev(host->mmc),
  500. "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
  501. data->sg_len, data->blksz, data->blocks, data->flags);
  502. ret = host->ops->dma_start(host, &datactrl);
  503. if (ret)
  504. return ret;
  505. /* Trigger the DMA transfer */
  506. mmci_write_datactrlreg(host, datactrl);
  507. /*
  508. * Let the MMCI say when the data is ended and it's time
  509. * to fire next DMA request. When that happens, MMCI will
  510. * call mmci_data_end()
  511. */
  512. writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
  513. host->base + MMCIMASK0);
  514. return 0;
  515. }
  516. static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
  517. {
  518. if (!host->use_dma)
  519. return;
  520. if (host->ops && host->ops->dma_finalize)
  521. host->ops->dma_finalize(host, data);
  522. }
  523. static void mmci_dma_error(struct mmci_host *host)
  524. {
  525. if (!host->use_dma)
  526. return;
  527. if (host->ops && host->ops->dma_error)
  528. host->ops->dma_error(host);
  529. }
  530. static void
  531. mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
  532. {
  533. writel(0, host->base + MMCICOMMAND);
  534. BUG_ON(host->data);
  535. host->mrq = NULL;
  536. host->cmd = NULL;
  537. mmc_request_done(host->mmc, mrq);
  538. }
  539. static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
  540. {
  541. void __iomem *base = host->base;
  542. struct variant_data *variant = host->variant;
  543. if (host->singleirq) {
  544. unsigned int mask0 = readl(base + MMCIMASK0);
  545. mask0 &= ~variant->irq_pio_mask;
  546. mask0 |= mask;
  547. writel(mask0, base + MMCIMASK0);
  548. }
  549. if (variant->mmcimask1)
  550. writel(mask, base + MMCIMASK1);
  551. host->mask1_reg = mask;
  552. }
  553. static void mmci_stop_data(struct mmci_host *host)
  554. {
  555. mmci_write_datactrlreg(host, 0);
  556. mmci_set_mask1(host, 0);
  557. host->data = NULL;
  558. }
  559. static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
  560. {
  561. unsigned int flags = SG_MITER_ATOMIC;
  562. if (data->flags & MMC_DATA_READ)
  563. flags |= SG_MITER_TO_SG;
  564. else
  565. flags |= SG_MITER_FROM_SG;
  566. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  567. }
  568. static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
  569. {
  570. return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
  571. }
  572. static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
  573. {
  574. return MCI_DPSM_ENABLE | (host->data->blksz << 16);
  575. }
  576. static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
  577. {
  578. void __iomem *base = host->base;
  579. /*
  580. * Before unmasking for the busy end IRQ, confirm that the
  581. * command was sent successfully. To keep track of having a
  582. * command in-progress, waiting for busy signaling to end,
  583. * store the status in host->busy_status.
  584. *
  585. * Note that, the card may need a couple of clock cycles before
  586. * it starts signaling busy on DAT0, hence re-read the
  587. * MMCISTATUS register here, to allow the busy bit to be set.
  588. * Potentially we may even need to poll the register for a
  589. * while, to allow it to be set, but tests indicates that it
  590. * isn't needed.
  591. */
  592. if (!host->busy_status && !(status & err_msk) &&
  593. (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
  594. writel(readl(base + MMCIMASK0) |
  595. host->variant->busy_detect_mask,
  596. base + MMCIMASK0);
  597. host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
  598. return false;
  599. }
  600. /*
  601. * If there is a command in-progress that has been successfully
  602. * sent, then bail out if busy status is set and wait for the
  603. * busy end IRQ.
  604. *
  605. * Note that, the HW triggers an IRQ on both edges while
  606. * monitoring DAT0 for busy completion, but there is only one
  607. * status bit in MMCISTATUS for the busy state. Therefore
  608. * both the start and the end interrupts needs to be cleared,
  609. * one after the other. So, clear the busy start IRQ here.
  610. */
  611. if (host->busy_status &&
  612. (status & host->variant->busy_detect_flag)) {
  613. writel(host->variant->busy_detect_mask, base + MMCICLEAR);
  614. return false;
  615. }
  616. /*
  617. * If there is a command in-progress that has been successfully
  618. * sent and the busy bit isn't set, it means we have received
  619. * the busy end IRQ. Clear and mask the IRQ, then continue to
  620. * process the command.
  621. */
  622. if (host->busy_status) {
  623. writel(host->variant->busy_detect_mask, base + MMCICLEAR);
  624. writel(readl(base + MMCIMASK0) &
  625. ~host->variant->busy_detect_mask, base + MMCIMASK0);
  626. host->busy_status = 0;
  627. }
  628. return true;
  629. }
  630. /*
  631. * All the DMA operation mode stuff goes inside this ifdef.
  632. * This assumes that you have a generic DMA device interface,
  633. * no custom DMA interfaces are supported.
  634. */
  635. #ifdef CONFIG_DMA_ENGINE
  636. struct mmci_dmae_next {
  637. struct dma_async_tx_descriptor *desc;
  638. struct dma_chan *chan;
  639. };
  640. struct mmci_dmae_priv {
  641. struct dma_chan *cur;
  642. struct dma_chan *rx_channel;
  643. struct dma_chan *tx_channel;
  644. struct dma_async_tx_descriptor *desc_current;
  645. struct mmci_dmae_next next_data;
  646. };
  647. int mmci_dmae_setup(struct mmci_host *host)
  648. {
  649. const char *rxname, *txname;
  650. struct mmci_dmae_priv *dmae;
  651. dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
  652. if (!dmae)
  653. return -ENOMEM;
  654. host->dma_priv = dmae;
  655. dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
  656. if (IS_ERR(dmae->rx_channel)) {
  657. int ret = PTR_ERR(dmae->rx_channel);
  658. dmae->rx_channel = NULL;
  659. return ret;
  660. }
  661. dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
  662. if (IS_ERR(dmae->tx_channel)) {
  663. if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER)
  664. dev_warn(mmc_dev(host->mmc),
  665. "Deferred probe for TX channel ignored\n");
  666. dmae->tx_channel = NULL;
  667. }
  668. /*
  669. * If only an RX channel is specified, the driver will
  670. * attempt to use it bidirectionally, however if it is
  671. * is specified but cannot be located, DMA will be disabled.
  672. */
  673. if (dmae->rx_channel && !dmae->tx_channel)
  674. dmae->tx_channel = dmae->rx_channel;
  675. if (dmae->rx_channel)
  676. rxname = dma_chan_name(dmae->rx_channel);
  677. else
  678. rxname = "none";
  679. if (dmae->tx_channel)
  680. txname = dma_chan_name(dmae->tx_channel);
  681. else
  682. txname = "none";
  683. dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
  684. rxname, txname);
  685. /*
  686. * Limit the maximum segment size in any SG entry according to
  687. * the parameters of the DMA engine device.
  688. */
  689. if (dmae->tx_channel) {
  690. struct device *dev = dmae->tx_channel->device->dev;
  691. unsigned int max_seg_size = dma_get_max_seg_size(dev);
  692. if (max_seg_size < host->mmc->max_seg_size)
  693. host->mmc->max_seg_size = max_seg_size;
  694. }
  695. if (dmae->rx_channel) {
  696. struct device *dev = dmae->rx_channel->device->dev;
  697. unsigned int max_seg_size = dma_get_max_seg_size(dev);
  698. if (max_seg_size < host->mmc->max_seg_size)
  699. host->mmc->max_seg_size = max_seg_size;
  700. }
  701. if (!dmae->tx_channel || !dmae->rx_channel) {
  702. mmci_dmae_release(host);
  703. return -EINVAL;
  704. }
  705. return 0;
  706. }
  707. /*
  708. * This is used in or so inline it
  709. * so it can be discarded.
  710. */
  711. void mmci_dmae_release(struct mmci_host *host)
  712. {
  713. struct mmci_dmae_priv *dmae = host->dma_priv;
  714. if (dmae->rx_channel)
  715. dma_release_channel(dmae->rx_channel);
  716. if (dmae->tx_channel)
  717. dma_release_channel(dmae->tx_channel);
  718. dmae->rx_channel = dmae->tx_channel = NULL;
  719. }
  720. static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
  721. {
  722. struct mmci_dmae_priv *dmae = host->dma_priv;
  723. struct dma_chan *chan;
  724. if (data->flags & MMC_DATA_READ)
  725. chan = dmae->rx_channel;
  726. else
  727. chan = dmae->tx_channel;
  728. dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
  729. mmc_get_dma_dir(data));
  730. }
  731. void mmci_dmae_error(struct mmci_host *host)
  732. {
  733. struct mmci_dmae_priv *dmae = host->dma_priv;
  734. if (!dma_inprogress(host))
  735. return;
  736. dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
  737. dmaengine_terminate_all(dmae->cur);
  738. host->dma_in_progress = false;
  739. dmae->cur = NULL;
  740. dmae->desc_current = NULL;
  741. host->data->host_cookie = 0;
  742. mmci_dma_unmap(host, host->data);
  743. }
  744. void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
  745. {
  746. struct mmci_dmae_priv *dmae = host->dma_priv;
  747. u32 status;
  748. int i;
  749. if (!dma_inprogress(host))
  750. return;
  751. /* Wait up to 1ms for the DMA to complete */
  752. for (i = 0; ; i++) {
  753. status = readl(host->base + MMCISTATUS);
  754. if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
  755. break;
  756. udelay(10);
  757. }
  758. /*
  759. * Check to see whether we still have some data left in the FIFO -
  760. * this catches DMA controllers which are unable to monitor the
  761. * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
  762. * contiguous buffers. On TX, we'll get a FIFO underrun error.
  763. */
  764. if (status & MCI_RXDATAAVLBLMASK) {
  765. mmci_dma_error(host);
  766. if (!data->error)
  767. data->error = -EIO;
  768. } else if (!data->host_cookie) {
  769. mmci_dma_unmap(host, data);
  770. }
  771. /*
  772. * Use of DMA with scatter-gather is impossible.
  773. * Give up with DMA and switch back to PIO mode.
  774. */
  775. if (status & MCI_RXDATAAVLBLMASK) {
  776. dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
  777. mmci_dma_release(host);
  778. }
  779. host->dma_in_progress = false;
  780. dmae->cur = NULL;
  781. dmae->desc_current = NULL;
  782. }
  783. /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
  784. static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
  785. struct dma_chan **dma_chan,
  786. struct dma_async_tx_descriptor **dma_desc)
  787. {
  788. struct mmci_dmae_priv *dmae = host->dma_priv;
  789. struct variant_data *variant = host->variant;
  790. struct dma_slave_config conf = {
  791. .src_addr = host->phybase + MMCIFIFO,
  792. .dst_addr = host->phybase + MMCIFIFO,
  793. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  794. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  795. .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
  796. .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
  797. .device_fc = false,
  798. };
  799. struct dma_chan *chan;
  800. struct dma_device *device;
  801. struct dma_async_tx_descriptor *desc;
  802. int nr_sg;
  803. unsigned long flags = DMA_CTRL_ACK;
  804. if (data->flags & MMC_DATA_READ) {
  805. conf.direction = DMA_DEV_TO_MEM;
  806. chan = dmae->rx_channel;
  807. } else {
  808. conf.direction = DMA_MEM_TO_DEV;
  809. chan = dmae->tx_channel;
  810. }
  811. /* If there's no DMA channel, fall back to PIO */
  812. if (!chan)
  813. return -EINVAL;
  814. /* If less than or equal to the fifo size, don't bother with DMA */
  815. if (data->blksz * data->blocks <= variant->fifosize)
  816. return -EINVAL;
  817. /*
  818. * This is necessary to get SDIO working on the Ux500. We do not yet
  819. * know if this is a bug in:
  820. * - The Ux500 DMA controller (DMA40)
  821. * - The MMCI DMA interface on the Ux500
  822. * some power of two blocks (such as 64 bytes) are sent regularly
  823. * during SDIO traffic and those work fine so for these we enable DMA
  824. * transfers.
  825. */
  826. if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
  827. return -EINVAL;
  828. device = chan->device;
  829. nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
  830. mmc_get_dma_dir(data));
  831. if (nr_sg == 0)
  832. return -EINVAL;
  833. if (host->variant->qcom_dml)
  834. flags |= DMA_PREP_INTERRUPT;
  835. dmaengine_slave_config(chan, &conf);
  836. desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
  837. conf.direction, flags);
  838. if (!desc)
  839. goto unmap_exit;
  840. *dma_chan = chan;
  841. *dma_desc = desc;
  842. return 0;
  843. unmap_exit:
  844. dma_unmap_sg(device->dev, data->sg, data->sg_len,
  845. mmc_get_dma_dir(data));
  846. return -ENOMEM;
  847. }
  848. int mmci_dmae_prep_data(struct mmci_host *host,
  849. struct mmc_data *data,
  850. bool next)
  851. {
  852. struct mmci_dmae_priv *dmae = host->dma_priv;
  853. struct mmci_dmae_next *nd = &dmae->next_data;
  854. if (!host->use_dma)
  855. return -EINVAL;
  856. if (next)
  857. return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
  858. /* Check if next job is already prepared. */
  859. if (dmae->cur && dmae->desc_current)
  860. return 0;
  861. /* No job were prepared thus do it now. */
  862. return _mmci_dmae_prep_data(host, data, &dmae->cur,
  863. &dmae->desc_current);
  864. }
  865. int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
  866. {
  867. struct mmci_dmae_priv *dmae = host->dma_priv;
  868. int ret;
  869. host->dma_in_progress = true;
  870. ret = dma_submit_error(dmaengine_submit(dmae->desc_current));
  871. if (ret < 0) {
  872. host->dma_in_progress = false;
  873. return ret;
  874. }
  875. dma_async_issue_pending(dmae->cur);
  876. *datactrl |= MCI_DPSM_DMAENABLE;
  877. return 0;
  878. }
  879. void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
  880. {
  881. struct mmci_dmae_priv *dmae = host->dma_priv;
  882. struct mmci_dmae_next *next = &dmae->next_data;
  883. if (!host->use_dma)
  884. return;
  885. WARN_ON(!data->host_cookie && (next->desc || next->chan));
  886. dmae->desc_current = next->desc;
  887. dmae->cur = next->chan;
  888. next->desc = NULL;
  889. next->chan = NULL;
  890. }
  891. void mmci_dmae_unprep_data(struct mmci_host *host,
  892. struct mmc_data *data, int err)
  893. {
  894. struct mmci_dmae_priv *dmae = host->dma_priv;
  895. if (!host->use_dma)
  896. return;
  897. mmci_dma_unmap(host, data);
  898. if (err) {
  899. struct mmci_dmae_next *next = &dmae->next_data;
  900. struct dma_chan *chan;
  901. if (data->flags & MMC_DATA_READ)
  902. chan = dmae->rx_channel;
  903. else
  904. chan = dmae->tx_channel;
  905. dmaengine_terminate_all(chan);
  906. if (dmae->desc_current == next->desc)
  907. dmae->desc_current = NULL;
  908. if (dmae->cur == next->chan) {
  909. host->dma_in_progress = false;
  910. dmae->cur = NULL;
  911. }
  912. next->desc = NULL;
  913. next->chan = NULL;
  914. }
  915. }
  916. static struct mmci_host_ops mmci_variant_ops = {
  917. .prep_data = mmci_dmae_prep_data,
  918. .unprep_data = mmci_dmae_unprep_data,
  919. .get_datactrl_cfg = mmci_get_dctrl_cfg,
  920. .get_next_data = mmci_dmae_get_next_data,
  921. .dma_setup = mmci_dmae_setup,
  922. .dma_release = mmci_dmae_release,
  923. .dma_start = mmci_dmae_start,
  924. .dma_finalize = mmci_dmae_finalize,
  925. .dma_error = mmci_dmae_error,
  926. };
  927. #else
  928. static struct mmci_host_ops mmci_variant_ops = {
  929. .get_datactrl_cfg = mmci_get_dctrl_cfg,
  930. };
  931. #endif
  932. static void mmci_variant_init(struct mmci_host *host)
  933. {
  934. host->ops = &mmci_variant_ops;
  935. }
  936. static void ux500_variant_init(struct mmci_host *host)
  937. {
  938. host->ops = &mmci_variant_ops;
  939. host->ops->busy_complete = ux500_busy_complete;
  940. }
  941. static void ux500v2_variant_init(struct mmci_host *host)
  942. {
  943. host->ops = &mmci_variant_ops;
  944. host->ops->busy_complete = ux500_busy_complete;
  945. host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
  946. }
  947. static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
  948. {
  949. struct mmci_host *host = mmc_priv(mmc);
  950. struct mmc_data *data = mrq->data;
  951. if (!data)
  952. return;
  953. WARN_ON(data->host_cookie);
  954. if (mmci_validate_data(host, data))
  955. return;
  956. mmci_prep_data(host, data, true);
  957. }
  958. static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
  959. int err)
  960. {
  961. struct mmci_host *host = mmc_priv(mmc);
  962. struct mmc_data *data = mrq->data;
  963. if (!data || !data->host_cookie)
  964. return;
  965. mmci_unprep_data(host, data, err);
  966. }
  967. static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
  968. {
  969. struct variant_data *variant = host->variant;
  970. unsigned int datactrl, timeout, irqmask;
  971. unsigned long long clks;
  972. void __iomem *base;
  973. dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
  974. data->blksz, data->blocks, data->flags);
  975. host->data = data;
  976. host->size = data->blksz * data->blocks;
  977. data->bytes_xfered = 0;
  978. clks = (unsigned long long)data->timeout_ns * host->cclk;
  979. do_div(clks, NSEC_PER_SEC);
  980. timeout = data->timeout_clks + (unsigned int)clks;
  981. base = host->base;
  982. writel(timeout, base + MMCIDATATIMER);
  983. writel(host->size, base + MMCIDATALENGTH);
  984. datactrl = host->ops->get_datactrl_cfg(host);
  985. datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
  986. if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
  987. u32 clk;
  988. datactrl |= variant->datactrl_mask_sdio;
  989. /*
  990. * The ST Micro variant for SDIO small write transfers
  991. * needs to have clock H/W flow control disabled,
  992. * otherwise the transfer will not start. The threshold
  993. * depends on the rate of MCLK.
  994. */
  995. if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
  996. (host->size < 8 ||
  997. (host->size <= 8 && host->mclk > 50000000)))
  998. clk = host->clk_reg & ~variant->clkreg_enable;
  999. else
  1000. clk = host->clk_reg | variant->clkreg_enable;
  1001. mmci_write_clkreg(host, clk);
  1002. }
  1003. if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
  1004. host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
  1005. datactrl |= variant->datactrl_mask_ddrmode;
  1006. /*
  1007. * Attempt to use DMA operation mode, if this
  1008. * should fail, fall back to PIO mode
  1009. */
  1010. if (!mmci_dma_start(host, datactrl))
  1011. return;
  1012. /* IRQ mode, map the SG list for CPU reading/writing */
  1013. mmci_init_sg(host, data);
  1014. if (data->flags & MMC_DATA_READ) {
  1015. irqmask = MCI_RXFIFOHALFFULLMASK;
  1016. /*
  1017. * If we have less than the fifo 'half-full' threshold to
  1018. * transfer, trigger a PIO interrupt as soon as any data
  1019. * is available.
  1020. */
  1021. if (host->size < variant->fifohalfsize)
  1022. irqmask |= MCI_RXDATAAVLBLMASK;
  1023. } else {
  1024. /*
  1025. * We don't actually need to include "FIFO empty" here
  1026. * since its implicit in "FIFO half empty".
  1027. */
  1028. irqmask = MCI_TXFIFOHALFEMPTYMASK;
  1029. }
  1030. mmci_write_datactrlreg(host, datactrl);
  1031. writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
  1032. mmci_set_mask1(host, irqmask);
  1033. }
  1034. static void
  1035. mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
  1036. {
  1037. void __iomem *base = host->base;
  1038. unsigned long long clks;
  1039. dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
  1040. cmd->opcode, cmd->arg, cmd->flags);
  1041. if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
  1042. writel(0, base + MMCICOMMAND);
  1043. mmci_reg_delay(host);
  1044. }
  1045. if (host->variant->cmdreg_stop &&
  1046. cmd->opcode == MMC_STOP_TRANSMISSION)
  1047. c |= host->variant->cmdreg_stop;
  1048. c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
  1049. if (cmd->flags & MMC_RSP_PRESENT) {
  1050. if (cmd->flags & MMC_RSP_136)
  1051. c |= host->variant->cmdreg_lrsp_crc;
  1052. else if (cmd->flags & MMC_RSP_CRC)
  1053. c |= host->variant->cmdreg_srsp_crc;
  1054. else
  1055. c |= host->variant->cmdreg_srsp;
  1056. }
  1057. if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) {
  1058. if (!cmd->busy_timeout)
  1059. cmd->busy_timeout = 10 * MSEC_PER_SEC;
  1060. if (cmd->busy_timeout > host->mmc->max_busy_timeout)
  1061. clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk;
  1062. else
  1063. clks = (unsigned long long)cmd->busy_timeout * host->cclk;
  1064. do_div(clks, MSEC_PER_SEC);
  1065. writel_relaxed(clks, host->base + MMCIDATATIMER);
  1066. }
  1067. if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE)
  1068. host->ops->pre_sig_volt_switch(host);
  1069. if (/*interrupt*/0)
  1070. c |= MCI_CPSM_INTERRUPT;
  1071. if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
  1072. c |= host->variant->data_cmd_enable;
  1073. host->cmd = cmd;
  1074. writel(cmd->arg, base + MMCIARGUMENT);
  1075. writel(c, base + MMCICOMMAND);
  1076. }
  1077. static void mmci_stop_command(struct mmci_host *host)
  1078. {
  1079. host->stop_abort.error = 0;
  1080. mmci_start_command(host, &host->stop_abort, 0);
  1081. }
  1082. static void
  1083. mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
  1084. unsigned int status)
  1085. {
  1086. unsigned int status_err;
  1087. /* Make sure we have data to handle */
  1088. if (!data)
  1089. return;
  1090. /* First check for errors */
  1091. status_err = status & (host->variant->start_err |
  1092. MCI_DATACRCFAIL | MCI_DATATIMEOUT |
  1093. MCI_TXUNDERRUN | MCI_RXOVERRUN);
  1094. if (status_err) {
  1095. u32 remain, success;
  1096. /* Terminate the DMA transfer */
  1097. mmci_dma_error(host);
  1098. /*
  1099. * Calculate how far we are into the transfer. Note that
  1100. * the data counter gives the number of bytes transferred
  1101. * on the MMC bus, not on the host side. On reads, this
  1102. * can be as much as a FIFO-worth of data ahead. This
  1103. * matters for FIFO overruns only.
  1104. */
  1105. if (!host->variant->datacnt_useless) {
  1106. remain = readl(host->base + MMCIDATACNT);
  1107. success = data->blksz * data->blocks - remain;
  1108. } else {
  1109. success = 0;
  1110. }
  1111. dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
  1112. status_err, success);
  1113. if (status_err & MCI_DATACRCFAIL) {
  1114. /* Last block was not successful */
  1115. success -= 1;
  1116. data->error = -EILSEQ;
  1117. } else if (status_err & MCI_DATATIMEOUT) {
  1118. data->error = -ETIMEDOUT;
  1119. } else if (status_err & MCI_STARTBITERR) {
  1120. data->error = -ECOMM;
  1121. } else if (status_err & MCI_TXUNDERRUN) {
  1122. data->error = -EIO;
  1123. } else if (status_err & MCI_RXOVERRUN) {
  1124. if (success > host->variant->fifosize)
  1125. success -= host->variant->fifosize;
  1126. else
  1127. success = 0;
  1128. data->error = -EIO;
  1129. }
  1130. data->bytes_xfered = round_down(success, data->blksz);
  1131. }
  1132. if (status & MCI_DATABLOCKEND)
  1133. dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
  1134. if (status & MCI_DATAEND || data->error) {
  1135. mmci_dma_finalize(host, data);
  1136. mmci_stop_data(host);
  1137. if (!data->error)
  1138. /* The error clause is handled above, success! */
  1139. data->bytes_xfered = data->blksz * data->blocks;
  1140. if (!data->stop) {
  1141. if (host->variant->cmdreg_stop && data->error)
  1142. mmci_stop_command(host);
  1143. else
  1144. mmci_request_end(host, data->mrq);
  1145. } else if (host->mrq->sbc && !data->error) {
  1146. mmci_request_end(host, data->mrq);
  1147. } else {
  1148. mmci_start_command(host, data->stop, 0);
  1149. }
  1150. }
  1151. }
  1152. static void
  1153. mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
  1154. unsigned int status)
  1155. {
  1156. u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT;
  1157. void __iomem *base = host->base;
  1158. bool sbc, busy_resp;
  1159. if (!cmd)
  1160. return;
  1161. sbc = (cmd == host->mrq->sbc);
  1162. busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
  1163. /*
  1164. * We need to be one of these interrupts to be considered worth
  1165. * handling. Note that we tag on any latent IRQs postponed
  1166. * due to waiting for busy status.
  1167. */
  1168. if (host->variant->busy_timeout && busy_resp)
  1169. err_msk |= MCI_DATATIMEOUT;
  1170. if (!((status | host->busy_status) &
  1171. (err_msk | MCI_CMDSENT | MCI_CMDRESPEND)))
  1172. return;
  1173. /* Handle busy detection on DAT0 if the variant supports it. */
  1174. if (busy_resp && host->variant->busy_detect)
  1175. if (!host->ops->busy_complete(host, status, err_msk))
  1176. return;
  1177. host->cmd = NULL;
  1178. if (status & MCI_CMDTIMEOUT) {
  1179. cmd->error = -ETIMEDOUT;
  1180. } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
  1181. cmd->error = -EILSEQ;
  1182. } else if (host->variant->busy_timeout && busy_resp &&
  1183. status & MCI_DATATIMEOUT) {
  1184. cmd->error = -ETIMEDOUT;
  1185. host->irq_action = IRQ_WAKE_THREAD;
  1186. } else {
  1187. cmd->resp[0] = readl(base + MMCIRESPONSE0);
  1188. cmd->resp[1] = readl(base + MMCIRESPONSE1);
  1189. cmd->resp[2] = readl(base + MMCIRESPONSE2);
  1190. cmd->resp[3] = readl(base + MMCIRESPONSE3);
  1191. }
  1192. if ((!sbc && !cmd->data) || cmd->error) {
  1193. if (host->data) {
  1194. /* Terminate the DMA transfer */
  1195. mmci_dma_error(host);
  1196. mmci_stop_data(host);
  1197. if (host->variant->cmdreg_stop && cmd->error) {
  1198. mmci_stop_command(host);
  1199. return;
  1200. }
  1201. }
  1202. if (host->irq_action != IRQ_WAKE_THREAD)
  1203. mmci_request_end(host, host->mrq);
  1204. } else if (sbc) {
  1205. mmci_start_command(host, host->mrq->cmd, 0);
  1206. } else if (!host->variant->datactrl_first &&
  1207. !(cmd->data->flags & MMC_DATA_READ)) {
  1208. mmci_start_data(host, cmd->data);
  1209. }
  1210. }
  1211. static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
  1212. {
  1213. return remain - (readl(host->base + MMCIFIFOCNT) << 2);
  1214. }
  1215. static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
  1216. {
  1217. /*
  1218. * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
  1219. * from the fifo range should be used
  1220. */
  1221. if (status & MCI_RXFIFOHALFFULL)
  1222. return host->variant->fifohalfsize;
  1223. else if (status & MCI_RXDATAAVLBL)
  1224. return 4;
  1225. return 0;
  1226. }
  1227. static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
  1228. {
  1229. void __iomem *base = host->base;
  1230. char *ptr = buffer;
  1231. u32 status = readl(host->base + MMCISTATUS);
  1232. int host_remain = host->size;
  1233. do {
  1234. int count = host->get_rx_fifocnt(host, status, host_remain);
  1235. if (count > remain)
  1236. count = remain;
  1237. if (count <= 0)
  1238. break;
  1239. /*
  1240. * SDIO especially may want to send something that is
  1241. * not divisible by 4 (as opposed to card sectors
  1242. * etc). Therefore make sure to always read the last bytes
  1243. * while only doing full 32-bit reads towards the FIFO.
  1244. */
  1245. if (unlikely(count & 0x3)) {
  1246. if (count < 4) {
  1247. unsigned char buf[4];
  1248. ioread32_rep(base + MMCIFIFO, buf, 1);
  1249. memcpy(ptr, buf, count);
  1250. } else {
  1251. ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
  1252. count &= ~0x3;
  1253. }
  1254. } else {
  1255. ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
  1256. }
  1257. ptr += count;
  1258. remain -= count;
  1259. host_remain -= count;
  1260. if (remain == 0)
  1261. break;
  1262. status = readl(base + MMCISTATUS);
  1263. } while (status & MCI_RXDATAAVLBL);
  1264. return ptr - buffer;
  1265. }
  1266. static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
  1267. {
  1268. struct variant_data *variant = host->variant;
  1269. void __iomem *base = host->base;
  1270. char *ptr = buffer;
  1271. do {
  1272. unsigned int count, maxcnt;
  1273. maxcnt = status & MCI_TXFIFOEMPTY ?
  1274. variant->fifosize : variant->fifohalfsize;
  1275. count = min(remain, maxcnt);
  1276. /*
  1277. * SDIO especially may want to send something that is
  1278. * not divisible by 4 (as opposed to card sectors
  1279. * etc), and the FIFO only accept full 32-bit writes.
  1280. * So compensate by adding +3 on the count, a single
  1281. * byte become a 32bit write, 7 bytes will be two
  1282. * 32bit writes etc.
  1283. */
  1284. iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
  1285. ptr += count;
  1286. remain -= count;
  1287. if (remain == 0)
  1288. break;
  1289. status = readl(base + MMCISTATUS);
  1290. } while (status & MCI_TXFIFOHALFEMPTY);
  1291. return ptr - buffer;
  1292. }
  1293. /*
  1294. * PIO data transfer IRQ handler.
  1295. */
  1296. static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
  1297. {
  1298. struct mmci_host *host = dev_id;
  1299. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  1300. struct variant_data *variant = host->variant;
  1301. void __iomem *base = host->base;
  1302. u32 status;
  1303. status = readl(base + MMCISTATUS);
  1304. dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
  1305. do {
  1306. unsigned int remain, len;
  1307. char *buffer;
  1308. /*
  1309. * For write, we only need to test the half-empty flag
  1310. * here - if the FIFO is completely empty, then by
  1311. * definition it is more than half empty.
  1312. *
  1313. * For read, check for data available.
  1314. */
  1315. if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
  1316. break;
  1317. if (!sg_miter_next(sg_miter))
  1318. break;
  1319. buffer = sg_miter->addr;
  1320. remain = sg_miter->length;
  1321. len = 0;
  1322. if (status & MCI_RXACTIVE)
  1323. len = mmci_pio_read(host, buffer, remain);
  1324. if (status & MCI_TXACTIVE)
  1325. len = mmci_pio_write(host, buffer, remain, status);
  1326. sg_miter->consumed = len;
  1327. host->size -= len;
  1328. remain -= len;
  1329. if (remain)
  1330. break;
  1331. status = readl(base + MMCISTATUS);
  1332. } while (1);
  1333. sg_miter_stop(sg_miter);
  1334. /*
  1335. * If we have less than the fifo 'half-full' threshold to transfer,
  1336. * trigger a PIO interrupt as soon as any data is available.
  1337. */
  1338. if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
  1339. mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
  1340. /*
  1341. * If we run out of data, disable the data IRQs; this
  1342. * prevents a race where the FIFO becomes empty before
  1343. * the chip itself has disabled the data path, and
  1344. * stops us racing with our data end IRQ.
  1345. */
  1346. if (host->size == 0) {
  1347. mmci_set_mask1(host, 0);
  1348. writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
  1349. }
  1350. return IRQ_HANDLED;
  1351. }
  1352. /*
  1353. * Handle completion of command and data transfers.
  1354. */
  1355. static irqreturn_t mmci_irq(int irq, void *dev_id)
  1356. {
  1357. struct mmci_host *host = dev_id;
  1358. u32 status;
  1359. spin_lock(&host->lock);
  1360. host->irq_action = IRQ_HANDLED;
  1361. do {
  1362. status = readl(host->base + MMCISTATUS);
  1363. if (host->singleirq) {
  1364. if (status & host->mask1_reg)
  1365. mmci_pio_irq(irq, dev_id);
  1366. status &= ~host->variant->irq_pio_mask;
  1367. }
  1368. /*
  1369. * Busy detection is managed by mmci_cmd_irq(), including to
  1370. * clear the corresponding IRQ.
  1371. */
  1372. status &= readl(host->base + MMCIMASK0);
  1373. if (host->variant->busy_detect)
  1374. writel(status & ~host->variant->busy_detect_mask,
  1375. host->base + MMCICLEAR);
  1376. else
  1377. writel(status, host->base + MMCICLEAR);
  1378. dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
  1379. if (host->variant->reversed_irq_handling) {
  1380. mmci_data_irq(host, host->data, status);
  1381. mmci_cmd_irq(host, host->cmd, status);
  1382. } else {
  1383. mmci_cmd_irq(host, host->cmd, status);
  1384. mmci_data_irq(host, host->data, status);
  1385. }
  1386. /*
  1387. * Busy detection has been handled by mmci_cmd_irq() above.
  1388. * Clear the status bit to prevent polling in IRQ context.
  1389. */
  1390. if (host->variant->busy_detect_flag)
  1391. status &= ~host->variant->busy_detect_flag;
  1392. } while (status);
  1393. spin_unlock(&host->lock);
  1394. return host->irq_action;
  1395. }
  1396. /*
  1397. * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW.
  1398. *
  1399. * A reset is needed for some variants, where a datatimeout for a R1B request
  1400. * causes the DPSM to stay busy (non-functional).
  1401. */
  1402. static irqreturn_t mmci_irq_thread(int irq, void *dev_id)
  1403. {
  1404. struct mmci_host *host = dev_id;
  1405. unsigned long flags;
  1406. if (host->rst) {
  1407. reset_control_assert(host->rst);
  1408. udelay(2);
  1409. reset_control_deassert(host->rst);
  1410. }
  1411. spin_lock_irqsave(&host->lock, flags);
  1412. writel(host->clk_reg, host->base + MMCICLOCK);
  1413. writel(host->pwr_reg, host->base + MMCIPOWER);
  1414. writel(MCI_IRQENABLE | host->variant->start_err,
  1415. host->base + MMCIMASK0);
  1416. host->irq_action = IRQ_HANDLED;
  1417. mmci_request_end(host, host->mrq);
  1418. spin_unlock_irqrestore(&host->lock, flags);
  1419. return host->irq_action;
  1420. }
  1421. static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  1422. {
  1423. struct mmci_host *host = mmc_priv(mmc);
  1424. unsigned long flags;
  1425. WARN_ON(host->mrq != NULL);
  1426. mrq->cmd->error = mmci_validate_data(host, mrq->data);
  1427. if (mrq->cmd->error) {
  1428. mmc_request_done(mmc, mrq);
  1429. return;
  1430. }
  1431. spin_lock_irqsave(&host->lock, flags);
  1432. host->mrq = mrq;
  1433. if (mrq->data)
  1434. mmci_get_next_data(host, mrq->data);
  1435. if (mrq->data &&
  1436. (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
  1437. mmci_start_data(host, mrq->data);
  1438. if (mrq->sbc)
  1439. mmci_start_command(host, mrq->sbc, 0);
  1440. else
  1441. mmci_start_command(host, mrq->cmd, 0);
  1442. spin_unlock_irqrestore(&host->lock, flags);
  1443. }
  1444. static void mmci_set_max_busy_timeout(struct mmc_host *mmc)
  1445. {
  1446. struct mmci_host *host = mmc_priv(mmc);
  1447. u32 max_busy_timeout = 0;
  1448. if (!host->variant->busy_detect)
  1449. return;
  1450. if (host->variant->busy_timeout && mmc->actual_clock)
  1451. max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC);
  1452. mmc->max_busy_timeout = max_busy_timeout;
  1453. }
  1454. static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1455. {
  1456. struct mmci_host *host = mmc_priv(mmc);
  1457. struct variant_data *variant = host->variant;
  1458. u32 pwr = 0;
  1459. unsigned long flags;
  1460. int ret;
  1461. if (host->plat->ios_handler &&
  1462. host->plat->ios_handler(mmc_dev(mmc), ios))
  1463. dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
  1464. switch (ios->power_mode) {
  1465. case MMC_POWER_OFF:
  1466. if (!IS_ERR(mmc->supply.vmmc))
  1467. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  1468. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
  1469. regulator_disable(mmc->supply.vqmmc);
  1470. host->vqmmc_enabled = false;
  1471. }
  1472. break;
  1473. case MMC_POWER_UP:
  1474. if (!IS_ERR(mmc->supply.vmmc))
  1475. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
  1476. /*
  1477. * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
  1478. * and instead uses MCI_PWR_ON so apply whatever value is
  1479. * configured in the variant data.
  1480. */
  1481. pwr |= variant->pwrreg_powerup;
  1482. break;
  1483. case MMC_POWER_ON:
  1484. if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
  1485. ret = regulator_enable(mmc->supply.vqmmc);
  1486. if (ret < 0)
  1487. dev_err(mmc_dev(mmc),
  1488. "failed to enable vqmmc regulator\n");
  1489. else
  1490. host->vqmmc_enabled = true;
  1491. }
  1492. pwr |= MCI_PWR_ON;
  1493. break;
  1494. }
  1495. if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
  1496. /*
  1497. * The ST Micro variant has some additional bits
  1498. * indicating signal direction for the signals in
  1499. * the SD/MMC bus and feedback-clock usage.
  1500. */
  1501. pwr |= host->pwr_reg_add;
  1502. if (ios->bus_width == MMC_BUS_WIDTH_4)
  1503. pwr &= ~MCI_ST_DATA74DIREN;
  1504. else if (ios->bus_width == MMC_BUS_WIDTH_1)
  1505. pwr &= (~MCI_ST_DATA74DIREN &
  1506. ~MCI_ST_DATA31DIREN &
  1507. ~MCI_ST_DATA2DIREN);
  1508. }
  1509. if (variant->opendrain) {
  1510. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  1511. pwr |= variant->opendrain;
  1512. } else {
  1513. /*
  1514. * If the variant cannot configure the pads by its own, then we
  1515. * expect the pinctrl to be able to do that for us
  1516. */
  1517. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  1518. pinctrl_select_state(host->pinctrl, host->pins_opendrain);
  1519. else
  1520. pinctrl_select_default_state(mmc_dev(mmc));
  1521. }
  1522. /*
  1523. * If clock = 0 and the variant requires the MMCIPOWER to be used for
  1524. * gating the clock, the MCI_PWR_ON bit is cleared.
  1525. */
  1526. if (!ios->clock && variant->pwrreg_clkgate)
  1527. pwr &= ~MCI_PWR_ON;
  1528. if (host->variant->explicit_mclk_control &&
  1529. ios->clock != host->clock_cache) {
  1530. ret = clk_set_rate(host->clk, ios->clock);
  1531. if (ret < 0)
  1532. dev_err(mmc_dev(host->mmc),
  1533. "Error setting clock rate (%d)\n", ret);
  1534. else
  1535. host->mclk = clk_get_rate(host->clk);
  1536. }
  1537. host->clock_cache = ios->clock;
  1538. spin_lock_irqsave(&host->lock, flags);
  1539. if (host->ops && host->ops->set_clkreg)
  1540. host->ops->set_clkreg(host, ios->clock);
  1541. else
  1542. mmci_set_clkreg(host, ios->clock);
  1543. mmci_set_max_busy_timeout(mmc);
  1544. if (host->ops && host->ops->set_pwrreg)
  1545. host->ops->set_pwrreg(host, pwr);
  1546. else
  1547. mmci_write_pwrreg(host, pwr);
  1548. mmci_reg_delay(host);
  1549. spin_unlock_irqrestore(&host->lock, flags);
  1550. }
  1551. static int mmci_get_cd(struct mmc_host *mmc)
  1552. {
  1553. struct mmci_host *host = mmc_priv(mmc);
  1554. struct mmci_platform_data *plat = host->plat;
  1555. unsigned int status = mmc_gpio_get_cd(mmc);
  1556. if (status == -ENOSYS) {
  1557. if (!plat->status)
  1558. return 1; /* Assume always present */
  1559. status = plat->status(mmc_dev(host->mmc));
  1560. }
  1561. return status;
  1562. }
  1563. static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
  1564. {
  1565. struct mmci_host *host = mmc_priv(mmc);
  1566. int ret;
  1567. ret = mmc_regulator_set_vqmmc(mmc, ios);
  1568. if (!ret && host->ops && host->ops->post_sig_volt_switch)
  1569. ret = host->ops->post_sig_volt_switch(host, ios);
  1570. else if (ret)
  1571. ret = 0;
  1572. if (ret < 0)
  1573. dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
  1574. return ret;
  1575. }
  1576. static struct mmc_host_ops mmci_ops = {
  1577. .request = mmci_request,
  1578. .pre_req = mmci_pre_request,
  1579. .post_req = mmci_post_request,
  1580. .set_ios = mmci_set_ios,
  1581. .get_ro = mmc_gpio_get_ro,
  1582. .get_cd = mmci_get_cd,
  1583. .start_signal_voltage_switch = mmci_sig_volt_switch,
  1584. };
  1585. static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
  1586. {
  1587. struct mmci_host *host = mmc_priv(mmc);
  1588. int ret = mmc_of_parse(mmc);
  1589. if (ret)
  1590. return ret;
  1591. if (of_get_property(np, "st,sig-dir-dat0", NULL))
  1592. host->pwr_reg_add |= MCI_ST_DATA0DIREN;
  1593. if (of_get_property(np, "st,sig-dir-dat2", NULL))
  1594. host->pwr_reg_add |= MCI_ST_DATA2DIREN;
  1595. if (of_get_property(np, "st,sig-dir-dat31", NULL))
  1596. host->pwr_reg_add |= MCI_ST_DATA31DIREN;
  1597. if (of_get_property(np, "st,sig-dir-dat74", NULL))
  1598. host->pwr_reg_add |= MCI_ST_DATA74DIREN;
  1599. if (of_get_property(np, "st,sig-dir-cmd", NULL))
  1600. host->pwr_reg_add |= MCI_ST_CMDDIREN;
  1601. if (of_get_property(np, "st,sig-pin-fbclk", NULL))
  1602. host->pwr_reg_add |= MCI_ST_FBCLKEN;
  1603. if (of_get_property(np, "st,sig-dir", NULL))
  1604. host->pwr_reg_add |= MCI_STM32_DIRPOL;
  1605. if (of_get_property(np, "st,neg-edge", NULL))
  1606. host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
  1607. if (of_get_property(np, "st,use-ckin", NULL))
  1608. host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
  1609. if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
  1610. mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
  1611. if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
  1612. mmc->caps |= MMC_CAP_SD_HIGHSPEED;
  1613. return 0;
  1614. }
  1615. static int mmci_probe(struct amba_device *dev,
  1616. const struct amba_id *id)
  1617. {
  1618. struct mmci_platform_data *plat = dev->dev.platform_data;
  1619. struct device_node *np = dev->dev.of_node;
  1620. struct variant_data *variant = id->data;
  1621. struct mmci_host *host;
  1622. struct mmc_host *mmc;
  1623. int ret;
  1624. /* Must have platform data or Device Tree. */
  1625. if (!plat && !np) {
  1626. dev_err(&dev->dev, "No plat data or DT found\n");
  1627. return -EINVAL;
  1628. }
  1629. if (!plat) {
  1630. plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
  1631. if (!plat)
  1632. return -ENOMEM;
  1633. }
  1634. mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
  1635. if (!mmc)
  1636. return -ENOMEM;
  1637. ret = mmci_of_parse(np, mmc);
  1638. if (ret)
  1639. goto host_free;
  1640. host = mmc_priv(mmc);
  1641. host->mmc = mmc;
  1642. host->mmc_ops = &mmci_ops;
  1643. mmc->ops = &mmci_ops;
  1644. /*
  1645. * Some variant (STM32) doesn't have opendrain bit, nevertheless
  1646. * pins can be set accordingly using pinctrl
  1647. */
  1648. if (!variant->opendrain) {
  1649. host->pinctrl = devm_pinctrl_get(&dev->dev);
  1650. if (IS_ERR(host->pinctrl)) {
  1651. dev_err(&dev->dev, "failed to get pinctrl");
  1652. ret = PTR_ERR(host->pinctrl);
  1653. goto host_free;
  1654. }
  1655. host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
  1656. MMCI_PINCTRL_STATE_OPENDRAIN);
  1657. if (IS_ERR(host->pins_opendrain)) {
  1658. dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
  1659. ret = PTR_ERR(host->pins_opendrain);
  1660. goto host_free;
  1661. }
  1662. }
  1663. host->hw_designer = amba_manf(dev);
  1664. host->hw_revision = amba_rev(dev);
  1665. dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
  1666. dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
  1667. host->clk = devm_clk_get(&dev->dev, NULL);
  1668. if (IS_ERR(host->clk)) {
  1669. ret = PTR_ERR(host->clk);
  1670. goto host_free;
  1671. }
  1672. ret = clk_prepare_enable(host->clk);
  1673. if (ret)
  1674. goto host_free;
  1675. if (variant->qcom_fifo)
  1676. host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
  1677. else
  1678. host->get_rx_fifocnt = mmci_get_rx_fifocnt;
  1679. host->plat = plat;
  1680. host->variant = variant;
  1681. host->mclk = clk_get_rate(host->clk);
  1682. /*
  1683. * According to the spec, mclk is max 100 MHz,
  1684. * so we try to adjust the clock down to this,
  1685. * (if possible).
  1686. */
  1687. if (host->mclk > variant->f_max) {
  1688. ret = clk_set_rate(host->clk, variant->f_max);
  1689. if (ret < 0)
  1690. goto clk_disable;
  1691. host->mclk = clk_get_rate(host->clk);
  1692. dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
  1693. host->mclk);
  1694. }
  1695. host->phybase = dev->res.start;
  1696. host->base = devm_ioremap_resource(&dev->dev, &dev->res);
  1697. if (IS_ERR(host->base)) {
  1698. ret = PTR_ERR(host->base);
  1699. goto clk_disable;
  1700. }
  1701. if (variant->init)
  1702. variant->init(host);
  1703. /*
  1704. * The ARM and ST versions of the block have slightly different
  1705. * clock divider equations which means that the minimum divider
  1706. * differs too.
  1707. * on Qualcomm like controllers get the nearest minimum clock to 100Khz
  1708. */
  1709. if (variant->st_clkdiv)
  1710. mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
  1711. else if (variant->stm32_clkdiv)
  1712. mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
  1713. else if (variant->explicit_mclk_control)
  1714. mmc->f_min = clk_round_rate(host->clk, 100000);
  1715. else
  1716. mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
  1717. /*
  1718. * If no maximum operating frequency is supplied, fall back to use
  1719. * the module parameter, which has a (low) default value in case it
  1720. * is not specified. Either value must not exceed the clock rate into
  1721. * the block, of course.
  1722. */
  1723. if (mmc->f_max)
  1724. mmc->f_max = variant->explicit_mclk_control ?
  1725. min(variant->f_max, mmc->f_max) :
  1726. min(host->mclk, mmc->f_max);
  1727. else
  1728. mmc->f_max = variant->explicit_mclk_control ?
  1729. fmax : min(host->mclk, fmax);
  1730. dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
  1731. host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
  1732. if (IS_ERR(host->rst)) {
  1733. ret = PTR_ERR(host->rst);
  1734. goto clk_disable;
  1735. }
  1736. /* Get regulators and the supported OCR mask */
  1737. ret = mmc_regulator_get_supply(mmc);
  1738. if (ret)
  1739. goto clk_disable;
  1740. if (!mmc->ocr_avail)
  1741. mmc->ocr_avail = plat->ocr_mask;
  1742. else if (plat->ocr_mask)
  1743. dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
  1744. /* We support these capabilities. */
  1745. mmc->caps |= MMC_CAP_CMD23;
  1746. /*
  1747. * Enable busy detection.
  1748. */
  1749. if (variant->busy_detect) {
  1750. mmci_ops.card_busy = mmci_card_busy;
  1751. /*
  1752. * Not all variants have a flag to enable busy detection
  1753. * in the DPSM, but if they do, set it here.
  1754. */
  1755. if (variant->busy_dpsm_flag)
  1756. mmci_write_datactrlreg(host,
  1757. host->variant->busy_dpsm_flag);
  1758. mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  1759. }
  1760. /* Variants with mandatory busy timeout in HW needs R1B responses. */
  1761. if (variant->busy_timeout)
  1762. mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
  1763. /* Prepare a CMD12 - needed to clear the DPSM on some variants. */
  1764. host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
  1765. host->stop_abort.arg = 0;
  1766. host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
  1767. /* We support these PM capabilities. */
  1768. mmc->pm_caps |= MMC_PM_KEEP_POWER;
  1769. /*
  1770. * We can do SGIO
  1771. */
  1772. mmc->max_segs = NR_SG;
  1773. /*
  1774. * Since only a certain number of bits are valid in the data length
  1775. * register, we must ensure that we don't exceed 2^num-1 bytes in a
  1776. * single request.
  1777. */
  1778. mmc->max_req_size = (1 << variant->datalength_bits) - 1;
  1779. /*
  1780. * Set the maximum segment size. Since we aren't doing DMA
  1781. * (yet) we are only limited by the data length register.
  1782. */
  1783. mmc->max_seg_size = mmc->max_req_size;
  1784. /*
  1785. * Block size can be up to 2048 bytes, but must be a power of two.
  1786. */
  1787. mmc->max_blk_size = 1 << variant->datactrl_blocksz;
  1788. /*
  1789. * Limit the number of blocks transferred so that we don't overflow
  1790. * the maximum request size.
  1791. */
  1792. mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
  1793. spin_lock_init(&host->lock);
  1794. writel(0, host->base + MMCIMASK0);
  1795. if (variant->mmcimask1)
  1796. writel(0, host->base + MMCIMASK1);
  1797. writel(0xfff, host->base + MMCICLEAR);
  1798. /*
  1799. * If:
  1800. * - not using DT but using a descriptor table, or
  1801. * - using a table of descriptors ALONGSIDE DT, or
  1802. * look up these descriptors named "cd" and "wp" right here, fail
  1803. * silently of these do not exist
  1804. */
  1805. if (!np) {
  1806. ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
  1807. if (ret == -EPROBE_DEFER)
  1808. goto clk_disable;
  1809. ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
  1810. if (ret == -EPROBE_DEFER)
  1811. goto clk_disable;
  1812. }
  1813. ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq,
  1814. mmci_irq_thread, IRQF_SHARED,
  1815. DRIVER_NAME " (cmd)", host);
  1816. if (ret)
  1817. goto clk_disable;
  1818. if (!dev->irq[1])
  1819. host->singleirq = true;
  1820. else {
  1821. ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
  1822. IRQF_SHARED, DRIVER_NAME " (pio)", host);
  1823. if (ret)
  1824. goto clk_disable;
  1825. }
  1826. writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
  1827. amba_set_drvdata(dev, mmc);
  1828. dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
  1829. mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
  1830. amba_rev(dev), (unsigned long long)dev->res.start,
  1831. dev->irq[0], dev->irq[1]);
  1832. mmci_dma_setup(host);
  1833. pm_runtime_set_autosuspend_delay(&dev->dev, 50);
  1834. pm_runtime_use_autosuspend(&dev->dev);
  1835. mmc_add_host(mmc);
  1836. pm_runtime_put(&dev->dev);
  1837. return 0;
  1838. clk_disable:
  1839. clk_disable_unprepare(host->clk);
  1840. host_free:
  1841. mmc_free_host(mmc);
  1842. return ret;
  1843. }
  1844. static void mmci_remove(struct amba_device *dev)
  1845. {
  1846. struct mmc_host *mmc = amba_get_drvdata(dev);
  1847. if (mmc) {
  1848. struct mmci_host *host = mmc_priv(mmc);
  1849. struct variant_data *variant = host->variant;
  1850. /*
  1851. * Undo pm_runtime_put() in probe. We use the _sync
  1852. * version here so that we can access the primecell.
  1853. */
  1854. pm_runtime_get_sync(&dev->dev);
  1855. mmc_remove_host(mmc);
  1856. writel(0, host->base + MMCIMASK0);
  1857. if (variant->mmcimask1)
  1858. writel(0, host->base + MMCIMASK1);
  1859. writel(0, host->base + MMCICOMMAND);
  1860. writel(0, host->base + MMCIDATACTRL);
  1861. mmci_dma_release(host);
  1862. clk_disable_unprepare(host->clk);
  1863. mmc_free_host(mmc);
  1864. }
  1865. }
  1866. #ifdef CONFIG_PM
  1867. static void mmci_save(struct mmci_host *host)
  1868. {
  1869. unsigned long flags;
  1870. spin_lock_irqsave(&host->lock, flags);
  1871. writel(0, host->base + MMCIMASK0);
  1872. if (host->variant->pwrreg_nopower) {
  1873. writel(0, host->base + MMCIDATACTRL);
  1874. writel(0, host->base + MMCIPOWER);
  1875. writel(0, host->base + MMCICLOCK);
  1876. }
  1877. mmci_reg_delay(host);
  1878. spin_unlock_irqrestore(&host->lock, flags);
  1879. }
  1880. static void mmci_restore(struct mmci_host *host)
  1881. {
  1882. unsigned long flags;
  1883. spin_lock_irqsave(&host->lock, flags);
  1884. if (host->variant->pwrreg_nopower) {
  1885. writel(host->clk_reg, host->base + MMCICLOCK);
  1886. writel(host->datactrl_reg, host->base + MMCIDATACTRL);
  1887. writel(host->pwr_reg, host->base + MMCIPOWER);
  1888. }
  1889. writel(MCI_IRQENABLE | host->variant->start_err,
  1890. host->base + MMCIMASK0);
  1891. mmci_reg_delay(host);
  1892. spin_unlock_irqrestore(&host->lock, flags);
  1893. }
  1894. static int mmci_runtime_suspend(struct device *dev)
  1895. {
  1896. struct amba_device *adev = to_amba_device(dev);
  1897. struct mmc_host *mmc = amba_get_drvdata(adev);
  1898. if (mmc) {
  1899. struct mmci_host *host = mmc_priv(mmc);
  1900. pinctrl_pm_select_sleep_state(dev);
  1901. mmci_save(host);
  1902. clk_disable_unprepare(host->clk);
  1903. }
  1904. return 0;
  1905. }
  1906. static int mmci_runtime_resume(struct device *dev)
  1907. {
  1908. struct amba_device *adev = to_amba_device(dev);
  1909. struct mmc_host *mmc = amba_get_drvdata(adev);
  1910. if (mmc) {
  1911. struct mmci_host *host = mmc_priv(mmc);
  1912. clk_prepare_enable(host->clk);
  1913. mmci_restore(host);
  1914. pinctrl_select_default_state(dev);
  1915. }
  1916. return 0;
  1917. }
  1918. #endif
  1919. static const struct dev_pm_ops mmci_dev_pm_ops = {
  1920. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1921. pm_runtime_force_resume)
  1922. SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
  1923. };
  1924. static const struct amba_id mmci_ids[] = {
  1925. {
  1926. .id = 0x00041180,
  1927. .mask = 0xff0fffff,
  1928. .data = &variant_arm,
  1929. },
  1930. {
  1931. .id = 0x01041180,
  1932. .mask = 0xff0fffff,
  1933. .data = &variant_arm_extended_fifo,
  1934. },
  1935. {
  1936. .id = 0x02041180,
  1937. .mask = 0xff0fffff,
  1938. .data = &variant_arm_extended_fifo_hwfc,
  1939. },
  1940. {
  1941. .id = 0x00041181,
  1942. .mask = 0x000fffff,
  1943. .data = &variant_arm,
  1944. },
  1945. /* ST Micro variants */
  1946. {
  1947. .id = 0x00180180,
  1948. .mask = 0x00ffffff,
  1949. .data = &variant_u300,
  1950. },
  1951. {
  1952. .id = 0x10180180,
  1953. .mask = 0xf0ffffff,
  1954. .data = &variant_nomadik,
  1955. },
  1956. {
  1957. .id = 0x00280180,
  1958. .mask = 0x00ffffff,
  1959. .data = &variant_nomadik,
  1960. },
  1961. {
  1962. .id = 0x00480180,
  1963. .mask = 0xf0ffffff,
  1964. .data = &variant_ux500,
  1965. },
  1966. {
  1967. .id = 0x10480180,
  1968. .mask = 0xf0ffffff,
  1969. .data = &variant_ux500v2,
  1970. },
  1971. {
  1972. .id = 0x00880180,
  1973. .mask = 0x00ffffff,
  1974. .data = &variant_stm32,
  1975. },
  1976. {
  1977. .id = 0x10153180,
  1978. .mask = 0xf0ffffff,
  1979. .data = &variant_stm32_sdmmc,
  1980. },
  1981. {
  1982. .id = 0x00253180,
  1983. .mask = 0xf0ffffff,
  1984. .data = &variant_stm32_sdmmcv2,
  1985. },
  1986. /* Qualcomm variants */
  1987. {
  1988. .id = 0x00051180,
  1989. .mask = 0x000fffff,
  1990. .data = &variant_qcom,
  1991. },
  1992. { 0, 0 },
  1993. };
  1994. MODULE_DEVICE_TABLE(amba, mmci_ids);
  1995. static struct amba_driver mmci_driver = {
  1996. .drv = {
  1997. .name = DRIVER_NAME,
  1998. .pm = &mmci_dev_pm_ops,
  1999. },
  2000. .probe = mmci_probe,
  2001. .remove = mmci_remove,
  2002. .id_table = mmci_ids,
  2003. };
  2004. module_amba_driver(mmci_driver);
  2005. module_param(fmax, uint, 0444);
  2006. MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
  2007. MODULE_LICENSE("GPL");