meson-mx-sdhc-mmc.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver.
  4. *
  5. * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/property.h>
  16. #include <linux/regmap.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/types.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/mmc/sdio.h>
  22. #include <linux/mmc/slot-gpio.h>
  23. #include "meson-mx-sdhc.h"
  24. #define MESON_SDHC_NUM_BULK_CLKS 4
  25. #define MESON_SDHC_MAX_BLK_SIZE 512
  26. #define MESON_SDHC_NUM_TUNING_TRIES 10
  27. #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US 1
  28. #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US 100000
  29. #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US 1
  30. #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US 200
  31. struct meson_mx_sdhc_data {
  32. void (*init_hw)(struct mmc_host *mmc);
  33. void (*set_pdma)(struct mmc_host *mmc);
  34. void (*wait_before_send)(struct mmc_host *mmc);
  35. bool hardware_flush_all_cmds;
  36. };
  37. struct meson_mx_sdhc_host {
  38. struct mmc_host *mmc;
  39. struct mmc_request *mrq;
  40. struct mmc_command *cmd;
  41. int error;
  42. struct regmap *regmap;
  43. struct clk *pclk;
  44. struct clk *sd_clk;
  45. struct clk_bulk_data bulk_clks[MESON_SDHC_NUM_BULK_CLKS];
  46. bool bulk_clks_enabled;
  47. const struct meson_mx_sdhc_data *platform;
  48. };
  49. static const struct regmap_config meson_mx_sdhc_regmap_config = {
  50. .reg_bits = 8,
  51. .val_bits = 32,
  52. .reg_stride = 4,
  53. .max_register = MESON_SDHC_CLK2,
  54. };
  55. static void meson_mx_sdhc_hw_reset(struct mmc_host *mmc)
  56. {
  57. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  58. regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL |
  59. MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO |
  60. MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX |
  61. MESON_SDHC_SRST_DMA_IF);
  62. usleep_range(10, 100);
  63. regmap_write(host->regmap, MESON_SDHC_SRST, 0);
  64. usleep_range(10, 100);
  65. }
  66. static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc)
  67. {
  68. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  69. u32 stat;
  70. regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
  71. if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) &&
  72. !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
  73. return;
  74. regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO |
  75. MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL);
  76. udelay(5);
  77. regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
  78. if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) ||
  79. FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
  80. dev_warn(mmc_dev(host->mmc),
  81. "Failed to clear FIFOs, RX: %lu, TX: %lu\n",
  82. FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat),
  83. FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat));
  84. }
  85. static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc)
  86. {
  87. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  88. u32 stat, esta;
  89. int ret;
  90. ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat,
  91. !(stat & MESON_SDHC_STAT_CMD_BUSY),
  92. MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
  93. MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
  94. if (ret) {
  95. dev_warn(mmc_dev(mmc),
  96. "Failed to poll for CMD_BUSY while processing CMD%d\n",
  97. host->cmd->opcode);
  98. meson_mx_sdhc_hw_reset(mmc);
  99. }
  100. ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta,
  101. !(esta & MESON_SDHC_ESTA_11_13),
  102. MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
  103. MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
  104. if (ret) {
  105. dev_warn(mmc_dev(mmc),
  106. "Failed to poll for ESTA[13:11] while processing CMD%d\n",
  107. host->cmd->opcode);
  108. meson_mx_sdhc_hw_reset(mmc);
  109. }
  110. }
  111. static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc,
  112. struct mmc_command *cmd)
  113. {
  114. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  115. bool manual_stop = false;
  116. u32 ictl, send;
  117. int pack_len;
  118. host->cmd = cmd;
  119. ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC |
  120. MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY |
  121. MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC;
  122. send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode);
  123. if (cmd->data) {
  124. send |= MESON_SDHC_SEND_CMD_HAS_DATA;
  125. send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK,
  126. cmd->data->blocks - 1);
  127. if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE)
  128. pack_len = cmd->data->blksz;
  129. else
  130. pack_len = 0;
  131. if (cmd->data->flags & MMC_DATA_WRITE)
  132. send |= MESON_SDHC_SEND_DATA_DIR;
  133. /*
  134. * If command with no data, just wait response done
  135. * interrupt(int[0]), and if command with data transfer, just
  136. * wait dma done interrupt(int[11]), don't need care about
  137. * dat0 busy or not.
  138. */
  139. if (host->platform->hardware_flush_all_cmds ||
  140. cmd->data->flags & MMC_DATA_WRITE)
  141. /* hardware flush: */
  142. ictl |= MESON_SDHC_ICTL_DMA_DONE;
  143. else
  144. /* software flush: */
  145. ictl |= MESON_SDHC_ICTL_DATA_XFER_OK;
  146. /*
  147. * Mimic the logic from the vendor driver where (only)
  148. * SD_IO_RW_EXTENDED commands with more than one block set the
  149. * MESON_SDHC_MISC_MANUAL_STOP bit. This fixes the firmware
  150. * download in the brcmfmac driver for a BCM43362/1 card.
  151. * Without this sdio_memcpy_toio() (with a size of 219557
  152. * bytes) times out if MESON_SDHC_MISC_MANUAL_STOP is not set.
  153. */
  154. manual_stop = cmd->data->blocks > 1 &&
  155. cmd->opcode == SD_IO_RW_EXTENDED;
  156. } else {
  157. pack_len = 0;
  158. ictl |= MESON_SDHC_ICTL_RESP_OK;
  159. }
  160. regmap_update_bits(host->regmap, MESON_SDHC_MISC,
  161. MESON_SDHC_MISC_MANUAL_STOP,
  162. manual_stop ? MESON_SDHC_MISC_MANUAL_STOP : 0);
  163. if (cmd->opcode == MMC_STOP_TRANSMISSION)
  164. send |= MESON_SDHC_SEND_DATA_STOP;
  165. if (cmd->flags & MMC_RSP_PRESENT)
  166. send |= MESON_SDHC_SEND_CMD_HAS_RESP;
  167. if (cmd->flags & MMC_RSP_136) {
  168. send |= MESON_SDHC_SEND_RESP_LEN;
  169. send |= MESON_SDHC_SEND_RESP_NO_CRC;
  170. }
  171. if (!(cmd->flags & MMC_RSP_CRC))
  172. send |= MESON_SDHC_SEND_RESP_NO_CRC;
  173. if (cmd->flags & MMC_RSP_BUSY)
  174. send |= MESON_SDHC_SEND_R1B;
  175. /* enable the new IRQs and mask all pending ones */
  176. regmap_write(host->regmap, MESON_SDHC_ICTL, ictl);
  177. regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
  178. regmap_write(host->regmap, MESON_SDHC_ARGU, cmd->arg);
  179. regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
  180. MESON_SDHC_CTRL_PACK_LEN,
  181. FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len));
  182. if (cmd->data)
  183. regmap_write(host->regmap, MESON_SDHC_ADDR,
  184. sg_dma_address(cmd->data->sg));
  185. meson_mx_sdhc_wait_cmd_ready(mmc);
  186. if (cmd->data)
  187. host->platform->set_pdma(mmc);
  188. if (host->platform->wait_before_send)
  189. host->platform->wait_before_send(mmc);
  190. regmap_write(host->regmap, MESON_SDHC_SEND, send);
  191. }
  192. static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc)
  193. {
  194. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  195. if (!host->bulk_clks_enabled)
  196. return;
  197. clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, host->bulk_clks);
  198. host->bulk_clks_enabled = false;
  199. }
  200. static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
  201. {
  202. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  203. int ret;
  204. if (host->bulk_clks_enabled)
  205. return 0;
  206. ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS,
  207. host->bulk_clks);
  208. if (ret)
  209. return ret;
  210. host->bulk_clks_enabled = true;
  211. return 0;
  212. }
  213. static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
  214. {
  215. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  216. u32 rx_clk_phase;
  217. int ret;
  218. meson_mx_sdhc_disable_clks(mmc);
  219. if (ios->clock) {
  220. ret = clk_set_rate(host->sd_clk, ios->clock);
  221. if (ret) {
  222. dev_warn(mmc_dev(mmc),
  223. "Failed to set MMC clock to %uHz: %d\n",
  224. ios->clock, host->error);
  225. return ret;
  226. }
  227. ret = meson_mx_sdhc_enable_clks(mmc);
  228. if (ret)
  229. return ret;
  230. mmc->actual_clock = clk_get_rate(host->sd_clk);
  231. /*
  232. * according to Amlogic the following latching points are
  233. * selected with empirical values, there is no (known) formula
  234. * to calculate these.
  235. */
  236. if (mmc->actual_clock > 100000000) {
  237. rx_clk_phase = 1;
  238. } else if (mmc->actual_clock > 45000000) {
  239. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  240. rx_clk_phase = 15;
  241. else
  242. rx_clk_phase = 11;
  243. } else if (mmc->actual_clock >= 25000000) {
  244. rx_clk_phase = 15;
  245. } else if (mmc->actual_clock > 5000000) {
  246. rx_clk_phase = 23;
  247. } else if (mmc->actual_clock > 1000000) {
  248. rx_clk_phase = 55;
  249. } else {
  250. rx_clk_phase = 1061;
  251. }
  252. regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
  253. MESON_SDHC_CLK2_RX_CLK_PHASE,
  254. FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
  255. rx_clk_phase));
  256. } else {
  257. mmc->actual_clock = 0;
  258. }
  259. return 0;
  260. }
  261. static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  262. {
  263. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  264. unsigned short vdd = ios->vdd;
  265. switch (ios->power_mode) {
  266. case MMC_POWER_OFF:
  267. vdd = 0;
  268. fallthrough;
  269. case MMC_POWER_UP:
  270. if (!IS_ERR(mmc->supply.vmmc)) {
  271. host->error = mmc_regulator_set_ocr(mmc,
  272. mmc->supply.vmmc,
  273. vdd);
  274. if (host->error)
  275. return;
  276. }
  277. break;
  278. case MMC_POWER_ON:
  279. break;
  280. }
  281. host->error = meson_mx_sdhc_set_clk(mmc, ios);
  282. if (host->error)
  283. return;
  284. switch (ios->bus_width) {
  285. case MMC_BUS_WIDTH_1:
  286. regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
  287. MESON_SDHC_CTRL_DAT_TYPE,
  288. FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0));
  289. break;
  290. case MMC_BUS_WIDTH_4:
  291. regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
  292. MESON_SDHC_CTRL_DAT_TYPE,
  293. FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1));
  294. break;
  295. case MMC_BUS_WIDTH_8:
  296. regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
  297. MESON_SDHC_CTRL_DAT_TYPE,
  298. FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2));
  299. break;
  300. default:
  301. dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
  302. ios->bus_width);
  303. host->error = -EINVAL;
  304. return;
  305. }
  306. }
  307. static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
  308. {
  309. struct mmc_data *data = mrq->data;
  310. int dma_len;
  311. if (!data)
  312. return 0;
  313. dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
  314. mmc_get_dma_dir(data));
  315. if (dma_len <= 0) {
  316. dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
  317. return -ENOMEM;
  318. }
  319. return 0;
  320. }
  321. static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  322. {
  323. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  324. struct mmc_command *cmd = mrq->cmd;
  325. if (!host->error)
  326. host->error = meson_mx_sdhc_map_dma(mmc, mrq);
  327. if (host->error) {
  328. cmd->error = host->error;
  329. mmc_request_done(mmc, mrq);
  330. return;
  331. }
  332. host->mrq = mrq;
  333. meson_mx_sdhc_start_cmd(mmc, mrq->cmd);
  334. }
  335. static int meson_mx_sdhc_card_busy(struct mmc_host *mmc)
  336. {
  337. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  338. u32 stat;
  339. regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
  340. return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0;
  341. }
  342. static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc,
  343. u32 opcode)
  344. {
  345. unsigned int i, num_matches = 0;
  346. int ret;
  347. for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) {
  348. ret = mmc_send_tuning(mmc, opcode, NULL);
  349. if (!ret)
  350. num_matches++;
  351. }
  352. return num_matches == MESON_SDHC_NUM_TUNING_TRIES;
  353. }
  354. static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
  355. {
  356. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  357. int div, start, len, best_start, best_len;
  358. int curr_phase, old_phase, new_phase;
  359. u32 val;
  360. len = 0;
  361. start = 0;
  362. best_len = 0;
  363. regmap_read(host->regmap, MESON_SDHC_CLK2, &val);
  364. old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val);
  365. regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
  366. div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val);
  367. for (curr_phase = 0; curr_phase <= div; curr_phase++) {
  368. regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
  369. MESON_SDHC_CLK2_RX_CLK_PHASE,
  370. FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
  371. curr_phase));
  372. if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) {
  373. if (!len) {
  374. start = curr_phase;
  375. dev_dbg(mmc_dev(mmc),
  376. "New RX phase window starts at %u\n",
  377. start);
  378. }
  379. len++;
  380. } else {
  381. if (len > best_len) {
  382. best_start = start;
  383. best_len = len;
  384. dev_dbg(mmc_dev(mmc),
  385. "New best RX phase window: %u - %u\n",
  386. best_start, best_start + best_len);
  387. }
  388. /* reset the current window */
  389. len = 0;
  390. }
  391. }
  392. if (len > best_len)
  393. /* the last window is the best (or possibly only) window */
  394. new_phase = start + (len / 2);
  395. else if (best_len)
  396. /* there was a better window than the last */
  397. new_phase = best_start + (best_len / 2);
  398. else
  399. /* no window was found at all, reset to the original phase */
  400. new_phase = old_phase;
  401. regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
  402. MESON_SDHC_CLK2_RX_CLK_PHASE,
  403. FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
  404. new_phase));
  405. if (!len && !best_len)
  406. return -EIO;
  407. dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n", new_phase);
  408. return 0;
  409. }
  410. static const struct mmc_host_ops meson_mx_sdhc_ops = {
  411. .hw_reset = meson_mx_sdhc_hw_reset,
  412. .request = meson_mx_sdhc_request,
  413. .set_ios = meson_mx_sdhc_set_ios,
  414. .card_busy = meson_mx_sdhc_card_busy,
  415. .execute_tuning = meson_mx_sdhc_execute_tuning,
  416. .get_cd = mmc_gpio_get_cd,
  417. .get_ro = mmc_gpio_get_ro,
  418. };
  419. static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host)
  420. {
  421. struct mmc_request *mrq = host->mrq;
  422. struct mmc_host *mmc = host->mmc;
  423. /* disable interrupts and mask all pending ones */
  424. regmap_update_bits(host->regmap, MESON_SDHC_ICTL,
  425. MESON_SDHC_ICTL_ALL_IRQS, 0);
  426. regmap_update_bits(host->regmap, MESON_SDHC_ISTA,
  427. MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS);
  428. host->mrq = NULL;
  429. host->cmd = NULL;
  430. mmc_request_done(mmc, mrq);
  431. }
  432. static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx)
  433. {
  434. u32 val;
  435. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  436. MESON_SDHC_PDMA_DMA_MODE, 0);
  437. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  438. MESON_SDHC_PDMA_PIO_RDRESP,
  439. FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx));
  440. regmap_read(host->regmap, MESON_SDHC_ARGU, &val);
  441. return val;
  442. }
  443. static irqreturn_t meson_mx_sdhc_irq(int irq, void *data)
  444. {
  445. struct meson_mx_sdhc_host *host = data;
  446. struct mmc_command *cmd = host->cmd;
  447. u32 ictl, ista;
  448. regmap_read(host->regmap, MESON_SDHC_ICTL, &ictl);
  449. regmap_read(host->regmap, MESON_SDHC_ISTA, &ista);
  450. if (!(ictl & ista))
  451. return IRQ_NONE;
  452. if (ista & MESON_SDHC_ISTA_RXFIFO_FULL ||
  453. ista & MESON_SDHC_ISTA_TXFIFO_EMPTY)
  454. cmd->error = -EIO;
  455. else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC)
  456. cmd->error = -EILSEQ;
  457. else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT)
  458. cmd->error = -ETIMEDOUT;
  459. if (cmd->data) {
  460. if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC)
  461. cmd->data->error = -EILSEQ;
  462. else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT)
  463. cmd->data->error = -ETIMEDOUT;
  464. }
  465. if (cmd->error || (cmd->data && cmd->data->error))
  466. dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n",
  467. cmd->opcode, ista);
  468. return IRQ_WAKE_THREAD;
  469. }
  470. static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data)
  471. {
  472. struct meson_mx_sdhc_host *host = irq_data;
  473. struct mmc_command *cmd;
  474. u32 val;
  475. cmd = host->cmd;
  476. if (WARN_ON(!cmd))
  477. return IRQ_HANDLED;
  478. if (cmd->data && !cmd->data->error) {
  479. if (!host->platform->hardware_flush_all_cmds &&
  480. cmd->data->flags & MMC_DATA_READ) {
  481. meson_mx_sdhc_wait_cmd_ready(host->mmc);
  482. /*
  483. * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was
  484. * previously 0x1 then it has to be set to 0x3. If it
  485. * was 0x0 before then it has to be set to 0x2. Without
  486. * this reading SD cards sometimes transfers garbage,
  487. * which results in cards not being detected due to:
  488. * unrecognised SCR structure version <random number>
  489. */
  490. val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
  491. 2);
  492. regmap_update_bits(host->regmap, MESON_SDHC_PDMA, val,
  493. val);
  494. }
  495. dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
  496. cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
  497. cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
  498. }
  499. meson_mx_sdhc_wait_cmd_ready(host->mmc);
  500. if (cmd->flags & MMC_RSP_136) {
  501. cmd->resp[0] = meson_mx_sdhc_read_response(host, 4);
  502. cmd->resp[1] = meson_mx_sdhc_read_response(host, 3);
  503. cmd->resp[2] = meson_mx_sdhc_read_response(host, 2);
  504. cmd->resp[3] = meson_mx_sdhc_read_response(host, 1);
  505. } else {
  506. cmd->resp[0] = meson_mx_sdhc_read_response(host, 0);
  507. }
  508. if (cmd->error == -EIO || cmd->error == -ETIMEDOUT)
  509. meson_mx_sdhc_hw_reset(host->mmc);
  510. else if (cmd->data)
  511. /*
  512. * Clear the FIFOs after completing data transfers to prevent
  513. * corrupting data on write access. It's not clear why this is
  514. * needed (for reads and writes), but it mimics what the BSP
  515. * kernel did.
  516. */
  517. meson_mx_sdhc_clear_fifo(host->mmc);
  518. meson_mx_sdhc_request_done(host);
  519. return IRQ_HANDLED;
  520. }
  521. static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc)
  522. {
  523. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  524. regmap_write(host->regmap, MESON_SDHC_MISC,
  525. FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) |
  526. FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
  527. FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
  528. regmap_write(host->regmap, MESON_SDHC_ENHC,
  529. FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) |
  530. MESON_SDHC_ENHC_MESON6_DMA_WR_RESP |
  531. FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) |
  532. FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
  533. };
  534. static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc)
  535. {
  536. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  537. if (host->cmd->data->flags & MMC_DATA_WRITE)
  538. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  539. MESON_SDHC_PDMA_DMA_MODE |
  540. MESON_SDHC_PDMA_RD_BURST |
  541. MESON_SDHC_PDMA_TXFIFO_FILL,
  542. MESON_SDHC_PDMA_DMA_MODE |
  543. FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) |
  544. MESON_SDHC_PDMA_TXFIFO_FILL);
  545. else
  546. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  547. MESON_SDHC_PDMA_DMA_MODE |
  548. MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
  549. MESON_SDHC_PDMA_DMA_MODE |
  550. FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
  551. 1));
  552. if (host->cmd->data->flags & MMC_DATA_WRITE)
  553. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  554. MESON_SDHC_PDMA_RD_BURST,
  555. FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15));
  556. }
  557. static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc)
  558. {
  559. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  560. u32 val;
  561. int ret;
  562. ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val,
  563. val == 0,
  564. MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
  565. MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
  566. if (ret)
  567. dev_warn(mmc_dev(mmc),
  568. "Failed to wait for ESTA to clear: 0x%08x\n", val);
  569. if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) {
  570. ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT,
  571. val, val & MESON_SDHC_STAT_TXFIFO_CNT,
  572. MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
  573. MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
  574. if (ret)
  575. dev_warn(mmc_dev(mmc),
  576. "Failed to wait for TX FIFO to fill\n");
  577. }
  578. }
  579. static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc)
  580. {
  581. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  582. regmap_write(host->regmap, MESON_SDHC_MISC,
  583. FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) |
  584. FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
  585. FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
  586. regmap_write(host->regmap, MESON_SDHC_ENHC,
  587. FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) |
  588. FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) |
  589. MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE |
  590. FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
  591. }
  592. static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc)
  593. {
  594. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  595. regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
  596. MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE);
  597. }
  598. static void meson_mx_sdhc_init_hw(struct mmc_host *mmc)
  599. {
  600. struct meson_mx_sdhc_host *host = mmc_priv(mmc);
  601. meson_mx_sdhc_hw_reset(mmc);
  602. regmap_write(host->regmap, MESON_SDHC_CTRL,
  603. FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) |
  604. FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) |
  605. FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) |
  606. FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7));
  607. /*
  608. * start with a valid divider and enable the memory (un-setting
  609. * MESON_SDHC_CLKC_MEM_PWR_OFF).
  610. */
  611. regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV);
  612. regmap_write(host->regmap, MESON_SDHC_CLK2,
  613. FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1));
  614. regmap_write(host->regmap, MESON_SDHC_PDMA,
  615. MESON_SDHC_PDMA_DMA_URGENT |
  616. FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) |
  617. FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) |
  618. FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) |
  619. FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7));
  620. /* some initialization bits depend on the SoC: */
  621. host->platform->init_hw(mmc);
  622. /* disable and mask all interrupts: */
  623. regmap_write(host->regmap, MESON_SDHC_ICTL, 0);
  624. regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
  625. }
  626. static int meson_mx_sdhc_probe(struct platform_device *pdev)
  627. {
  628. struct device *dev = &pdev->dev;
  629. struct meson_mx_sdhc_host *host;
  630. struct mmc_host *mmc;
  631. void __iomem *base;
  632. int ret, irq;
  633. mmc = mmc_alloc_host(sizeof(*host), dev);
  634. if (!mmc)
  635. return -ENOMEM;
  636. ret = devm_add_action_or_reset(dev, (void(*)(void *))mmc_free_host,
  637. mmc);
  638. if (ret) {
  639. dev_err(dev, "Failed to register mmc_free_host action\n");
  640. return ret;
  641. }
  642. host = mmc_priv(mmc);
  643. host->mmc = mmc;
  644. platform_set_drvdata(pdev, host);
  645. host->platform = device_get_match_data(dev);
  646. if (!host->platform)
  647. return -EINVAL;
  648. base = devm_platform_ioremap_resource(pdev, 0);
  649. if (IS_ERR(base))
  650. return PTR_ERR(base);
  651. host->regmap = devm_regmap_init_mmio(dev, base,
  652. &meson_mx_sdhc_regmap_config);
  653. if (IS_ERR(host->regmap))
  654. return PTR_ERR(host->regmap);
  655. host->pclk = devm_clk_get(dev, "pclk");
  656. if (IS_ERR(host->pclk))
  657. return PTR_ERR(host->pclk);
  658. /* accessing any register requires the module clock to be enabled: */
  659. ret = clk_prepare_enable(host->pclk);
  660. if (ret) {
  661. dev_err(dev, "Failed to enable 'pclk' clock\n");
  662. return ret;
  663. }
  664. meson_mx_sdhc_init_hw(mmc);
  665. ret = meson_mx_sdhc_register_clkc(dev, base, host->bulk_clks);
  666. if (ret)
  667. goto err_disable_pclk;
  668. host->sd_clk = host->bulk_clks[1].clk;
  669. /* Get regulators and the supported OCR mask */
  670. ret = mmc_regulator_get_supply(mmc);
  671. if (ret)
  672. goto err_disable_pclk;
  673. mmc->max_req_size = SZ_128K;
  674. mmc->max_seg_size = mmc->max_req_size;
  675. mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0);
  676. mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE;
  677. mmc->max_busy_timeout = 30 * MSEC_PER_SEC;
  678. mmc->f_min = clk_round_rate(host->sd_clk, 1);
  679. mmc->f_max = clk_round_rate(host->sd_clk, ULONG_MAX);
  680. mmc->max_current_180 = 300;
  681. mmc->max_current_330 = 300;
  682. mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET;
  683. mmc->ops = &meson_mx_sdhc_ops;
  684. ret = mmc_of_parse(mmc);
  685. if (ret)
  686. goto err_disable_pclk;
  687. irq = platform_get_irq(pdev, 0);
  688. if (irq < 0) {
  689. ret = irq;
  690. goto err_disable_pclk;
  691. }
  692. ret = devm_request_threaded_irq(dev, irq, meson_mx_sdhc_irq,
  693. meson_mx_sdhc_irq_thread, IRQF_ONESHOT,
  694. NULL, host);
  695. if (ret)
  696. goto err_disable_pclk;
  697. ret = mmc_add_host(mmc);
  698. if (ret)
  699. goto err_disable_pclk;
  700. return 0;
  701. err_disable_pclk:
  702. clk_disable_unprepare(host->pclk);
  703. return ret;
  704. }
  705. static int meson_mx_sdhc_remove(struct platform_device *pdev)
  706. {
  707. struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev);
  708. mmc_remove_host(host->mmc);
  709. meson_mx_sdhc_disable_clks(host->mmc);
  710. clk_disable_unprepare(host->pclk);
  711. return 0;
  712. }
  713. static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = {
  714. .init_hw = meson_mx_sdhc_init_hw_meson8,
  715. .set_pdma = meson_mx_sdhc_set_pdma_meson8,
  716. .wait_before_send = meson_mx_sdhc_wait_before_send_meson8,
  717. .hardware_flush_all_cmds = false,
  718. };
  719. static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = {
  720. .init_hw = meson_mx_sdhc_init_hw_meson8m2,
  721. .set_pdma = meson_mx_sdhc_set_pdma_meson8m2,
  722. .hardware_flush_all_cmds = true,
  723. };
  724. static const struct of_device_id meson_mx_sdhc_of_match[] = {
  725. {
  726. .compatible = "amlogic,meson8-sdhc",
  727. .data = &meson_mx_sdhc_data_meson8
  728. },
  729. {
  730. .compatible = "amlogic,meson8b-sdhc",
  731. .data = &meson_mx_sdhc_data_meson8
  732. },
  733. {
  734. .compatible = "amlogic,meson8m2-sdhc",
  735. .data = &meson_mx_sdhc_data_meson8m2
  736. },
  737. { /* sentinel */ }
  738. };
  739. MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match);
  740. static struct platform_driver meson_mx_sdhc_driver = {
  741. .probe = meson_mx_sdhc_probe,
  742. .remove = meson_mx_sdhc_remove,
  743. .driver = {
  744. .name = "meson-mx-sdhc",
  745. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  746. .of_match_table = of_match_ptr(meson_mx_sdhc_of_match),
  747. },
  748. };
  749. module_platform_driver(meson_mx_sdhc_driver);
  750. MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver");
  751. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  752. MODULE_LICENSE("GPL v2");