dw_mmc.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Synopsys DesignWare Multimedia Card Interface driver
  4. * (Based on NXP driver for lpc 31xx)
  5. *
  6. * Copyright (C) 2009 NXP Semiconductors
  7. * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  8. */
  9. #ifndef _DW_MMC_H_
  10. #define _DW_MMC_H_
  11. #include <linux/scatterlist.h>
  12. #include <linux/mmc/core.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/reset.h>
  15. #include <linux/interrupt.h>
  16. enum dw_mci_state {
  17. STATE_IDLE = 0,
  18. STATE_SENDING_CMD,
  19. STATE_SENDING_DATA,
  20. STATE_DATA_BUSY,
  21. STATE_SENDING_STOP,
  22. STATE_DATA_ERROR,
  23. STATE_SENDING_CMD11,
  24. STATE_WAITING_CMD11_DONE,
  25. };
  26. enum {
  27. EVENT_CMD_COMPLETE = 0,
  28. EVENT_XFER_COMPLETE,
  29. EVENT_DATA_COMPLETE,
  30. EVENT_DATA_ERROR,
  31. };
  32. enum dw_mci_cookie {
  33. COOKIE_UNMAPPED,
  34. COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
  35. COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
  36. };
  37. struct mmc_data;
  38. enum {
  39. TRANS_MODE_PIO = 0,
  40. TRANS_MODE_IDMAC,
  41. TRANS_MODE_EDMAC
  42. };
  43. struct dw_mci_dma_slave {
  44. struct dma_chan *ch;
  45. enum dma_transfer_direction direction;
  46. };
  47. /**
  48. * struct dw_mci - MMC controller state shared between all slots
  49. * @lock: Spinlock protecting the queue and associated data.
  50. * @irq_lock: Spinlock protecting the INTMASK setting.
  51. * @regs: Pointer to MMIO registers.
  52. * @fifo_reg: Pointer to MMIO registers for data FIFO
  53. * @sg: Scatterlist entry currently being processed by PIO code, if any.
  54. * @sg_miter: PIO mapping scatterlist iterator.
  55. * @mrq: The request currently being processed on @slot,
  56. * or NULL if the controller is idle.
  57. * @cmd: The command currently being sent to the card, or NULL.
  58. * @data: The data currently being transferred, or NULL if no data
  59. * transfer is in progress.
  60. * @stop_abort: The command currently prepared for stoping transfer.
  61. * @prev_blksz: The former transfer blksz record.
  62. * @timing: Record of current ios timing.
  63. * @use_dma: Which DMA channel is in use for the current transfer, zero
  64. * denotes PIO mode.
  65. * @using_dma: Whether DMA is in use for the current transfer.
  66. * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
  67. * @sg_dma: Bus address of DMA buffer.
  68. * @sg_cpu: Virtual address of DMA buffer.
  69. * @dma_ops: Pointer to platform-specific DMA callbacks.
  70. * @cmd_status: Snapshot of SR taken upon completion of the current
  71. * @ring_size: Buffer size for idma descriptors.
  72. * command. Only valid when EVENT_CMD_COMPLETE is pending.
  73. * @dms: structure of slave-dma private data.
  74. * @phy_regs: physical address of controller's register map
  75. * @data_status: Snapshot of SR taken upon completion of the current
  76. * data transfer. Only valid when EVENT_DATA_COMPLETE or
  77. * EVENT_DATA_ERROR is pending.
  78. * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  79. * to be sent.
  80. * @dir_status: Direction of current transfer.
  81. * @tasklet: Tasklet running the request state machine.
  82. * @pending_events: Bitmask of events flagged by the interrupt handler
  83. * to be processed by the tasklet.
  84. * @completed_events: Bitmask of events which the state machine has
  85. * processed.
  86. * @state: Tasklet state.
  87. * @queue: List of slots waiting for access to the controller.
  88. * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  89. * rate and timeout calculations.
  90. * @current_speed: Configured rate of the controller.
  91. * @fifoth_val: The value of FIFOTH register.
  92. * @verid: Denote Version ID.
  93. * @dev: Device associated with the MMC controller.
  94. * @pdata: Platform data associated with the MMC controller.
  95. * @drv_data: Driver specific data for identified variant of the controller
  96. * @priv: Implementation defined private data.
  97. * @biu_clk: Pointer to bus interface unit clock instance.
  98. * @ciu_clk: Pointer to card interface unit clock instance.
  99. * @slot: Slots sharing this MMC controller.
  100. * @fifo_depth: depth of FIFO.
  101. * @data_addr_override: override fifo reg offset with this value.
  102. * @wm_aligned: force fifo watermark equal with data length in PIO mode.
  103. * Set as true if alignment is needed.
  104. * @data_shift: log2 of FIFO item size.
  105. * @part_buf_start: Start index in part_buf.
  106. * @part_buf_count: Bytes of partial data in part_buf.
  107. * @part_buf: Simple buffer for partial fifo reads/writes.
  108. * @push_data: Pointer to FIFO push function.
  109. * @pull_data: Pointer to FIFO pull function.
  110. * @vqmmc_enabled: Status of vqmmc, should be true or false.
  111. * @irq_flags: The flags to be passed to request_irq.
  112. * @irq: The irq value to be passed to request_irq.
  113. * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
  114. * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
  115. * @cto_timer: Timer for broken command transfer over scheme.
  116. * @dto_timer: Timer for broken data transfer over scheme.
  117. *
  118. * Locking
  119. * =======
  120. *
  121. * @lock is a softirq-safe spinlock protecting @queue as well as
  122. * @slot, @mrq and @state. These must always be updated
  123. * at the same time while holding @lock.
  124. * The @mrq field of struct dw_mci_slot is also protected by @lock,
  125. * and must always be written at the same time as the slot is added to
  126. * @queue.
  127. *
  128. * @irq_lock is an irq-safe spinlock protecting the INTMASK register
  129. * to allow the interrupt handler to modify it directly. Held for only long
  130. * enough to read-modify-write INTMASK and no other locks are grabbed when
  131. * holding this one.
  132. *
  133. * @pending_events and @completed_events are accessed using atomic bit
  134. * operations, so they don't need any locking.
  135. *
  136. * None of the fields touched by the interrupt handler need any
  137. * locking. However, ordering is important: Before EVENT_DATA_ERROR or
  138. * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
  139. * interrupts must be disabled and @data_status updated with a
  140. * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
  141. * CMDRDY interrupt must be disabled and @cmd_status updated with a
  142. * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
  143. * bytes_xfered field of @data must be written. This is ensured by
  144. * using barriers.
  145. */
  146. struct dw_mci {
  147. spinlock_t lock;
  148. spinlock_t irq_lock;
  149. void __iomem *regs;
  150. void __iomem *fifo_reg;
  151. u32 data_addr_override;
  152. bool wm_aligned;
  153. struct scatterlist *sg;
  154. struct sg_mapping_iter sg_miter;
  155. struct mmc_request *mrq;
  156. struct mmc_command *cmd;
  157. struct mmc_data *data;
  158. struct mmc_command stop_abort;
  159. unsigned int prev_blksz;
  160. unsigned char timing;
  161. /* DMA interface members*/
  162. int use_dma;
  163. int using_dma;
  164. int dma_64bit_address;
  165. dma_addr_t sg_dma;
  166. void *sg_cpu;
  167. const struct dw_mci_dma_ops *dma_ops;
  168. /* For idmac */
  169. unsigned int ring_size;
  170. /* For edmac */
  171. struct dw_mci_dma_slave *dms;
  172. /* Registers's physical base address */
  173. resource_size_t phy_regs;
  174. u32 cmd_status;
  175. u32 data_status;
  176. u32 stop_cmdr;
  177. u32 dir_status;
  178. struct tasklet_struct tasklet;
  179. unsigned long pending_events;
  180. unsigned long completed_events;
  181. enum dw_mci_state state;
  182. struct list_head queue;
  183. u32 bus_hz;
  184. u32 current_speed;
  185. u32 fifoth_val;
  186. u16 verid;
  187. struct device *dev;
  188. struct dw_mci_board *pdata;
  189. const struct dw_mci_drv_data *drv_data;
  190. void *priv;
  191. struct clk *biu_clk;
  192. struct clk *ciu_clk;
  193. struct dw_mci_slot *slot;
  194. /* FIFO push and pull */
  195. int fifo_depth;
  196. int data_shift;
  197. u8 part_buf_start;
  198. u8 part_buf_count;
  199. union {
  200. u16 part_buf16;
  201. u32 part_buf32;
  202. u64 part_buf;
  203. };
  204. void (*push_data)(struct dw_mci *host, void *buf, int cnt);
  205. void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
  206. bool vqmmc_enabled;
  207. unsigned long irq_flags; /* IRQ flags */
  208. int irq;
  209. int sdio_id0;
  210. struct timer_list cmd11_timer;
  211. struct timer_list cto_timer;
  212. struct timer_list dto_timer;
  213. };
  214. /* DMA ops for Internal/External DMAC interface */
  215. struct dw_mci_dma_ops {
  216. /* DMA Ops */
  217. int (*init)(struct dw_mci *host);
  218. int (*start)(struct dw_mci *host, unsigned int sg_len);
  219. void (*complete)(void *host);
  220. void (*stop)(struct dw_mci *host);
  221. void (*cleanup)(struct dw_mci *host);
  222. void (*exit)(struct dw_mci *host);
  223. };
  224. struct dma_pdata;
  225. /* Board platform data */
  226. struct dw_mci_board {
  227. unsigned int bus_hz; /* Clock speed at the cclk_in pad */
  228. u32 caps; /* Capabilities */
  229. u32 caps2; /* More capabilities */
  230. u32 pm_caps; /* PM capabilities */
  231. /*
  232. * Override fifo depth. If 0, autodetect it from the FIFOTH register,
  233. * but note that this may not be reliable after a bootloader has used
  234. * it.
  235. */
  236. unsigned int fifo_depth;
  237. /* delay in mS before detecting cards after interrupt */
  238. u32 detect_delay_ms;
  239. struct reset_control *rstc;
  240. struct dw_mci_dma_ops *dma_ops;
  241. struct dma_pdata *data;
  242. };
  243. #define DW_MMC_240A 0x240a
  244. #define DW_MMC_280A 0x280a
  245. #define SDMMC_CTRL 0x000
  246. #define SDMMC_PWREN 0x004
  247. #define SDMMC_CLKDIV 0x008
  248. #define SDMMC_CLKSRC 0x00c
  249. #define SDMMC_CLKENA 0x010
  250. #define SDMMC_TMOUT 0x014
  251. #define SDMMC_CTYPE 0x018
  252. #define SDMMC_BLKSIZ 0x01c
  253. #define SDMMC_BYTCNT 0x020
  254. #define SDMMC_INTMASK 0x024
  255. #define SDMMC_CMDARG 0x028
  256. #define SDMMC_CMD 0x02c
  257. #define SDMMC_RESP0 0x030
  258. #define SDMMC_RESP1 0x034
  259. #define SDMMC_RESP2 0x038
  260. #define SDMMC_RESP3 0x03c
  261. #define SDMMC_MINTSTS 0x040
  262. #define SDMMC_RINTSTS 0x044
  263. #define SDMMC_STATUS 0x048
  264. #define SDMMC_FIFOTH 0x04c
  265. #define SDMMC_CDETECT 0x050
  266. #define SDMMC_WRTPRT 0x054
  267. #define SDMMC_GPIO 0x058
  268. #define SDMMC_TCBCNT 0x05c
  269. #define SDMMC_TBBCNT 0x060
  270. #define SDMMC_DEBNCE 0x064
  271. #define SDMMC_USRID 0x068
  272. #define SDMMC_VERID 0x06c
  273. #define SDMMC_HCON 0x070
  274. #define SDMMC_UHS_REG 0x074
  275. #define SDMMC_RST_N 0x078
  276. #define SDMMC_BMOD 0x080
  277. #define SDMMC_PLDMND 0x084
  278. #define SDMMC_DBADDR 0x088
  279. #define SDMMC_IDSTS 0x08c
  280. #define SDMMC_IDINTEN 0x090
  281. #define SDMMC_DSCADDR 0x094
  282. #define SDMMC_BUFADDR 0x098
  283. #define SDMMC_CDTHRCTL 0x100
  284. #define SDMMC_UHS_REG_EXT 0x108
  285. #define SDMMC_DDR_REG 0x10c
  286. #define SDMMC_ENABLE_SHIFT 0x110
  287. #define SDMMC_DATA(x) (x)
  288. /*
  289. * Registers to support idmac 64-bit address mode
  290. */
  291. #define SDMMC_DBADDRL 0x088
  292. #define SDMMC_DBADDRU 0x08c
  293. #define SDMMC_IDSTS64 0x090
  294. #define SDMMC_IDINTEN64 0x094
  295. #define SDMMC_DSCADDRL 0x098
  296. #define SDMMC_DSCADDRU 0x09c
  297. #define SDMMC_BUFADDRL 0x0A0
  298. #define SDMMC_BUFADDRU 0x0A4
  299. /*
  300. * Data offset is difference according to Version
  301. * Lower than 2.40a : data register offest is 0x100
  302. */
  303. #define DATA_OFFSET 0x100
  304. #define DATA_240A_OFFSET 0x200
  305. /* shift bit field */
  306. #define _SBF(f, v) ((v) << (f))
  307. /* Control register defines */
  308. #define SDMMC_CTRL_USE_IDMAC BIT(25)
  309. #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
  310. #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
  311. #define SDMMC_CTRL_SEND_CCSD BIT(9)
  312. #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
  313. #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
  314. #define SDMMC_CTRL_READ_WAIT BIT(6)
  315. #define SDMMC_CTRL_DMA_ENABLE BIT(5)
  316. #define SDMMC_CTRL_INT_ENABLE BIT(4)
  317. #define SDMMC_CTRL_DMA_RESET BIT(2)
  318. #define SDMMC_CTRL_FIFO_RESET BIT(1)
  319. #define SDMMC_CTRL_RESET BIT(0)
  320. /* Clock Enable register defines */
  321. #define SDMMC_CLKEN_LOW_PWR BIT(16)
  322. #define SDMMC_CLKEN_ENABLE BIT(0)
  323. /* time-out register defines */
  324. #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
  325. #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
  326. #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
  327. #define SDMMC_TMOUT_RESP_MSK 0xFF
  328. /* card-type register defines */
  329. #define SDMMC_CTYPE_8BIT BIT(16)
  330. #define SDMMC_CTYPE_4BIT BIT(0)
  331. #define SDMMC_CTYPE_1BIT 0
  332. /* Interrupt status & mask register defines */
  333. #define SDMMC_INT_SDIO(n) BIT(16 + (n))
  334. #define SDMMC_INT_EBE BIT(15)
  335. #define SDMMC_INT_ACD BIT(14)
  336. #define SDMMC_INT_SBE BIT(13)
  337. #define SDMMC_INT_HLE BIT(12)
  338. #define SDMMC_INT_FRUN BIT(11)
  339. #define SDMMC_INT_HTO BIT(10)
  340. #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
  341. #define SDMMC_INT_DRTO BIT(9)
  342. #define SDMMC_INT_RTO BIT(8)
  343. #define SDMMC_INT_DCRC BIT(7)
  344. #define SDMMC_INT_RCRC BIT(6)
  345. #define SDMMC_INT_RXDR BIT(5)
  346. #define SDMMC_INT_TXDR BIT(4)
  347. #define SDMMC_INT_DATA_OVER BIT(3)
  348. #define SDMMC_INT_CMD_DONE BIT(2)
  349. #define SDMMC_INT_RESP_ERR BIT(1)
  350. #define SDMMC_INT_CD BIT(0)
  351. #define SDMMC_INT_ERROR 0xbfc2
  352. /* Command register defines */
  353. #define SDMMC_CMD_START BIT(31)
  354. #define SDMMC_CMD_USE_HOLD_REG BIT(29)
  355. #define SDMMC_CMD_VOLT_SWITCH BIT(28)
  356. #define SDMMC_CMD_CCS_EXP BIT(23)
  357. #define SDMMC_CMD_CEATA_RD BIT(22)
  358. #define SDMMC_CMD_UPD_CLK BIT(21)
  359. #define SDMMC_CMD_INIT BIT(15)
  360. #define SDMMC_CMD_STOP BIT(14)
  361. #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
  362. #define SDMMC_CMD_SEND_STOP BIT(12)
  363. #define SDMMC_CMD_STRM_MODE BIT(11)
  364. #define SDMMC_CMD_DAT_WR BIT(10)
  365. #define SDMMC_CMD_DAT_EXP BIT(9)
  366. #define SDMMC_CMD_RESP_CRC BIT(8)
  367. #define SDMMC_CMD_RESP_LONG BIT(7)
  368. #define SDMMC_CMD_RESP_EXP BIT(6)
  369. #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
  370. /* Status register defines */
  371. #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
  372. #define SDMMC_STATUS_DMA_REQ BIT(31)
  373. #define SDMMC_STATUS_BUSY BIT(9)
  374. /* FIFOTH register defines */
  375. #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
  376. ((r) & 0xFFF) << 16 | \
  377. ((t) & 0xFFF))
  378. /* HCON register defines */
  379. #define DMA_INTERFACE_IDMA (0x0)
  380. #define DMA_INTERFACE_DWDMA (0x1)
  381. #define DMA_INTERFACE_GDMA (0x2)
  382. #define DMA_INTERFACE_NODMA (0x3)
  383. #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
  384. #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
  385. #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
  386. #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
  387. /* Internal DMAC interrupt defines */
  388. #define SDMMC_IDMAC_INT_AI BIT(9)
  389. #define SDMMC_IDMAC_INT_NI BIT(8)
  390. #define SDMMC_IDMAC_INT_CES BIT(5)
  391. #define SDMMC_IDMAC_INT_DU BIT(4)
  392. #define SDMMC_IDMAC_INT_FBE BIT(2)
  393. #define SDMMC_IDMAC_INT_RI BIT(1)
  394. #define SDMMC_IDMAC_INT_TI BIT(0)
  395. /* Internal DMAC bus mode bits */
  396. #define SDMMC_IDMAC_ENABLE BIT(7)
  397. #define SDMMC_IDMAC_FB BIT(1)
  398. #define SDMMC_IDMAC_SWRESET BIT(0)
  399. /* H/W reset */
  400. #define SDMMC_RST_HWACTIVE 0x1
  401. /* Version ID register define */
  402. #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
  403. /* Card read threshold */
  404. #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
  405. #define SDMMC_CARD_WR_THR_EN BIT(2)
  406. #define SDMMC_CARD_RD_THR_EN BIT(0)
  407. /* UHS-1 register defines */
  408. #define SDMMC_UHS_DDR BIT(16)
  409. #define SDMMC_UHS_18V BIT(0)
  410. /* DDR register defines */
  411. #define SDMMC_DDR_HS400 BIT(31)
  412. /* Enable shift register defines */
  413. #define SDMMC_ENABLE_PHASE BIT(0)
  414. /* All ctrl reset bits */
  415. #define SDMMC_CTRL_ALL_RESET_FLAGS \
  416. (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
  417. /* FIFO register access macros. These should not change the data endian-ness
  418. * as they are written to memory to be dealt with by the upper layers
  419. */
  420. #define mci_fifo_readw(__reg) __raw_readw(__reg)
  421. #define mci_fifo_readl(__reg) __raw_readl(__reg)
  422. #define mci_fifo_readq(__reg) __raw_readq(__reg)
  423. #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
  424. #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
  425. #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
  426. /* Register access macros */
  427. #define mci_readl(dev, reg) \
  428. readl_relaxed((dev)->regs + SDMMC_##reg)
  429. #define mci_writel(dev, reg, value) \
  430. writel_relaxed((value), (dev)->regs + SDMMC_##reg)
  431. /* 16-bit FIFO access macros */
  432. #define mci_readw(dev, reg) \
  433. readw_relaxed((dev)->regs + SDMMC_##reg)
  434. #define mci_writew(dev, reg, value) \
  435. writew_relaxed((value), (dev)->regs + SDMMC_##reg)
  436. /* 64-bit FIFO access macros */
  437. #ifdef readq
  438. #define mci_readq(dev, reg) \
  439. readq_relaxed((dev)->regs + SDMMC_##reg)
  440. #define mci_writeq(dev, reg, value) \
  441. writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
  442. #else
  443. /*
  444. * Dummy readq implementation for architectures that don't define it.
  445. *
  446. * We would assume that none of these architectures would configure
  447. * the IP block with a 64bit FIFO width, so this code will never be
  448. * executed on those machines. Defining these macros here keeps the
  449. * rest of the code free from ifdefs.
  450. */
  451. #define mci_readq(dev, reg) \
  452. (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
  453. #define mci_writeq(dev, reg, value) \
  454. (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
  455. #define __raw_writeq(__value, __reg) \
  456. (*(volatile u64 __force *)(__reg) = (__value))
  457. #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
  458. #endif
  459. extern int dw_mci_probe(struct dw_mci *host);
  460. extern void dw_mci_remove(struct dw_mci *host);
  461. #ifdef CONFIG_PM
  462. extern int dw_mci_runtime_suspend(struct device *device);
  463. extern int dw_mci_runtime_resume(struct device *device);
  464. #endif
  465. /**
  466. * struct dw_mci_slot - MMC slot state
  467. * @mmc: The mmc_host representing this slot.
  468. * @host: The MMC controller this slot is using.
  469. * @ctype: Card type for this slot.
  470. * @mrq: mmc_request currently being processed or waiting to be
  471. * processed, or NULL when the slot is idle.
  472. * @queue_node: List node for placing this node in the @queue list of
  473. * &struct dw_mci.
  474. * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  475. * @__clk_old: The last clock value that was requested from core.
  476. * Keeping track of this helps us to avoid spamming the console.
  477. * @flags: Random state bits associated with the slot.
  478. * @id: Number of this slot.
  479. * @sdio_id: Number of this slot in the SDIO interrupt registers.
  480. */
  481. struct dw_mci_slot {
  482. struct mmc_host *mmc;
  483. struct dw_mci *host;
  484. u32 ctype;
  485. struct mmc_request *mrq;
  486. struct list_head queue_node;
  487. unsigned int clock;
  488. unsigned int __clk_old;
  489. unsigned long flags;
  490. #define DW_MMC_CARD_PRESENT 0
  491. #define DW_MMC_CARD_NEED_INIT 1
  492. #define DW_MMC_CARD_NO_LOW_PWR 2
  493. #define DW_MMC_CARD_NO_USE_HOLD 3
  494. #define DW_MMC_CARD_NEEDS_POLL 4
  495. int id;
  496. int sdio_id;
  497. };
  498. /**
  499. * dw_mci driver data - dw-mshc implementation specific driver data.
  500. * @caps: mmc subsystem specified capabilities of the controller(s).
  501. * @num_caps: number of capabilities specified by @caps.
  502. * @init: early implementation specific initialization.
  503. * @set_ios: handle bus specific extensions.
  504. * @parse_dt: parse implementation specific device tree properties.
  505. * @execute_tuning: implementation specific tuning procedure.
  506. *
  507. * Provide controller implementation specific extensions. The usage of this
  508. * data structure is fully optional and usage of each member in this structure
  509. * is optional as well.
  510. */
  511. struct dw_mci_drv_data {
  512. unsigned long *caps;
  513. u32 num_caps;
  514. int (*init)(struct dw_mci *host);
  515. void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
  516. int (*parse_dt)(struct dw_mci *host);
  517. int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
  518. int (*prepare_hs400_tuning)(struct dw_mci *host,
  519. struct mmc_ios *ios);
  520. int (*switch_voltage)(struct mmc_host *mmc,
  521. struct mmc_ios *ios);
  522. };
  523. #endif /* _DW_MMC_H_ */