dw_mmc-hi3798cv200.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/mfd/syscon.h>
  7. #include <linux/mmc/host.h>
  8. #include <linux/module.h>
  9. #include <linux/of_address.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/regmap.h>
  13. #include <linux/regulator/consumer.h>
  14. #include "dw_mmc.h"
  15. #include "dw_mmc-pltfm.h"
  16. #define ALL_INT_CLR 0x1ffff
  17. struct hi3798cv200_priv {
  18. struct clk *sample_clk;
  19. struct clk *drive_clk;
  20. };
  21. static unsigned long dw_mci_hi3798cv200_caps[] = {
  22. MMC_CAP_CMD23,
  23. MMC_CAP_CMD23,
  24. MMC_CAP_CMD23
  25. };
  26. static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  27. {
  28. struct hi3798cv200_priv *priv = host->priv;
  29. u32 val;
  30. val = mci_readl(host, UHS_REG);
  31. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  32. ios->timing == MMC_TIMING_UHS_DDR50)
  33. val |= SDMMC_UHS_DDR;
  34. else
  35. val &= ~SDMMC_UHS_DDR;
  36. mci_writel(host, UHS_REG, val);
  37. val = mci_readl(host, ENABLE_SHIFT);
  38. if (ios->timing == MMC_TIMING_MMC_DDR52)
  39. val |= SDMMC_ENABLE_PHASE;
  40. else
  41. val &= ~SDMMC_ENABLE_PHASE;
  42. mci_writel(host, ENABLE_SHIFT, val);
  43. val = mci_readl(host, DDR_REG);
  44. if (ios->timing == MMC_TIMING_MMC_HS400)
  45. val |= SDMMC_DDR_HS400;
  46. else
  47. val &= ~SDMMC_DDR_HS400;
  48. mci_writel(host, DDR_REG, val);
  49. if (ios->timing == MMC_TIMING_MMC_HS ||
  50. ios->timing == MMC_TIMING_LEGACY)
  51. clk_set_phase(priv->drive_clk, 180);
  52. else if (ios->timing == MMC_TIMING_MMC_HS200)
  53. clk_set_phase(priv->drive_clk, 135);
  54. }
  55. static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
  56. u32 opcode)
  57. {
  58. static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
  59. struct dw_mci *host = slot->host;
  60. struct hi3798cv200_priv *priv = host->priv;
  61. int raise_point = -1, fall_point = -1;
  62. int err, prev_err = -1;
  63. int found = 0;
  64. int i;
  65. for (i = 0; i < ARRAY_SIZE(degrees); i++) {
  66. clk_set_phase(priv->sample_clk, degrees[i]);
  67. mci_writel(host, RINTSTS, ALL_INT_CLR);
  68. err = mmc_send_tuning(slot->mmc, opcode, NULL);
  69. if (!err)
  70. found = 1;
  71. if (i > 0) {
  72. if (err && !prev_err)
  73. fall_point = i - 1;
  74. if (!err && prev_err)
  75. raise_point = i;
  76. }
  77. if (raise_point != -1 && fall_point != -1)
  78. goto tuning_out;
  79. prev_err = err;
  80. err = 0;
  81. }
  82. tuning_out:
  83. if (found) {
  84. if (raise_point == -1)
  85. raise_point = 0;
  86. if (fall_point == -1)
  87. fall_point = ARRAY_SIZE(degrees) - 1;
  88. if (fall_point < raise_point) {
  89. if ((raise_point + fall_point) >
  90. (ARRAY_SIZE(degrees) - 1))
  91. i = fall_point / 2;
  92. else
  93. i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;
  94. } else {
  95. i = (raise_point + fall_point) / 2;
  96. }
  97. clk_set_phase(priv->sample_clk, degrees[i]);
  98. dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",
  99. raise_point, fall_point, degrees[i]);
  100. } else {
  101. dev_err(host->dev, "No valid clk_sample shift! use default\n");
  102. err = -EINVAL;
  103. }
  104. mci_writel(host, RINTSTS, ALL_INT_CLR);
  105. return err;
  106. }
  107. static int dw_mci_hi3798cv200_init(struct dw_mci *host)
  108. {
  109. struct hi3798cv200_priv *priv;
  110. int ret;
  111. priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  112. if (!priv)
  113. return -ENOMEM;
  114. priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
  115. if (IS_ERR(priv->sample_clk)) {
  116. dev_err(host->dev, "failed to get ciu-sample clock\n");
  117. return PTR_ERR(priv->sample_clk);
  118. }
  119. priv->drive_clk = devm_clk_get(host->dev, "ciu-drive");
  120. if (IS_ERR(priv->drive_clk)) {
  121. dev_err(host->dev, "failed to get ciu-drive clock\n");
  122. return PTR_ERR(priv->drive_clk);
  123. }
  124. ret = clk_prepare_enable(priv->sample_clk);
  125. if (ret) {
  126. dev_err(host->dev, "failed to enable ciu-sample clock\n");
  127. return ret;
  128. }
  129. ret = clk_prepare_enable(priv->drive_clk);
  130. if (ret) {
  131. dev_err(host->dev, "failed to enable ciu-drive clock\n");
  132. goto disable_sample_clk;
  133. }
  134. host->priv = priv;
  135. return 0;
  136. disable_sample_clk:
  137. clk_disable_unprepare(priv->sample_clk);
  138. return ret;
  139. }
  140. static const struct dw_mci_drv_data hi3798cv200_data = {
  141. .caps = dw_mci_hi3798cv200_caps,
  142. .num_caps = ARRAY_SIZE(dw_mci_hi3798cv200_caps),
  143. .init = dw_mci_hi3798cv200_init,
  144. .set_ios = dw_mci_hi3798cv200_set_ios,
  145. .execute_tuning = dw_mci_hi3798cv200_execute_tuning,
  146. };
  147. static int dw_mci_hi3798cv200_probe(struct platform_device *pdev)
  148. {
  149. return dw_mci_pltfm_register(pdev, &hi3798cv200_data);
  150. }
  151. static int dw_mci_hi3798cv200_remove(struct platform_device *pdev)
  152. {
  153. struct dw_mci *host = platform_get_drvdata(pdev);
  154. struct hi3798cv200_priv *priv = host->priv;
  155. clk_disable_unprepare(priv->drive_clk);
  156. clk_disable_unprepare(priv->sample_clk);
  157. return dw_mci_pltfm_remove(pdev);
  158. }
  159. static const struct of_device_id dw_mci_hi3798cv200_match[] = {
  160. { .compatible = "hisilicon,hi3798cv200-dw-mshc", },
  161. {},
  162. };
  163. MODULE_DEVICE_TABLE(of, dw_mci_hi3798cv200_match);
  164. static struct platform_driver dw_mci_hi3798cv200_driver = {
  165. .probe = dw_mci_hi3798cv200_probe,
  166. .remove = dw_mci_hi3798cv200_remove,
  167. .driver = {
  168. .name = "dwmmc_hi3798cv200",
  169. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  170. .of_match_table = dw_mci_hi3798cv200_match,
  171. },
  172. };
  173. module_platform_driver(dw_mci_hi3798cv200_driver);
  174. MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension");
  175. MODULE_LICENSE("GPL v2");
  176. MODULE_ALIAS("platform:dwmmc_hi3798cv200");