android-goldfish.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2007, Google Inc.
  4. * Copyright 2012, Intel Inc.
  5. *
  6. * based on omap.c driver, which was
  7. * Copyright (C) 2004 Nokia Corporation
  8. * Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
  9. * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
  10. * Other hacks (DMA, SD, etc) by David Brownell
  11. */
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/major.h>
  15. #include <linux/types.h>
  16. #include <linux/pci.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/kernel.h>
  19. #include <linux/fs.h>
  20. #include <linux/errno.h>
  21. #include <linux/hdreg.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/mutex.h>
  25. #include <linux/scatterlist.h>
  26. #include <linux/mmc/mmc.h>
  27. #include <linux/mmc/host.h>
  28. #include <linux/mmc/card.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/init.h>
  31. #include <linux/ioport.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/delay.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/timer.h>
  36. #include <linux/clk.h>
  37. #include <asm/io.h>
  38. #include <asm/irq.h>
  39. #include <asm/types.h>
  40. #include <linux/uaccess.h>
  41. #define DRIVER_NAME "goldfish_mmc"
  42. #define BUFFER_SIZE 16384
  43. #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
  44. #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
  45. enum {
  46. /* status register */
  47. MMC_INT_STATUS = 0x00,
  48. /* set this to enable IRQ */
  49. MMC_INT_ENABLE = 0x04,
  50. /* set this to specify buffer address */
  51. MMC_SET_BUFFER = 0x08,
  52. /* MMC command number */
  53. MMC_CMD = 0x0C,
  54. /* MMC argument */
  55. MMC_ARG = 0x10,
  56. /* MMC response (or R2 bits 0 - 31) */
  57. MMC_RESP_0 = 0x14,
  58. /* MMC R2 response bits 32 - 63 */
  59. MMC_RESP_1 = 0x18,
  60. /* MMC R2 response bits 64 - 95 */
  61. MMC_RESP_2 = 0x1C,
  62. /* MMC R2 response bits 96 - 127 */
  63. MMC_RESP_3 = 0x20,
  64. MMC_BLOCK_LENGTH = 0x24,
  65. MMC_BLOCK_COUNT = 0x28,
  66. /* MMC state flags */
  67. MMC_STATE = 0x2C,
  68. /* MMC_INT_STATUS bits */
  69. MMC_STAT_END_OF_CMD = 1U << 0,
  70. MMC_STAT_END_OF_DATA = 1U << 1,
  71. MMC_STAT_STATE_CHANGE = 1U << 2,
  72. MMC_STAT_CMD_TIMEOUT = 1U << 3,
  73. /* MMC_STATE bits */
  74. MMC_STATE_INSERTED = 1U << 0,
  75. MMC_STATE_READ_ONLY = 1U << 1,
  76. };
  77. /*
  78. * Command types
  79. */
  80. #define OMAP_MMC_CMDTYPE_BC 0
  81. #define OMAP_MMC_CMDTYPE_BCR 1
  82. #define OMAP_MMC_CMDTYPE_AC 2
  83. #define OMAP_MMC_CMDTYPE_ADTC 3
  84. struct goldfish_mmc_host {
  85. struct mmc_request *mrq;
  86. struct mmc_command *cmd;
  87. struct mmc_data *data;
  88. struct device *dev;
  89. unsigned char id; /* 16xx chips have 2 MMC blocks */
  90. void *virt_base;
  91. unsigned int phys_base;
  92. int irq;
  93. unsigned char bus_mode;
  94. unsigned char hw_bus_mode;
  95. unsigned int sg_len;
  96. unsigned dma_done:1;
  97. unsigned dma_in_use:1;
  98. void __iomem *reg_base;
  99. };
  100. static inline int
  101. goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
  102. {
  103. return 0;
  104. }
  105. static ssize_t
  106. goldfish_mmc_show_cover_switch(struct device *dev,
  107. struct device_attribute *attr, char *buf)
  108. {
  109. struct goldfish_mmc_host *host = dev_get_drvdata(dev);
  110. return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
  111. "closed");
  112. }
  113. static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
  114. static void
  115. goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
  116. {
  117. u32 cmdreg;
  118. u32 resptype;
  119. u32 cmdtype;
  120. host->cmd = cmd;
  121. resptype = 0;
  122. cmdtype = 0;
  123. /* Our hardware needs to know exact type */
  124. switch (mmc_resp_type(cmd)) {
  125. case MMC_RSP_NONE:
  126. break;
  127. case MMC_RSP_R1:
  128. case MMC_RSP_R1B:
  129. /* resp 1, 1b, 6, 7 */
  130. resptype = 1;
  131. break;
  132. case MMC_RSP_R2:
  133. resptype = 2;
  134. break;
  135. case MMC_RSP_R3:
  136. resptype = 3;
  137. break;
  138. default:
  139. dev_err(mmc_dev(mmc_from_priv(host)),
  140. "Invalid response type: %04x\n", mmc_resp_type(cmd));
  141. break;
  142. }
  143. if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
  144. cmdtype = OMAP_MMC_CMDTYPE_ADTC;
  145. else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
  146. cmdtype = OMAP_MMC_CMDTYPE_BC;
  147. else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
  148. cmdtype = OMAP_MMC_CMDTYPE_BCR;
  149. else
  150. cmdtype = OMAP_MMC_CMDTYPE_AC;
  151. cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
  152. if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
  153. cmdreg |= 1 << 6;
  154. if (cmd->flags & MMC_RSP_BUSY)
  155. cmdreg |= 1 << 11;
  156. if (host->data && !(host->data->flags & MMC_DATA_WRITE))
  157. cmdreg |= 1 << 15;
  158. GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
  159. GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
  160. }
  161. static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
  162. struct mmc_data *data)
  163. {
  164. if (host->dma_in_use) {
  165. enum dma_data_direction dma_data_dir;
  166. dma_data_dir = mmc_get_dma_dir(data);
  167. if (dma_data_dir == DMA_FROM_DEVICE) {
  168. /*
  169. * We don't really have DMA, so we need
  170. * to copy from our platform driver buffer
  171. */
  172. sg_copy_from_buffer(data->sg, 1, host->virt_base,
  173. data->sg->length);
  174. }
  175. host->data->bytes_xfered += data->sg->length;
  176. dma_unmap_sg(mmc_dev(mmc_from_priv(host)), data->sg,
  177. host->sg_len, dma_data_dir);
  178. }
  179. host->data = NULL;
  180. host->sg_len = 0;
  181. /*
  182. * NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
  183. * dozens of requests until the card finishes writing data.
  184. * It'd be cheaper to just wait till an EOFB interrupt arrives...
  185. */
  186. if (!data->stop) {
  187. host->mrq = NULL;
  188. mmc_request_done(mmc_from_priv(host), data->mrq);
  189. return;
  190. }
  191. goldfish_mmc_start_command(host, data->stop);
  192. }
  193. static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
  194. struct mmc_data *data)
  195. {
  196. if (!host->dma_in_use) {
  197. goldfish_mmc_xfer_done(host, data);
  198. return;
  199. }
  200. if (host->dma_done)
  201. goldfish_mmc_xfer_done(host, data);
  202. }
  203. static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
  204. struct mmc_command *cmd)
  205. {
  206. host->cmd = NULL;
  207. if (cmd->flags & MMC_RSP_PRESENT) {
  208. if (cmd->flags & MMC_RSP_136) {
  209. /* response type 2 */
  210. cmd->resp[3] =
  211. GOLDFISH_MMC_READ(host, MMC_RESP_0);
  212. cmd->resp[2] =
  213. GOLDFISH_MMC_READ(host, MMC_RESP_1);
  214. cmd->resp[1] =
  215. GOLDFISH_MMC_READ(host, MMC_RESP_2);
  216. cmd->resp[0] =
  217. GOLDFISH_MMC_READ(host, MMC_RESP_3);
  218. } else {
  219. /* response types 1, 1b, 3, 4, 5, 6 */
  220. cmd->resp[0] =
  221. GOLDFISH_MMC_READ(host, MMC_RESP_0);
  222. }
  223. }
  224. if (host->data == NULL || cmd->error) {
  225. host->mrq = NULL;
  226. mmc_request_done(mmc_from_priv(host), cmd->mrq);
  227. }
  228. }
  229. static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
  230. {
  231. struct goldfish_mmc_host *host = (struct goldfish_mmc_host *)dev_id;
  232. u16 status;
  233. int end_command = 0;
  234. int end_transfer = 0;
  235. int state_changed = 0;
  236. int cmd_timeout = 0;
  237. while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
  238. GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
  239. if (status & MMC_STAT_END_OF_CMD)
  240. end_command = 1;
  241. if (status & MMC_STAT_END_OF_DATA)
  242. end_transfer = 1;
  243. if (status & MMC_STAT_STATE_CHANGE)
  244. state_changed = 1;
  245. if (status & MMC_STAT_CMD_TIMEOUT) {
  246. end_command = 0;
  247. cmd_timeout = 1;
  248. }
  249. }
  250. if (cmd_timeout) {
  251. struct mmc_request *mrq = host->mrq;
  252. mrq->cmd->error = -ETIMEDOUT;
  253. host->mrq = NULL;
  254. mmc_request_done(mmc_from_priv(host), mrq);
  255. }
  256. if (end_command)
  257. goldfish_mmc_cmd_done(host, host->cmd);
  258. if (end_transfer) {
  259. host->dma_done = 1;
  260. goldfish_mmc_end_of_data(host, host->data);
  261. } else if (host->data != NULL) {
  262. /*
  263. * WORKAROUND -- after porting this driver from 2.6 to 3.4,
  264. * during device initialization, cases where host->data is
  265. * non-null but end_transfer is false would occur. Doing
  266. * nothing in such cases results in no further interrupts,
  267. * and initialization failure.
  268. * TODO -- find the real cause.
  269. */
  270. host->dma_done = 1;
  271. goldfish_mmc_end_of_data(host, host->data);
  272. }
  273. if (state_changed) {
  274. u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
  275. pr_info("%s: Card detect now %d\n", __func__,
  276. (state & MMC_STATE_INSERTED));
  277. mmc_detect_change(mmc_from_priv(host), 0);
  278. }
  279. if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
  280. status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
  281. dev_info(mmc_dev(mmc_from_priv(host)), "spurious irq 0x%04x\n",
  282. status);
  283. if (status != 0) {
  284. GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
  285. GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
  286. }
  287. }
  288. return IRQ_HANDLED;
  289. }
  290. static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
  291. struct mmc_request *req)
  292. {
  293. struct mmc_data *data = req->data;
  294. int block_size;
  295. unsigned sg_len;
  296. enum dma_data_direction dma_data_dir;
  297. host->data = data;
  298. if (data == NULL) {
  299. GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
  300. GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
  301. host->dma_in_use = 0;
  302. return;
  303. }
  304. block_size = data->blksz;
  305. GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
  306. GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
  307. /*
  308. * Cope with calling layer confusion; it issues "single
  309. * block" writes using multi-block scatterlists.
  310. */
  311. sg_len = (data->blocks == 1) ? 1 : data->sg_len;
  312. dma_data_dir = mmc_get_dma_dir(data);
  313. host->sg_len = dma_map_sg(mmc_dev(mmc_from_priv(host)), data->sg,
  314. sg_len, dma_data_dir);
  315. host->dma_done = 0;
  316. host->dma_in_use = 1;
  317. if (dma_data_dir == DMA_TO_DEVICE) {
  318. /*
  319. * We don't really have DMA, so we need to copy to our
  320. * platform driver buffer
  321. */
  322. sg_copy_to_buffer(data->sg, 1, host->virt_base,
  323. data->sg->length);
  324. }
  325. }
  326. static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
  327. {
  328. struct goldfish_mmc_host *host = mmc_priv(mmc);
  329. WARN_ON(host->mrq != NULL);
  330. host->mrq = req;
  331. goldfish_mmc_prepare_data(host, req);
  332. goldfish_mmc_start_command(host, req->cmd);
  333. }
  334. static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  335. {
  336. struct goldfish_mmc_host *host = mmc_priv(mmc);
  337. host->bus_mode = ios->bus_mode;
  338. host->hw_bus_mode = host->bus_mode;
  339. }
  340. static int goldfish_mmc_get_ro(struct mmc_host *mmc)
  341. {
  342. uint32_t state;
  343. struct goldfish_mmc_host *host = mmc_priv(mmc);
  344. state = GOLDFISH_MMC_READ(host, MMC_STATE);
  345. return ((state & MMC_STATE_READ_ONLY) != 0);
  346. }
  347. static const struct mmc_host_ops goldfish_mmc_ops = {
  348. .request = goldfish_mmc_request,
  349. .set_ios = goldfish_mmc_set_ios,
  350. .get_ro = goldfish_mmc_get_ro,
  351. };
  352. static int goldfish_mmc_probe(struct platform_device *pdev)
  353. {
  354. struct mmc_host *mmc;
  355. struct goldfish_mmc_host *host = NULL;
  356. struct resource *res;
  357. int ret = 0;
  358. int irq;
  359. dma_addr_t buf_addr;
  360. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  361. irq = platform_get_irq(pdev, 0);
  362. if (res == NULL || irq < 0)
  363. return -ENXIO;
  364. mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
  365. if (mmc == NULL) {
  366. ret = -ENOMEM;
  367. goto err_alloc_host_failed;
  368. }
  369. host = mmc_priv(mmc);
  370. pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
  371. host->reg_base = ioremap(res->start, resource_size(res));
  372. if (host->reg_base == NULL) {
  373. ret = -ENOMEM;
  374. goto ioremap_failed;
  375. }
  376. host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
  377. &buf_addr, GFP_KERNEL);
  378. if (host->virt_base == 0) {
  379. ret = -ENOMEM;
  380. goto dma_alloc_failed;
  381. }
  382. host->phys_base = buf_addr;
  383. host->id = pdev->id;
  384. host->irq = irq;
  385. mmc->ops = &goldfish_mmc_ops;
  386. mmc->f_min = 400000;
  387. mmc->f_max = 24000000;
  388. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  389. mmc->caps = MMC_CAP_4_BIT_DATA;
  390. mmc->caps2 = MMC_CAP2_NO_SDIO;
  391. /* Use scatterlist DMA to reduce per-transfer costs.
  392. * NOTE max_seg_size assumption that small blocks aren't
  393. * normally used (except e.g. for reading SD registers).
  394. */
  395. mmc->max_segs = 32;
  396. mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
  397. mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
  398. mmc->max_req_size = BUFFER_SIZE;
  399. mmc->max_seg_size = mmc->max_req_size;
  400. ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
  401. if (ret) {
  402. dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
  403. goto err_request_irq_failed;
  404. }
  405. host->dev = &pdev->dev;
  406. platform_set_drvdata(pdev, host);
  407. ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
  408. if (ret)
  409. dev_warn(mmc_dev(mmc), "Unable to create sysfs attributes\n");
  410. GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
  411. GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
  412. MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA |
  413. MMC_STAT_STATE_CHANGE | MMC_STAT_CMD_TIMEOUT);
  414. mmc_add_host(mmc);
  415. return 0;
  416. err_request_irq_failed:
  417. dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
  418. host->phys_base);
  419. dma_alloc_failed:
  420. iounmap(host->reg_base);
  421. ioremap_failed:
  422. mmc_free_host(mmc);
  423. err_alloc_host_failed:
  424. return ret;
  425. }
  426. static int goldfish_mmc_remove(struct platform_device *pdev)
  427. {
  428. struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
  429. struct mmc_host *mmc = mmc_from_priv(host);
  430. BUG_ON(host == NULL);
  431. mmc_remove_host(mmc);
  432. free_irq(host->irq, host);
  433. dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
  434. iounmap(host->reg_base);
  435. mmc_free_host(mmc);
  436. return 0;
  437. }
  438. static struct platform_driver goldfish_mmc_driver = {
  439. .probe = goldfish_mmc_probe,
  440. .remove = goldfish_mmc_remove,
  441. .driver = {
  442. .name = DRIVER_NAME,
  443. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  444. },
  445. };
  446. module_platform_driver(goldfish_mmc_driver);
  447. MODULE_LICENSE("GPL v2");