config.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930
  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright 2017 IBM Corp.
  3. #include <linux/pci.h>
  4. #include <asm/pnv-ocxl.h>
  5. #include <misc/ocxl-config.h>
  6. #include "ocxl_internal.h"
  7. #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
  8. #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
  9. #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
  10. #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
  11. #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
  12. #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
  13. #define OCXL_DVSEC_TEMPL_VERSION 0x0
  14. #define OCXL_DVSEC_TEMPL_NAME 0x4
  15. #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
  16. #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
  17. #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
  18. #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
  19. #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
  20. #define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
  21. #define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
  22. #define OCXL_DVSEC_TEMPL_WWID 0x48
  23. #define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
  24. #define OCXL_MAX_AFU_PER_FUNCTION 64
  25. #define OCXL_TEMPL_LEN_1_0 0x58
  26. #define OCXL_TEMPL_LEN_1_1 0x60
  27. #define OCXL_TEMPL_NAME_LEN 24
  28. #define OCXL_CFG_TIMEOUT 3
  29. static int find_dvsec(struct pci_dev *dev, int dvsec_id)
  30. {
  31. int vsec = 0;
  32. u16 vendor, id;
  33. while ((vsec = pci_find_next_ext_capability(dev, vsec,
  34. OCXL_EXT_CAP_ID_DVSEC))) {
  35. pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
  36. &vendor);
  37. pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
  38. if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
  39. return vsec;
  40. }
  41. return 0;
  42. }
  43. static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
  44. {
  45. int vsec = 0;
  46. u16 vendor, id;
  47. u8 idx;
  48. while ((vsec = pci_find_next_ext_capability(dev, vsec,
  49. OCXL_EXT_CAP_ID_DVSEC))) {
  50. pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
  51. &vendor);
  52. pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
  53. if (vendor == PCI_VENDOR_ID_IBM &&
  54. id == OCXL_DVSEC_AFU_CTRL_ID) {
  55. pci_read_config_byte(dev,
  56. vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
  57. &idx);
  58. if (idx == afu_idx)
  59. return vsec;
  60. }
  61. }
  62. return 0;
  63. }
  64. /**
  65. * get_function_0() - Find a related PCI device (function 0)
  66. * @device: PCI device to match
  67. *
  68. * Returns a pointer to the related device, or null if not found
  69. */
  70. static struct pci_dev *get_function_0(struct pci_dev *dev)
  71. {
  72. unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
  73. return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
  74. dev->bus->number, devfn);
  75. }
  76. static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
  77. {
  78. u16 val;
  79. int pos;
  80. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
  81. if (!pos) {
  82. /*
  83. * PASID capability is not mandatory, but there
  84. * shouldn't be any AFU
  85. */
  86. dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
  87. fn->max_pasid_log = -1;
  88. goto out;
  89. }
  90. pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
  91. fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
  92. out:
  93. dev_dbg(&dev->dev, "PASID capability:\n");
  94. dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
  95. }
  96. static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
  97. {
  98. int pos;
  99. pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
  100. if (!pos && PCI_FUNC(dev->devfn) == 0) {
  101. dev_err(&dev->dev, "Can't find TL DVSEC\n");
  102. return -ENODEV;
  103. }
  104. if (pos && PCI_FUNC(dev->devfn) != 0) {
  105. dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
  106. return -ENODEV;
  107. }
  108. fn->dvsec_tl_pos = pos;
  109. return 0;
  110. }
  111. static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
  112. {
  113. int pos, afu_present;
  114. u32 val;
  115. pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
  116. if (!pos) {
  117. dev_err(&dev->dev, "Can't find function DVSEC\n");
  118. return -ENODEV;
  119. }
  120. fn->dvsec_function_pos = pos;
  121. pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
  122. afu_present = EXTRACT_BIT(val, 31);
  123. if (!afu_present) {
  124. fn->max_afu_index = -1;
  125. dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
  126. goto out;
  127. }
  128. fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
  129. out:
  130. dev_dbg(&dev->dev, "Function DVSEC:\n");
  131. dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
  132. return 0;
  133. }
  134. static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
  135. {
  136. int pos;
  137. if (fn->max_afu_index < 0) {
  138. fn->dvsec_afu_info_pos = -1;
  139. return 0;
  140. }
  141. pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
  142. if (!pos) {
  143. dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
  144. return -ENODEV;
  145. }
  146. fn->dvsec_afu_info_pos = pos;
  147. return 0;
  148. }
  149. static int read_dvsec_vendor(struct pci_dev *dev)
  150. {
  151. int pos;
  152. u32 cfg, tlx, dlx, reset_reload;
  153. /*
  154. * vendor specific DVSEC, for IBM images only. Some older
  155. * images may not have it
  156. *
  157. * It's only used on function 0 to specify the version of some
  158. * logic blocks and to give access to special registers to
  159. * enable host-based flashing.
  160. */
  161. if (PCI_FUNC(dev->devfn) != 0)
  162. return 0;
  163. pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
  164. if (!pos)
  165. return 0;
  166. pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
  167. pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
  168. pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
  169. pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
  170. &reset_reload);
  171. dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
  172. dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
  173. dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
  174. dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
  175. dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
  176. return 0;
  177. }
  178. static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
  179. int *out_pos)
  180. {
  181. int pos;
  182. if (PCI_FUNC(dev->devfn) != 0) {
  183. dev = get_function_0(dev);
  184. if (!dev)
  185. return -1;
  186. }
  187. pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
  188. if (!pos)
  189. return -1;
  190. *dev0 = dev;
  191. *out_pos = pos;
  192. return 0;
  193. }
  194. int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
  195. {
  196. struct pci_dev *dev0;
  197. u32 reset_reload;
  198. int pos;
  199. if (get_dvsec_vendor0(dev, &dev0, &pos))
  200. return -1;
  201. pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
  202. &reset_reload);
  203. *val = !!(reset_reload & BIT(0));
  204. return 0;
  205. }
  206. int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
  207. {
  208. struct pci_dev *dev0;
  209. u32 reset_reload;
  210. int pos;
  211. if (get_dvsec_vendor0(dev, &dev0, &pos))
  212. return -1;
  213. pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
  214. &reset_reload);
  215. if (val)
  216. reset_reload |= BIT(0);
  217. else
  218. reset_reload &= ~BIT(0);
  219. pci_write_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
  220. reset_reload);
  221. return 0;
  222. }
  223. static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
  224. {
  225. if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
  226. dev_err(&dev->dev,
  227. "AFUs are defined but no PASIDs are requested\n");
  228. return -EINVAL;
  229. }
  230. if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
  231. dev_err(&dev->dev,
  232. "Max AFU index out of architectural limit (%d vs %d)\n",
  233. fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
  234. return -EINVAL;
  235. }
  236. return 0;
  237. }
  238. int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
  239. {
  240. int rc;
  241. read_pasid(dev, fn);
  242. rc = read_dvsec_tl(dev, fn);
  243. if (rc) {
  244. dev_err(&dev->dev,
  245. "Invalid Transaction Layer DVSEC configuration: %d\n",
  246. rc);
  247. return -ENODEV;
  248. }
  249. rc = read_dvsec_function(dev, fn);
  250. if (rc) {
  251. dev_err(&dev->dev,
  252. "Invalid Function DVSEC configuration: %d\n", rc);
  253. return -ENODEV;
  254. }
  255. rc = read_dvsec_afu_info(dev, fn);
  256. if (rc) {
  257. dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
  258. return -ENODEV;
  259. }
  260. rc = read_dvsec_vendor(dev);
  261. if (rc) {
  262. dev_err(&dev->dev,
  263. "Invalid vendor specific DVSEC configuration: %d\n",
  264. rc);
  265. return -ENODEV;
  266. }
  267. rc = validate_function(dev, fn);
  268. return rc;
  269. }
  270. EXPORT_SYMBOL_GPL(ocxl_config_read_function);
  271. static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
  272. int offset, u32 *data)
  273. {
  274. u32 val;
  275. unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
  276. int pos = fn->dvsec_afu_info_pos;
  277. /* Protect 'data valid' bit */
  278. if (EXTRACT_BIT(offset, 31)) {
  279. dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
  280. return -EINVAL;
  281. }
  282. pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
  283. pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
  284. while (!EXTRACT_BIT(val, 31)) {
  285. if (time_after_eq(jiffies, timeout)) {
  286. dev_err(&dev->dev,
  287. "Timeout while reading AFU info DVSEC (offset=%d)\n",
  288. offset);
  289. return -EBUSY;
  290. }
  291. cpu_relax();
  292. pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
  293. }
  294. pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
  295. return 0;
  296. }
  297. /**
  298. * read_template_version() - Read the template version from the AFU
  299. * @dev: the device for the AFU
  300. * @fn: the AFU offsets
  301. * @len: outputs the template length
  302. * @version: outputs the major<<8,minor version
  303. *
  304. * Returns 0 on success, negative on failure
  305. */
  306. static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
  307. u16 *len, u16 *version)
  308. {
  309. u32 val32;
  310. u8 major, minor;
  311. int rc;
  312. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
  313. if (rc)
  314. return rc;
  315. *len = EXTRACT_BITS(val32, 16, 31);
  316. major = EXTRACT_BITS(val32, 8, 15);
  317. minor = EXTRACT_BITS(val32, 0, 7);
  318. *version = (major << 8) + minor;
  319. return 0;
  320. }
  321. int ocxl_config_check_afu_index(struct pci_dev *dev,
  322. struct ocxl_fn_config *fn, int afu_idx)
  323. {
  324. int rc;
  325. u16 templ_version;
  326. u16 len, expected_len;
  327. pci_write_config_byte(dev,
  328. fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
  329. afu_idx);
  330. rc = read_template_version(dev, fn, &len, &templ_version);
  331. if (rc)
  332. return rc;
  333. /* AFU index map can have holes, in which case we read all 0's */
  334. if (!templ_version && !len)
  335. return 0;
  336. dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
  337. templ_version >> 8, templ_version & 0xFF);
  338. switch (templ_version) {
  339. case 0x0005: // v0.5 was used prior to the spec approval
  340. case 0x0100:
  341. expected_len = OCXL_TEMPL_LEN_1_0;
  342. break;
  343. case 0x0101:
  344. expected_len = OCXL_TEMPL_LEN_1_1;
  345. break;
  346. default:
  347. dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
  348. templ_version);
  349. expected_len = len;
  350. }
  351. if (len != expected_len)
  352. dev_warn(&dev->dev,
  353. "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
  354. len, expected_len, templ_version);
  355. return 1;
  356. }
  357. static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
  358. struct ocxl_afu_config *afu)
  359. {
  360. int i, rc;
  361. u32 val, *ptr;
  362. BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
  363. for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
  364. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
  365. if (rc)
  366. return rc;
  367. ptr = (u32 *) &afu->name[i];
  368. *ptr = le32_to_cpu((__force __le32) val);
  369. }
  370. afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
  371. return 0;
  372. }
  373. static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
  374. struct ocxl_afu_config *afu)
  375. {
  376. int rc;
  377. u32 val;
  378. /*
  379. * Global MMIO
  380. */
  381. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
  382. if (rc)
  383. return rc;
  384. afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
  385. afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
  386. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
  387. if (rc)
  388. return rc;
  389. afu->global_mmio_offset += (u64) val << 32;
  390. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
  391. if (rc)
  392. return rc;
  393. afu->global_mmio_size = val;
  394. /*
  395. * Per-process MMIO
  396. */
  397. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
  398. if (rc)
  399. return rc;
  400. afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
  401. afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
  402. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
  403. if (rc)
  404. return rc;
  405. afu->pp_mmio_offset += (u64) val << 32;
  406. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
  407. if (rc)
  408. return rc;
  409. afu->pp_mmio_stride = val;
  410. return 0;
  411. }
  412. static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
  413. {
  414. int pos;
  415. u8 val8;
  416. u16 val16;
  417. pos = find_dvsec_afu_ctrl(dev, afu->idx);
  418. if (!pos) {
  419. dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
  420. afu->idx);
  421. return -ENODEV;
  422. }
  423. afu->dvsec_afu_control_pos = pos;
  424. pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
  425. afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
  426. pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
  427. afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
  428. return 0;
  429. }
  430. static bool char_allowed(int c)
  431. {
  432. /*
  433. * Permitted Characters : Alphanumeric, hyphen, underscore, comma
  434. */
  435. if ((c >= 0x30 && c <= 0x39) /* digits */ ||
  436. (c >= 0x41 && c <= 0x5A) /* upper case */ ||
  437. (c >= 0x61 && c <= 0x7A) /* lower case */ ||
  438. c == 0 /* NULL */ ||
  439. c == 0x2D /* - */ ||
  440. c == 0x5F /* _ */ ||
  441. c == 0x2C /* , */)
  442. return true;
  443. return false;
  444. }
  445. static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
  446. {
  447. int i;
  448. if (!afu->name[0]) {
  449. dev_err(&dev->dev, "Empty AFU name\n");
  450. return -EINVAL;
  451. }
  452. for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
  453. if (!char_allowed(afu->name[i])) {
  454. dev_err(&dev->dev,
  455. "Invalid character in AFU name\n");
  456. return -EINVAL;
  457. }
  458. }
  459. if (afu->global_mmio_bar != 0 &&
  460. afu->global_mmio_bar != 2 &&
  461. afu->global_mmio_bar != 4) {
  462. dev_err(&dev->dev, "Invalid global MMIO bar number\n");
  463. return -EINVAL;
  464. }
  465. if (afu->pp_mmio_bar != 0 &&
  466. afu->pp_mmio_bar != 2 &&
  467. afu->pp_mmio_bar != 4) {
  468. dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
  469. return -EINVAL;
  470. }
  471. return 0;
  472. }
  473. /**
  474. * read_afu_lpc_memory_info() - Populate AFU metadata regarding LPC memory
  475. * @dev: the device for the AFU
  476. * @fn: the AFU offsets
  477. * @afu: the AFU struct to populate the LPC metadata into
  478. *
  479. * Returns 0 on success, negative on failure
  480. */
  481. static int read_afu_lpc_memory_info(struct pci_dev *dev,
  482. struct ocxl_fn_config *fn,
  483. struct ocxl_afu_config *afu)
  484. {
  485. int rc;
  486. u32 val32;
  487. u16 templ_version;
  488. u16 templ_len;
  489. u64 total_mem_size = 0;
  490. u64 lpc_mem_size = 0;
  491. afu->lpc_mem_offset = 0;
  492. afu->lpc_mem_size = 0;
  493. afu->special_purpose_mem_offset = 0;
  494. afu->special_purpose_mem_size = 0;
  495. /*
  496. * For AFUs following template v1.0, the LPC memory covers the
  497. * total memory. Its size is a power of 2.
  498. *
  499. * For AFUs with template >= v1.01, the total memory size is
  500. * still a power of 2, but it is split in 2 parts:
  501. * - the LPC memory, whose size can now be anything
  502. * - the remainder memory is a special purpose memory, whose
  503. * definition is AFU-dependent. It is not accessible through
  504. * the usual commands for LPC memory
  505. */
  506. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
  507. if (rc)
  508. return rc;
  509. val32 = EXTRACT_BITS(val32, 0, 7);
  510. if (!val32)
  511. return 0; /* No LPC memory */
  512. /*
  513. * The configuration space spec allows for a memory size of up
  514. * to 2^255 bytes.
  515. *
  516. * Current generation hardware uses 56-bit physical addresses,
  517. * but we won't be able to get near close to that, as we won't
  518. * have a hole big enough in the memory map. Let it pass in
  519. * the driver for now. We'll get an error from the firmware
  520. * when trying to configure something too big.
  521. */
  522. total_mem_size = 1ull << val32;
  523. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
  524. if (rc)
  525. return rc;
  526. afu->lpc_mem_offset = val32;
  527. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
  528. if (rc)
  529. return rc;
  530. afu->lpc_mem_offset |= (u64) val32 << 32;
  531. rc = read_template_version(dev, fn, &templ_len, &templ_version);
  532. if (rc)
  533. return rc;
  534. if (templ_version >= 0x0101) {
  535. rc = read_afu_info(dev, fn,
  536. OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
  537. if (rc)
  538. return rc;
  539. lpc_mem_size = val32;
  540. rc = read_afu_info(dev, fn,
  541. OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
  542. if (rc)
  543. return rc;
  544. lpc_mem_size |= (u64) val32 << 32;
  545. } else {
  546. lpc_mem_size = total_mem_size;
  547. }
  548. afu->lpc_mem_size = lpc_mem_size;
  549. if (lpc_mem_size < total_mem_size) {
  550. afu->special_purpose_mem_offset =
  551. afu->lpc_mem_offset + lpc_mem_size;
  552. afu->special_purpose_mem_size =
  553. total_mem_size - lpc_mem_size;
  554. }
  555. return 0;
  556. }
  557. int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
  558. struct ocxl_afu_config *afu, u8 afu_idx)
  559. {
  560. int rc;
  561. u32 val32;
  562. /*
  563. * First, we need to write the AFU idx for the AFU we want to
  564. * access.
  565. */
  566. WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
  567. afu->idx = afu_idx;
  568. pci_write_config_byte(dev,
  569. fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
  570. afu->idx);
  571. rc = read_afu_name(dev, fn, afu);
  572. if (rc)
  573. return rc;
  574. rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
  575. if (rc)
  576. return rc;
  577. afu->version_major = EXTRACT_BITS(val32, 24, 31);
  578. afu->version_minor = EXTRACT_BITS(val32, 16, 23);
  579. afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
  580. afu->afum_type = EXTRACT_BITS(val32, 12, 13);
  581. afu->profile = EXTRACT_BITS(val32, 0, 7);
  582. rc = read_afu_mmio(dev, fn, afu);
  583. if (rc)
  584. return rc;
  585. rc = read_afu_lpc_memory_info(dev, fn, afu);
  586. if (rc)
  587. return rc;
  588. rc = read_afu_control(dev, afu);
  589. if (rc)
  590. return rc;
  591. dev_dbg(&dev->dev, "AFU configuration:\n");
  592. dev_dbg(&dev->dev, " name = %s\n", afu->name);
  593. dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
  594. afu->version_minor);
  595. dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
  596. dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
  597. afu->global_mmio_offset);
  598. dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
  599. dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
  600. dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
  601. dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
  602. dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
  603. dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
  604. dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
  605. afu->special_purpose_mem_offset);
  606. dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
  607. afu->special_purpose_mem_size);
  608. dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
  609. afu->pasid_supported_log);
  610. dev_dbg(&dev->dev, " actag supported = %u\n",
  611. afu->actag_supported);
  612. rc = validate_afu(dev, afu);
  613. return rc;
  614. }
  615. EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
  616. int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
  617. u16 *supported)
  618. {
  619. int rc;
  620. /*
  621. * This is really a simple wrapper for the kernel API, to
  622. * avoid an external driver using ocxl as a library to call
  623. * platform-dependent code
  624. */
  625. rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
  626. if (rc) {
  627. dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
  628. return rc;
  629. }
  630. return 0;
  631. }
  632. EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
  633. void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
  634. int actag_count)
  635. {
  636. u16 val;
  637. val = actag_count & OCXL_DVSEC_ACTAG_MASK;
  638. pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
  639. val = actag_base & OCXL_DVSEC_ACTAG_MASK;
  640. pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
  641. }
  642. EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
  643. int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
  644. {
  645. return pnv_ocxl_get_pasid_count(dev, count);
  646. }
  647. void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
  648. u32 pasid_count_log)
  649. {
  650. u8 val8;
  651. u32 val32;
  652. val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
  653. pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
  654. pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
  655. &val32);
  656. val32 &= ~OCXL_DVSEC_PASID_MASK;
  657. val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
  658. pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
  659. val32);
  660. }
  661. EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
  662. void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
  663. {
  664. u8 val;
  665. pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
  666. if (enable)
  667. val |= 1;
  668. else
  669. val &= 0xFE;
  670. pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
  671. }
  672. EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
  673. int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
  674. {
  675. u32 val;
  676. __be32 *be32ptr;
  677. u8 timers;
  678. int i, rc;
  679. long recv_cap;
  680. char *recv_rate;
  681. /*
  682. * Skip on function != 0, as the TL can only be defined on 0
  683. */
  684. if (PCI_FUNC(dev->devfn) != 0)
  685. return 0;
  686. recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
  687. if (!recv_rate)
  688. return -ENOMEM;
  689. /*
  690. * The spec defines 64 templates for messages in the
  691. * Transaction Layer (TL).
  692. *
  693. * The host and device each support a subset, so we need to
  694. * configure the transmitters on each side to send only
  695. * templates the receiver understands, at a rate the receiver
  696. * can process. Per the spec, template 0 must be supported by
  697. * everybody. That's the template which has been used by the
  698. * host and device so far.
  699. *
  700. * The sending rate limit must be set before the template is
  701. * enabled.
  702. */
  703. /*
  704. * Device -> host
  705. */
  706. rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
  707. PNV_OCXL_TL_RATE_BUF_SIZE);
  708. if (rc)
  709. goto out;
  710. for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
  711. be32ptr = (__be32 *) &recv_rate[i];
  712. pci_write_config_dword(dev,
  713. tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
  714. be32_to_cpu(*be32ptr));
  715. }
  716. val = recv_cap >> 32;
  717. pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
  718. val = recv_cap & GENMASK(31, 0);
  719. pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
  720. /*
  721. * Host -> device
  722. */
  723. for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
  724. pci_read_config_dword(dev,
  725. tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
  726. &val);
  727. be32ptr = (__be32 *) &recv_rate[i];
  728. *be32ptr = cpu_to_be32(val);
  729. }
  730. pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
  731. recv_cap = (long) val << 32;
  732. pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
  733. recv_cap |= val;
  734. rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
  735. PNV_OCXL_TL_RATE_BUF_SIZE);
  736. if (rc)
  737. goto out;
  738. /*
  739. * Opencapi commands needing to be retried are classified per
  740. * the TL in 2 groups: short and long commands.
  741. *
  742. * The short back off timer it not used for now. It will be
  743. * for opencapi 4.0.
  744. *
  745. * The long back off timer is typically used when an AFU hits
  746. * a page fault but the NPU is already processing one. So the
  747. * AFU needs to wait before it can resubmit. Having a value
  748. * too low doesn't break anything, but can generate extra
  749. * traffic on the link.
  750. * We set it to 1.6 us for now. It's shorter than, but in the
  751. * same order of magnitude as the time spent to process a page
  752. * fault.
  753. */
  754. timers = 0x2 << 4; /* long timer = 1.6 us */
  755. pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
  756. timers);
  757. rc = 0;
  758. out:
  759. kfree(recv_rate);
  760. return rc;
  761. }
  762. EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
  763. int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
  764. {
  765. u32 val;
  766. unsigned long timeout;
  767. pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
  768. &val);
  769. if (EXTRACT_BIT(val, 20)) {
  770. dev_err(&dev->dev,
  771. "Can't terminate PASID %#x, previous termination didn't complete\n",
  772. pasid);
  773. return -EBUSY;
  774. }
  775. val &= ~OCXL_DVSEC_PASID_MASK;
  776. val |= pasid & OCXL_DVSEC_PASID_MASK;
  777. val |= BIT(20);
  778. pci_write_config_dword(dev,
  779. afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
  780. val);
  781. timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
  782. pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
  783. &val);
  784. while (EXTRACT_BIT(val, 20)) {
  785. if (time_after_eq(jiffies, timeout)) {
  786. dev_err(&dev->dev,
  787. "Timeout while waiting for AFU to terminate PASID %#x\n",
  788. pasid);
  789. return -EBUSY;
  790. }
  791. cpu_relax();
  792. pci_read_config_dword(dev,
  793. afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
  794. &val);
  795. }
  796. return 0;
  797. }
  798. EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
  799. void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
  800. u32 tag_count)
  801. {
  802. u32 val;
  803. val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
  804. val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
  805. pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
  806. val);
  807. }
  808. EXPORT_SYMBOL_GPL(ocxl_config_set_actag);