rtsx_pcr.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/module.h>
  11. #include <linux/slab.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/highmem.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/idr.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/mfd/core.h>
  19. #include <linux/rtsx_pci.h>
  20. #include <linux/mmc/card.h>
  21. #include <asm/unaligned.h>
  22. #include "rtsx_pcr.h"
  23. #include "rts5261.h"
  24. #include "rts5228.h"
  25. static bool msi_en = true;
  26. module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  27. MODULE_PARM_DESC(msi_en, "Enable MSI");
  28. static DEFINE_IDR(rtsx_pci_idr);
  29. static DEFINE_SPINLOCK(rtsx_pci_lock);
  30. static struct mfd_cell rtsx_pcr_cells[] = {
  31. [RTSX_SD_CARD] = {
  32. .name = DRV_NAME_RTSX_PCI_SDMMC,
  33. },
  34. };
  35. static const struct pci_device_id rtsx_pci_ids[] = {
  36. { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  37. { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  38. { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  39. { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  40. { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  41. { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  42. { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  43. { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  44. { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  45. { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  46. { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  47. { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  48. { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  49. { 0, }
  50. };
  51. MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  52. static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
  53. {
  54. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  55. PCI_EXP_LNKCTL_ASPMC, 0);
  56. }
  57. static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  58. {
  59. rtsx_pci_write_register(pcr, MSGTXDATA0,
  60. MASK_8_BIT_DEF, (u8) (latency & 0xFF));
  61. rtsx_pci_write_register(pcr, MSGTXDATA1,
  62. MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
  63. rtsx_pci_write_register(pcr, MSGTXDATA2,
  64. MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
  65. rtsx_pci_write_register(pcr, MSGTXDATA3,
  66. MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
  67. rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
  68. LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
  69. return 0;
  70. }
  71. int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
  72. {
  73. return rtsx_comm_set_ltr_latency(pcr, latency);
  74. }
  75. static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
  76. {
  77. if (pcr->aspm_enabled == enable)
  78. return;
  79. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  80. PCI_EXP_LNKCTL_ASPMC,
  81. enable ? pcr->aspm_en : 0);
  82. pcr->aspm_enabled = enable;
  83. }
  84. static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
  85. {
  86. if (pcr->ops->set_aspm)
  87. pcr->ops->set_aspm(pcr, false);
  88. else
  89. rtsx_comm_set_aspm(pcr, false);
  90. }
  91. int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
  92. {
  93. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
  94. return 0;
  95. }
  96. static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
  97. {
  98. if (pcr->ops->set_l1off_cfg_sub_d0)
  99. pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
  100. }
  101. static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
  102. {
  103. struct rtsx_cr_option *option = &pcr->option;
  104. rtsx_disable_aspm(pcr);
  105. /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */
  106. msleep(1);
  107. if (option->ltr_enabled)
  108. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  109. if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
  110. rtsx_set_l1off_sub_cfg_d0(pcr, 1);
  111. }
  112. static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
  113. {
  114. rtsx_comm_pm_full_on(pcr);
  115. }
  116. void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  117. {
  118. /* If pci device removed, don't queue idle work any more */
  119. if (pcr->remove_pci)
  120. return;
  121. if (pcr->state != PDEV_STAT_RUN) {
  122. pcr->state = PDEV_STAT_RUN;
  123. if (pcr->ops->enable_auto_blink)
  124. pcr->ops->enable_auto_blink(pcr);
  125. rtsx_pm_full_on(pcr);
  126. }
  127. mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  128. }
  129. EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  130. int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  131. {
  132. int i;
  133. u32 val = HAIMR_WRITE_START;
  134. val |= (u32)(addr & 0x3FFF) << 16;
  135. val |= (u32)mask << 8;
  136. val |= (u32)data;
  137. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  138. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  139. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  140. if ((val & HAIMR_TRANS_END) == 0) {
  141. if (data != (u8)val)
  142. return -EIO;
  143. return 0;
  144. }
  145. }
  146. return -ETIMEDOUT;
  147. }
  148. EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
  149. int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
  150. {
  151. u32 val = HAIMR_READ_START;
  152. int i;
  153. val |= (u32)(addr & 0x3FFF) << 16;
  154. rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  155. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  156. val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  157. if ((val & HAIMR_TRANS_END) == 0)
  158. break;
  159. }
  160. if (i >= MAX_RW_REG_CNT)
  161. return -ETIMEDOUT;
  162. if (data)
  163. *data = (u8)(val & 0xFF);
  164. return 0;
  165. }
  166. EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
  167. int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
  168. {
  169. int err, i, finished = 0;
  170. u8 tmp;
  171. rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
  172. rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
  173. rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
  174. rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
  175. for (i = 0; i < 100000; i++) {
  176. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  177. if (err < 0)
  178. return err;
  179. if (!(tmp & 0x80)) {
  180. finished = 1;
  181. break;
  182. }
  183. }
  184. if (!finished)
  185. return -ETIMEDOUT;
  186. return 0;
  187. }
  188. int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
  189. {
  190. if (pcr->ops->write_phy)
  191. return pcr->ops->write_phy(pcr, addr, val);
  192. return __rtsx_pci_write_phy_register(pcr, addr, val);
  193. }
  194. EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
  195. int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  196. {
  197. int err, i, finished = 0;
  198. u16 data;
  199. u8 tmp, val1, val2;
  200. rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
  201. rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
  202. for (i = 0; i < 100000; i++) {
  203. err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
  204. if (err < 0)
  205. return err;
  206. if (!(tmp & 0x80)) {
  207. finished = 1;
  208. break;
  209. }
  210. }
  211. if (!finished)
  212. return -ETIMEDOUT;
  213. rtsx_pci_read_register(pcr, PHYDATA0, &val1);
  214. rtsx_pci_read_register(pcr, PHYDATA1, &val2);
  215. data = val1 | (val2 << 8);
  216. if (val)
  217. *val = data;
  218. return 0;
  219. }
  220. int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  221. {
  222. if (pcr->ops->read_phy)
  223. return pcr->ops->read_phy(pcr, addr, val);
  224. return __rtsx_pci_read_phy_register(pcr, addr, val);
  225. }
  226. EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
  227. void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
  228. {
  229. if (pcr->ops->stop_cmd)
  230. return pcr->ops->stop_cmd(pcr);
  231. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  232. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  233. rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
  234. rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
  235. }
  236. EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
  237. void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
  238. u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
  239. {
  240. unsigned long flags;
  241. u32 val = 0;
  242. u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
  243. val |= (u32)(cmd_type & 0x03) << 30;
  244. val |= (u32)(reg_addr & 0x3FFF) << 16;
  245. val |= (u32)mask << 8;
  246. val |= (u32)data;
  247. spin_lock_irqsave(&pcr->lock, flags);
  248. ptr += pcr->ci;
  249. if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
  250. put_unaligned_le32(val, ptr);
  251. ptr++;
  252. pcr->ci++;
  253. }
  254. spin_unlock_irqrestore(&pcr->lock, flags);
  255. }
  256. EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
  257. void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
  258. {
  259. u32 val = 1 << 31;
  260. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  261. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  262. /* Hardware Auto Response */
  263. val |= 0x40000000;
  264. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  265. }
  266. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
  267. int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
  268. {
  269. struct completion trans_done;
  270. u32 val = 1 << 31;
  271. long timeleft;
  272. unsigned long flags;
  273. int err = 0;
  274. spin_lock_irqsave(&pcr->lock, flags);
  275. /* set up data structures for the wakeup system */
  276. pcr->done = &trans_done;
  277. pcr->trans_result = TRANS_NOT_READY;
  278. init_completion(&trans_done);
  279. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  280. val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
  281. /* Hardware Auto Response */
  282. val |= 0x40000000;
  283. rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
  284. spin_unlock_irqrestore(&pcr->lock, flags);
  285. /* Wait for TRANS_OK_INT */
  286. timeleft = wait_for_completion_interruptible_timeout(
  287. &trans_done, msecs_to_jiffies(timeout));
  288. if (timeleft <= 0) {
  289. pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
  290. err = -ETIMEDOUT;
  291. goto finish_send_cmd;
  292. }
  293. spin_lock_irqsave(&pcr->lock, flags);
  294. if (pcr->trans_result == TRANS_RESULT_FAIL)
  295. err = -EINVAL;
  296. else if (pcr->trans_result == TRANS_RESULT_OK)
  297. err = 0;
  298. else if (pcr->trans_result == TRANS_NO_DEVICE)
  299. err = -ENODEV;
  300. spin_unlock_irqrestore(&pcr->lock, flags);
  301. finish_send_cmd:
  302. spin_lock_irqsave(&pcr->lock, flags);
  303. pcr->done = NULL;
  304. spin_unlock_irqrestore(&pcr->lock, flags);
  305. if ((err < 0) && (err != -ENODEV))
  306. rtsx_pci_stop_cmd(pcr);
  307. if (pcr->finish_me)
  308. complete(pcr->finish_me);
  309. return err;
  310. }
  311. EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
  312. static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
  313. dma_addr_t addr, unsigned int len, int end)
  314. {
  315. u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
  316. u64 val;
  317. u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
  318. pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
  319. if (end)
  320. option |= RTSX_SG_END;
  321. if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
  322. if (len > 0xFFFF)
  323. val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
  324. | (((u64)len >> 16) << 6) | option;
  325. else
  326. val = ((u64)addr << 32) | ((u64)len << 16) | option;
  327. } else {
  328. val = ((u64)addr << 32) | ((u64)len << 12) | option;
  329. }
  330. put_unaligned_le64(val, ptr);
  331. pcr->sgi++;
  332. }
  333. int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  334. int num_sg, bool read, int timeout)
  335. {
  336. int err = 0, count;
  337. pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
  338. count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
  339. if (count < 1)
  340. return -EINVAL;
  341. pcr_dbg(pcr, "DMA mapping count: %d\n", count);
  342. err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
  343. rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
  344. return err;
  345. }
  346. EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
  347. int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  348. int num_sg, bool read)
  349. {
  350. enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  351. if (pcr->remove_pci)
  352. return -EINVAL;
  353. if ((sglist == NULL) || (num_sg <= 0))
  354. return -EINVAL;
  355. return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
  356. }
  357. EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
  358. void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  359. int num_sg, bool read)
  360. {
  361. enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  362. dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
  363. }
  364. EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
  365. int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  366. int count, bool read, int timeout)
  367. {
  368. struct completion trans_done;
  369. struct scatterlist *sg;
  370. dma_addr_t addr;
  371. long timeleft;
  372. unsigned long flags;
  373. unsigned int len;
  374. int i, err = 0;
  375. u32 val;
  376. u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
  377. if (pcr->remove_pci)
  378. return -ENODEV;
  379. if ((sglist == NULL) || (count < 1))
  380. return -EINVAL;
  381. val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
  382. pcr->sgi = 0;
  383. for_each_sg(sglist, sg, count, i) {
  384. addr = sg_dma_address(sg);
  385. len = sg_dma_len(sg);
  386. rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
  387. }
  388. spin_lock_irqsave(&pcr->lock, flags);
  389. pcr->done = &trans_done;
  390. pcr->trans_result = TRANS_NOT_READY;
  391. init_completion(&trans_done);
  392. rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
  393. rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
  394. spin_unlock_irqrestore(&pcr->lock, flags);
  395. timeleft = wait_for_completion_interruptible_timeout(
  396. &trans_done, msecs_to_jiffies(timeout));
  397. if (timeleft <= 0) {
  398. pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
  399. err = -ETIMEDOUT;
  400. goto out;
  401. }
  402. spin_lock_irqsave(&pcr->lock, flags);
  403. if (pcr->trans_result == TRANS_RESULT_FAIL) {
  404. err = -EILSEQ;
  405. if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
  406. pcr->dma_error_count++;
  407. }
  408. else if (pcr->trans_result == TRANS_NO_DEVICE)
  409. err = -ENODEV;
  410. spin_unlock_irqrestore(&pcr->lock, flags);
  411. out:
  412. spin_lock_irqsave(&pcr->lock, flags);
  413. pcr->done = NULL;
  414. spin_unlock_irqrestore(&pcr->lock, flags);
  415. if ((err < 0) && (err != -ENODEV))
  416. rtsx_pci_stop_cmd(pcr);
  417. if (pcr->finish_me)
  418. complete(pcr->finish_me);
  419. return err;
  420. }
  421. EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
  422. int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  423. {
  424. int err;
  425. int i, j;
  426. u16 reg;
  427. u8 *ptr;
  428. if (buf_len > 512)
  429. buf_len = 512;
  430. ptr = buf;
  431. reg = PPBUF_BASE2;
  432. for (i = 0; i < buf_len / 256; i++) {
  433. rtsx_pci_init_cmd(pcr);
  434. for (j = 0; j < 256; j++)
  435. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  436. err = rtsx_pci_send_cmd(pcr, 250);
  437. if (err < 0)
  438. return err;
  439. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
  440. ptr += 256;
  441. }
  442. if (buf_len % 256) {
  443. rtsx_pci_init_cmd(pcr);
  444. for (j = 0; j < buf_len % 256; j++)
  445. rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
  446. err = rtsx_pci_send_cmd(pcr, 250);
  447. if (err < 0)
  448. return err;
  449. }
  450. memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
  451. return 0;
  452. }
  453. EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
  454. int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
  455. {
  456. int err;
  457. int i, j;
  458. u16 reg;
  459. u8 *ptr;
  460. if (buf_len > 512)
  461. buf_len = 512;
  462. ptr = buf;
  463. reg = PPBUF_BASE2;
  464. for (i = 0; i < buf_len / 256; i++) {
  465. rtsx_pci_init_cmd(pcr);
  466. for (j = 0; j < 256; j++) {
  467. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  468. reg++, 0xFF, *ptr);
  469. ptr++;
  470. }
  471. err = rtsx_pci_send_cmd(pcr, 250);
  472. if (err < 0)
  473. return err;
  474. }
  475. if (buf_len % 256) {
  476. rtsx_pci_init_cmd(pcr);
  477. for (j = 0; j < buf_len % 256; j++) {
  478. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  479. reg++, 0xFF, *ptr);
  480. ptr++;
  481. }
  482. err = rtsx_pci_send_cmd(pcr, 250);
  483. if (err < 0)
  484. return err;
  485. }
  486. return 0;
  487. }
  488. EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
  489. static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
  490. {
  491. rtsx_pci_init_cmd(pcr);
  492. while (*tbl & 0xFFFF0000) {
  493. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  494. (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
  495. tbl++;
  496. }
  497. return rtsx_pci_send_cmd(pcr, 100);
  498. }
  499. int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
  500. {
  501. const u32 *tbl;
  502. if (card == RTSX_SD_CARD)
  503. tbl = pcr->sd_pull_ctl_enable_tbl;
  504. else if (card == RTSX_MS_CARD)
  505. tbl = pcr->ms_pull_ctl_enable_tbl;
  506. else
  507. return -EINVAL;
  508. return rtsx_pci_set_pull_ctl(pcr, tbl);
  509. }
  510. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
  511. int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
  512. {
  513. const u32 *tbl;
  514. if (card == RTSX_SD_CARD)
  515. tbl = pcr->sd_pull_ctl_disable_tbl;
  516. else if (card == RTSX_MS_CARD)
  517. tbl = pcr->ms_pull_ctl_disable_tbl;
  518. else
  519. return -EINVAL;
  520. return rtsx_pci_set_pull_ctl(pcr, tbl);
  521. }
  522. EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
  523. static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
  524. {
  525. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  526. pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
  527. | hw_param->interrupt_en;
  528. if (pcr->num_slots > 1)
  529. pcr->bier |= MS_INT_EN;
  530. /* Enable Bus Interrupt */
  531. rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
  532. pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
  533. }
  534. static inline u8 double_ssc_depth(u8 depth)
  535. {
  536. return ((depth > 1) ? (depth - 1) : depth);
  537. }
  538. static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
  539. {
  540. if (div > CLK_DIV_1) {
  541. if (ssc_depth > (div - 1))
  542. ssc_depth -= (div - 1);
  543. else
  544. ssc_depth = SSC_DEPTH_4M;
  545. }
  546. return ssc_depth;
  547. }
  548. int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  549. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  550. {
  551. int err, clk;
  552. u8 n, clk_divider, mcu_cnt, div;
  553. static const u8 depth[] = {
  554. [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
  555. [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
  556. [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
  557. [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
  558. [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
  559. };
  560. if (PCI_PID(pcr) == PID_5261)
  561. return rts5261_pci_switch_clock(pcr, card_clock,
  562. ssc_depth, initial_mode, double_clk, vpclk);
  563. if (PCI_PID(pcr) == PID_5228)
  564. return rts5228_pci_switch_clock(pcr, card_clock,
  565. ssc_depth, initial_mode, double_clk, vpclk);
  566. if (initial_mode) {
  567. /* We use 250k(around) here, in initial stage */
  568. clk_divider = SD_CLK_DIVIDE_128;
  569. card_clock = 30000000;
  570. } else {
  571. clk_divider = SD_CLK_DIVIDE_0;
  572. }
  573. err = rtsx_pci_write_register(pcr, SD_CFG1,
  574. SD_CLK_DIVIDE_MASK, clk_divider);
  575. if (err < 0)
  576. return err;
  577. /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
  578. if (card_clock == UHS_SDR104_MAX_DTR &&
  579. pcr->dma_error_count &&
  580. PCI_PID(pcr) == RTS5227_DEVICE_ID)
  581. card_clock = UHS_SDR104_MAX_DTR -
  582. (pcr->dma_error_count * 20000000);
  583. card_clock /= 1000000;
  584. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  585. clk = card_clock;
  586. if (!initial_mode && double_clk)
  587. clk = card_clock * 2;
  588. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  589. clk, pcr->cur_clock);
  590. if (clk == pcr->cur_clock)
  591. return 0;
  592. if (pcr->ops->conv_clk_and_div_n)
  593. n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  594. else
  595. n = (u8)(clk - 2);
  596. if ((clk <= 2) || (n > MAX_DIV_N_PCR))
  597. return -EINVAL;
  598. mcu_cnt = (u8)(125/clk + 3);
  599. if (mcu_cnt > 15)
  600. mcu_cnt = 15;
  601. /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
  602. div = CLK_DIV_1;
  603. while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
  604. if (pcr->ops->conv_clk_and_div_n) {
  605. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  606. DIV_N_TO_CLK) * 2;
  607. n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
  608. CLK_TO_DIV_N);
  609. } else {
  610. n = (n + 2) * 2 - 2;
  611. }
  612. div++;
  613. }
  614. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  615. ssc_depth = depth[ssc_depth];
  616. if (double_clk)
  617. ssc_depth = double_ssc_depth(ssc_depth);
  618. ssc_depth = revise_ssc_depth(ssc_depth, div);
  619. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  620. rtsx_pci_init_cmd(pcr);
  621. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  622. CLK_LOW_FREQ, CLK_LOW_FREQ);
  623. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  624. 0xFF, (div << 4) | mcu_cnt);
  625. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  626. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  627. SSC_DEPTH_MASK, ssc_depth);
  628. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  629. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  630. if (vpclk) {
  631. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  632. PHASE_NOT_RESET, 0);
  633. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  634. PHASE_NOT_RESET, PHASE_NOT_RESET);
  635. }
  636. err = rtsx_pci_send_cmd(pcr, 2000);
  637. if (err < 0)
  638. return err;
  639. /* Wait SSC clock stable */
  640. udelay(SSC_CLOCK_STABLE_WAIT);
  641. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  642. if (err < 0)
  643. return err;
  644. pcr->cur_clock = clk;
  645. return 0;
  646. }
  647. EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
  648. int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
  649. {
  650. if (pcr->ops->card_power_on)
  651. return pcr->ops->card_power_on(pcr, card);
  652. return 0;
  653. }
  654. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
  655. int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
  656. {
  657. if (pcr->ops->card_power_off)
  658. return pcr->ops->card_power_off(pcr, card);
  659. return 0;
  660. }
  661. EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
  662. int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
  663. {
  664. static const unsigned int cd_mask[] = {
  665. [RTSX_SD_CARD] = SD_EXIST,
  666. [RTSX_MS_CARD] = MS_EXIST
  667. };
  668. if (!(pcr->flags & PCR_MS_PMOS)) {
  669. /* When using single PMOS, accessing card is not permitted
  670. * if the existing card is not the designated one.
  671. */
  672. if (pcr->card_exist & (~cd_mask[card]))
  673. return -EIO;
  674. }
  675. return 0;
  676. }
  677. EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
  678. int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  679. {
  680. if (pcr->ops->switch_output_voltage)
  681. return pcr->ops->switch_output_voltage(pcr, voltage);
  682. return 0;
  683. }
  684. EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
  685. unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
  686. {
  687. unsigned int val;
  688. val = rtsx_pci_readl(pcr, RTSX_BIPR);
  689. if (pcr->ops->cd_deglitch)
  690. val = pcr->ops->cd_deglitch(pcr);
  691. return val;
  692. }
  693. EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
  694. void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
  695. {
  696. struct completion finish;
  697. pcr->finish_me = &finish;
  698. init_completion(&finish);
  699. if (pcr->done)
  700. complete(pcr->done);
  701. if (!pcr->remove_pci)
  702. rtsx_pci_stop_cmd(pcr);
  703. wait_for_completion_interruptible_timeout(&finish,
  704. msecs_to_jiffies(2));
  705. pcr->finish_me = NULL;
  706. }
  707. EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
  708. static void rtsx_pci_card_detect(struct work_struct *work)
  709. {
  710. struct delayed_work *dwork;
  711. struct rtsx_pcr *pcr;
  712. unsigned long flags;
  713. unsigned int card_detect = 0, card_inserted, card_removed;
  714. u32 irq_status;
  715. dwork = to_delayed_work(work);
  716. pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
  717. pcr_dbg(pcr, "--> %s\n", __func__);
  718. mutex_lock(&pcr->pcr_mutex);
  719. spin_lock_irqsave(&pcr->lock, flags);
  720. irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
  721. pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
  722. irq_status &= CARD_EXIST;
  723. card_inserted = pcr->card_inserted & irq_status;
  724. card_removed = pcr->card_removed;
  725. pcr->card_inserted = 0;
  726. pcr->card_removed = 0;
  727. spin_unlock_irqrestore(&pcr->lock, flags);
  728. if (card_inserted || card_removed) {
  729. pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
  730. card_inserted, card_removed);
  731. if (pcr->ops->cd_deglitch)
  732. card_inserted = pcr->ops->cd_deglitch(pcr);
  733. card_detect = card_inserted | card_removed;
  734. pcr->card_exist |= card_inserted;
  735. pcr->card_exist &= ~card_removed;
  736. }
  737. mutex_unlock(&pcr->pcr_mutex);
  738. if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
  739. pcr->slots[RTSX_SD_CARD].card_event(
  740. pcr->slots[RTSX_SD_CARD].p_dev);
  741. if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
  742. pcr->slots[RTSX_MS_CARD].card_event(
  743. pcr->slots[RTSX_MS_CARD].p_dev);
  744. }
  745. static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
  746. {
  747. if (pcr->ops->process_ocp) {
  748. pcr->ops->process_ocp(pcr);
  749. } else {
  750. if (!pcr->option.ocp_en)
  751. return;
  752. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  753. if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
  754. rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
  755. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  756. rtsx_pci_clear_ocpstat(pcr);
  757. pcr->ocp_stat = 0;
  758. }
  759. }
  760. }
  761. static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
  762. {
  763. if (pcr->option.ocp_en)
  764. rtsx_pci_process_ocp(pcr);
  765. return 0;
  766. }
  767. static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
  768. {
  769. struct rtsx_pcr *pcr = dev_id;
  770. u32 int_reg;
  771. if (!pcr)
  772. return IRQ_NONE;
  773. spin_lock(&pcr->lock);
  774. int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
  775. /* Clear interrupt flag */
  776. rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
  777. if ((int_reg & pcr->bier) == 0) {
  778. spin_unlock(&pcr->lock);
  779. return IRQ_NONE;
  780. }
  781. if (int_reg == 0xFFFFFFFF) {
  782. spin_unlock(&pcr->lock);
  783. return IRQ_HANDLED;
  784. }
  785. int_reg &= (pcr->bier | 0x7FFFFF);
  786. if (int_reg & SD_OC_INT)
  787. rtsx_pci_process_ocp_interrupt(pcr);
  788. if (int_reg & SD_INT) {
  789. if (int_reg & SD_EXIST) {
  790. pcr->card_inserted |= SD_EXIST;
  791. } else {
  792. pcr->card_removed |= SD_EXIST;
  793. pcr->card_inserted &= ~SD_EXIST;
  794. }
  795. pcr->dma_error_count = 0;
  796. }
  797. if (int_reg & MS_INT) {
  798. if (int_reg & MS_EXIST) {
  799. pcr->card_inserted |= MS_EXIST;
  800. } else {
  801. pcr->card_removed |= MS_EXIST;
  802. pcr->card_inserted &= ~MS_EXIST;
  803. }
  804. }
  805. if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
  806. if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
  807. pcr->trans_result = TRANS_RESULT_FAIL;
  808. if (pcr->done)
  809. complete(pcr->done);
  810. } else if (int_reg & TRANS_OK_INT) {
  811. pcr->trans_result = TRANS_RESULT_OK;
  812. if (pcr->done)
  813. complete(pcr->done);
  814. }
  815. }
  816. if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
  817. schedule_delayed_work(&pcr->carddet_work,
  818. msecs_to_jiffies(200));
  819. spin_unlock(&pcr->lock);
  820. return IRQ_HANDLED;
  821. }
  822. static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
  823. {
  824. pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
  825. __func__, pcr->msi_en, pcr->pci->irq);
  826. if (request_irq(pcr->pci->irq, rtsx_pci_isr,
  827. pcr->msi_en ? 0 : IRQF_SHARED,
  828. DRV_NAME_RTSX_PCI, pcr)) {
  829. dev_err(&(pcr->pci->dev),
  830. "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
  831. pcr->pci->irq);
  832. return -1;
  833. }
  834. pcr->irq = pcr->pci->irq;
  835. pci_intx(pcr->pci, !pcr->msi_en);
  836. return 0;
  837. }
  838. static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
  839. {
  840. if (pcr->ops->set_aspm)
  841. pcr->ops->set_aspm(pcr, true);
  842. else
  843. rtsx_comm_set_aspm(pcr, true);
  844. }
  845. static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
  846. {
  847. struct rtsx_cr_option *option = &pcr->option;
  848. if (option->ltr_enabled) {
  849. u32 latency = option->ltr_l1off_latency;
  850. if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
  851. mdelay(option->l1_snooze_delay);
  852. rtsx_set_ltr_latency(pcr, latency);
  853. }
  854. if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
  855. rtsx_set_l1off_sub_cfg_d0(pcr, 0);
  856. rtsx_enable_aspm(pcr);
  857. }
  858. static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
  859. {
  860. rtsx_comm_pm_power_saving(pcr);
  861. }
  862. static void rtsx_pci_idle_work(struct work_struct *work)
  863. {
  864. struct delayed_work *dwork = to_delayed_work(work);
  865. struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
  866. pcr_dbg(pcr, "--> %s\n", __func__);
  867. mutex_lock(&pcr->pcr_mutex);
  868. pcr->state = PDEV_STAT_IDLE;
  869. if (pcr->ops->disable_auto_blink)
  870. pcr->ops->disable_auto_blink(pcr);
  871. if (pcr->ops->turn_off_led)
  872. pcr->ops->turn_off_led(pcr);
  873. rtsx_pm_power_saving(pcr);
  874. mutex_unlock(&pcr->pcr_mutex);
  875. }
  876. static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  877. {
  878. /* Set relink_time to 0 */
  879. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  880. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  881. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  882. RELINK_TIME_MASK, 0);
  883. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  884. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  885. rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
  886. }
  887. static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
  888. {
  889. if (pcr->ops->turn_off_led)
  890. pcr->ops->turn_off_led(pcr);
  891. rtsx_pci_writel(pcr, RTSX_BIER, 0);
  892. pcr->bier = 0;
  893. rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
  894. rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
  895. if (pcr->ops->force_power_down)
  896. pcr->ops->force_power_down(pcr, pm_state);
  897. else
  898. rtsx_base_force_power_down(pcr, pm_state);
  899. }
  900. void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
  901. {
  902. u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
  903. if (pcr->ops->enable_ocp) {
  904. pcr->ops->enable_ocp(pcr);
  905. } else {
  906. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
  907. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  908. }
  909. }
  910. void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
  911. {
  912. u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
  913. if (pcr->ops->disable_ocp) {
  914. pcr->ops->disable_ocp(pcr);
  915. } else {
  916. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  917. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
  918. OC_POWER_DOWN);
  919. }
  920. }
  921. void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
  922. {
  923. if (pcr->ops->init_ocp) {
  924. pcr->ops->init_ocp(pcr);
  925. } else {
  926. struct rtsx_cr_option *option = &(pcr->option);
  927. if (option->ocp_en) {
  928. u8 val = option->sd_800mA_ocp_thd;
  929. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
  930. rtsx_pci_write_register(pcr, REG_OCPPARA1,
  931. SD_OCP_TIME_MASK, SD_OCP_TIME_800);
  932. rtsx_pci_write_register(pcr, REG_OCPPARA2,
  933. SD_OCP_THD_MASK, val);
  934. rtsx_pci_write_register(pcr, REG_OCPGLITCH,
  935. SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
  936. rtsx_pci_enable_ocp(pcr);
  937. }
  938. }
  939. }
  940. int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
  941. {
  942. if (pcr->ops->get_ocpstat)
  943. return pcr->ops->get_ocpstat(pcr, val);
  944. else
  945. return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
  946. }
  947. void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
  948. {
  949. if (pcr->ops->clear_ocpstat) {
  950. pcr->ops->clear_ocpstat(pcr);
  951. } else {
  952. u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
  953. u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
  954. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  955. udelay(100);
  956. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  957. }
  958. }
  959. void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
  960. {
  961. u16 val;
  962. if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
  963. rtsx_pci_read_phy_register(pcr, 0x01, &val);
  964. val |= 1<<9;
  965. rtsx_pci_write_phy_register(pcr, 0x01, val);
  966. }
  967. rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
  968. rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
  969. rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
  970. rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
  971. }
  972. void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
  973. {
  974. u16 val;
  975. if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
  976. rtsx_pci_read_phy_register(pcr, 0x01, &val);
  977. val &= ~(1<<9);
  978. rtsx_pci_write_phy_register(pcr, 0x01, val);
  979. }
  980. rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
  981. rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
  982. }
  983. int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
  984. {
  985. rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
  986. MS_CLK_EN | SD40_CLK_EN, 0);
  987. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  988. rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
  989. msleep(50);
  990. rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
  991. return 0;
  992. }
  993. int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
  994. {
  995. rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
  996. MS_CLK_EN | SD40_CLK_EN, 0);
  997. rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
  998. rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
  999. rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
  1000. return 0;
  1001. }
  1002. static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
  1003. {
  1004. struct pci_dev *pdev = pcr->pci;
  1005. int err;
  1006. if (PCI_PID(pcr) == PID_5228)
  1007. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
  1008. RTS5228_LDO1_SR_0_5);
  1009. rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
  1010. rtsx_pci_enable_bus_int(pcr);
  1011. /* Power on SSC */
  1012. if (PCI_PID(pcr) == PID_5261) {
  1013. /* Gating real mcu clock */
  1014. err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
  1015. RTS5261_MCU_CLOCK_GATING, 0);
  1016. err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
  1017. SSC_POWER_DOWN, 0);
  1018. } else {
  1019. err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
  1020. }
  1021. if (err < 0)
  1022. return err;
  1023. /* Wait SSC power stable */
  1024. udelay(200);
  1025. rtsx_pci_disable_aspm(pcr);
  1026. if (pcr->ops->optimize_phy) {
  1027. err = pcr->ops->optimize_phy(pcr);
  1028. if (err < 0)
  1029. return err;
  1030. }
  1031. rtsx_pci_init_cmd(pcr);
  1032. /* Set mcu_cnt to 7 to ensure data can be sampled properly */
  1033. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
  1034. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
  1035. /* Disable card clock */
  1036. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
  1037. /* Reset delink mode */
  1038. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
  1039. /* Card driving select */
  1040. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
  1041. 0xFF, pcr->card_drive_sel);
  1042. /* Enable SSC Clock */
  1043. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
  1044. 0xFF, SSC_8X_EN | SSC_SEL_4M);
  1045. if (PCI_PID(pcr) == PID_5261)
  1046. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
  1047. RTS5261_SSC_DEPTH_2M);
  1048. else if (PCI_PID(pcr) == PID_5228)
  1049. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
  1050. RTS5228_SSC_DEPTH_2M);
  1051. else
  1052. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
  1053. /* Disable cd_pwr_save */
  1054. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
  1055. /* Clear Link Ready Interrupt */
  1056. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
  1057. LINK_RDY_INT, LINK_RDY_INT);
  1058. /* Enlarge the estimation window of PERST# glitch
  1059. * to reduce the chance of invalid card interrupt
  1060. */
  1061. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
  1062. /* Update RC oscillator to 400k
  1063. * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
  1064. * 1: 2M 0: 400k
  1065. */
  1066. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
  1067. /* Set interrupt write clear
  1068. * bit 1: U_elbi_if_rd_clr_en
  1069. * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
  1070. * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
  1071. */
  1072. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
  1073. err = rtsx_pci_send_cmd(pcr, 100);
  1074. if (err < 0)
  1075. return err;
  1076. switch (PCI_PID(pcr)) {
  1077. case PID_5250:
  1078. case PID_524A:
  1079. case PID_525A:
  1080. case PID_5260:
  1081. case PID_5261:
  1082. case PID_5228:
  1083. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
  1084. break;
  1085. default:
  1086. break;
  1087. }
  1088. /*init ocp*/
  1089. rtsx_pci_init_ocp(pcr);
  1090. /* Enable clk_request_n to enable clock power management */
  1091. pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
  1092. PCI_EXP_LNKCTL_CLKREQ_EN);
  1093. /* Enter L1 when host tx idle */
  1094. pci_write_config_byte(pdev, 0x70F, 0x5B);
  1095. if (pcr->ops->extra_init_hw) {
  1096. err = pcr->ops->extra_init_hw(pcr);
  1097. if (err < 0)
  1098. return err;
  1099. }
  1100. /* No CD interrupt if probing driver with card inserted.
  1101. * So we need to initialize pcr->card_exist here.
  1102. */
  1103. if (pcr->ops->cd_deglitch)
  1104. pcr->card_exist = pcr->ops->cd_deglitch(pcr);
  1105. else
  1106. pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
  1107. return 0;
  1108. }
  1109. static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
  1110. {
  1111. int err;
  1112. spin_lock_init(&pcr->lock);
  1113. mutex_init(&pcr->pcr_mutex);
  1114. switch (PCI_PID(pcr)) {
  1115. default:
  1116. case 0x5209:
  1117. rts5209_init_params(pcr);
  1118. break;
  1119. case 0x5229:
  1120. rts5229_init_params(pcr);
  1121. break;
  1122. case 0x5289:
  1123. rtl8411_init_params(pcr);
  1124. break;
  1125. case 0x5227:
  1126. rts5227_init_params(pcr);
  1127. break;
  1128. case 0x522A:
  1129. rts522a_init_params(pcr);
  1130. break;
  1131. case 0x5249:
  1132. rts5249_init_params(pcr);
  1133. break;
  1134. case 0x524A:
  1135. rts524a_init_params(pcr);
  1136. break;
  1137. case 0x525A:
  1138. rts525a_init_params(pcr);
  1139. break;
  1140. case 0x5287:
  1141. rtl8411b_init_params(pcr);
  1142. break;
  1143. case 0x5286:
  1144. rtl8402_init_params(pcr);
  1145. break;
  1146. case 0x5260:
  1147. rts5260_init_params(pcr);
  1148. break;
  1149. case 0x5261:
  1150. rts5261_init_params(pcr);
  1151. break;
  1152. case 0x5228:
  1153. rts5228_init_params(pcr);
  1154. break;
  1155. }
  1156. pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
  1157. PCI_PID(pcr), pcr->ic_version);
  1158. pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
  1159. GFP_KERNEL);
  1160. if (!pcr->slots)
  1161. return -ENOMEM;
  1162. if (pcr->ops->fetch_vendor_settings)
  1163. pcr->ops->fetch_vendor_settings(pcr);
  1164. pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
  1165. pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
  1166. pcr->sd30_drive_sel_1v8);
  1167. pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
  1168. pcr->sd30_drive_sel_3v3);
  1169. pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
  1170. pcr->card_drive_sel);
  1171. pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
  1172. pcr->state = PDEV_STAT_IDLE;
  1173. err = rtsx_pci_init_hw(pcr);
  1174. if (err < 0) {
  1175. kfree(pcr->slots);
  1176. return err;
  1177. }
  1178. return 0;
  1179. }
  1180. static int rtsx_pci_probe(struct pci_dev *pcidev,
  1181. const struct pci_device_id *id)
  1182. {
  1183. struct rtsx_pcr *pcr;
  1184. struct pcr_handle *handle;
  1185. u32 base, len;
  1186. int ret, i, bar = 0;
  1187. dev_dbg(&(pcidev->dev),
  1188. ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
  1189. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
  1190. (int)pcidev->revision);
  1191. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  1192. if (ret < 0)
  1193. return ret;
  1194. ret = pci_enable_device(pcidev);
  1195. if (ret)
  1196. return ret;
  1197. ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
  1198. if (ret)
  1199. goto disable;
  1200. pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
  1201. if (!pcr) {
  1202. ret = -ENOMEM;
  1203. goto release_pci;
  1204. }
  1205. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1206. if (!handle) {
  1207. ret = -ENOMEM;
  1208. goto free_pcr;
  1209. }
  1210. handle->pcr = pcr;
  1211. idr_preload(GFP_KERNEL);
  1212. spin_lock(&rtsx_pci_lock);
  1213. ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
  1214. if (ret >= 0)
  1215. pcr->id = ret;
  1216. spin_unlock(&rtsx_pci_lock);
  1217. idr_preload_end();
  1218. if (ret < 0)
  1219. goto free_handle;
  1220. pcr->pci = pcidev;
  1221. dev_set_drvdata(&pcidev->dev, handle);
  1222. if (CHK_PCI_PID(pcr, 0x525A))
  1223. bar = 1;
  1224. len = pci_resource_len(pcidev, bar);
  1225. base = pci_resource_start(pcidev, bar);
  1226. pcr->remap_addr = ioremap(base, len);
  1227. if (!pcr->remap_addr) {
  1228. ret = -ENOMEM;
  1229. goto free_handle;
  1230. }
  1231. pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
  1232. RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
  1233. GFP_KERNEL);
  1234. if (pcr->rtsx_resv_buf == NULL) {
  1235. ret = -ENXIO;
  1236. goto unmap;
  1237. }
  1238. pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
  1239. pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
  1240. pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
  1241. pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
  1242. pcr->card_inserted = 0;
  1243. pcr->card_removed = 0;
  1244. INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
  1245. INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
  1246. pcr->msi_en = msi_en;
  1247. if (pcr->msi_en) {
  1248. ret = pci_enable_msi(pcidev);
  1249. if (ret)
  1250. pcr->msi_en = false;
  1251. }
  1252. ret = rtsx_pci_acquire_irq(pcr);
  1253. if (ret < 0)
  1254. goto disable_msi;
  1255. pci_set_master(pcidev);
  1256. synchronize_irq(pcr->irq);
  1257. ret = rtsx_pci_init_chip(pcr);
  1258. if (ret < 0)
  1259. goto disable_irq;
  1260. for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
  1261. rtsx_pcr_cells[i].platform_data = handle;
  1262. rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
  1263. }
  1264. ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
  1265. ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
  1266. if (ret < 0)
  1267. goto free_slots;
  1268. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  1269. return 0;
  1270. free_slots:
  1271. kfree(pcr->slots);
  1272. disable_irq:
  1273. free_irq(pcr->irq, (void *)pcr);
  1274. disable_msi:
  1275. if (pcr->msi_en)
  1276. pci_disable_msi(pcr->pci);
  1277. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  1278. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  1279. unmap:
  1280. iounmap(pcr->remap_addr);
  1281. free_handle:
  1282. kfree(handle);
  1283. free_pcr:
  1284. kfree(pcr);
  1285. release_pci:
  1286. pci_release_regions(pcidev);
  1287. disable:
  1288. pci_disable_device(pcidev);
  1289. return ret;
  1290. }
  1291. static void rtsx_pci_remove(struct pci_dev *pcidev)
  1292. {
  1293. struct pcr_handle *handle = pci_get_drvdata(pcidev);
  1294. struct rtsx_pcr *pcr = handle->pcr;
  1295. pcr->remove_pci = true;
  1296. /* Disable interrupts at the pcr level */
  1297. spin_lock_irq(&pcr->lock);
  1298. rtsx_pci_writel(pcr, RTSX_BIER, 0);
  1299. pcr->bier = 0;
  1300. spin_unlock_irq(&pcr->lock);
  1301. cancel_delayed_work_sync(&pcr->carddet_work);
  1302. cancel_delayed_work_sync(&pcr->idle_work);
  1303. mfd_remove_devices(&pcidev->dev);
  1304. dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
  1305. pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
  1306. free_irq(pcr->irq, (void *)pcr);
  1307. if (pcr->msi_en)
  1308. pci_disable_msi(pcr->pci);
  1309. iounmap(pcr->remap_addr);
  1310. pci_release_regions(pcidev);
  1311. pci_disable_device(pcidev);
  1312. spin_lock(&rtsx_pci_lock);
  1313. idr_remove(&rtsx_pci_idr, pcr->id);
  1314. spin_unlock(&rtsx_pci_lock);
  1315. kfree(pcr->slots);
  1316. kfree(pcr);
  1317. kfree(handle);
  1318. dev_dbg(&(pcidev->dev),
  1319. ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
  1320. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
  1321. }
  1322. static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
  1323. {
  1324. struct pci_dev *pcidev = to_pci_dev(dev_d);
  1325. struct pcr_handle *handle;
  1326. struct rtsx_pcr *pcr;
  1327. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1328. handle = pci_get_drvdata(pcidev);
  1329. pcr = handle->pcr;
  1330. cancel_delayed_work(&pcr->carddet_work);
  1331. cancel_delayed_work(&pcr->idle_work);
  1332. mutex_lock(&pcr->pcr_mutex);
  1333. rtsx_pci_power_off(pcr, HOST_ENTER_S3);
  1334. device_wakeup_disable(dev_d);
  1335. mutex_unlock(&pcr->pcr_mutex);
  1336. return 0;
  1337. }
  1338. static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
  1339. {
  1340. struct pci_dev *pcidev = to_pci_dev(dev_d);
  1341. struct pcr_handle *handle;
  1342. struct rtsx_pcr *pcr;
  1343. int ret = 0;
  1344. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1345. handle = pci_get_drvdata(pcidev);
  1346. pcr = handle->pcr;
  1347. mutex_lock(&pcr->pcr_mutex);
  1348. ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
  1349. if (ret)
  1350. goto out;
  1351. ret = rtsx_pci_init_hw(pcr);
  1352. if (ret)
  1353. goto out;
  1354. schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
  1355. out:
  1356. mutex_unlock(&pcr->pcr_mutex);
  1357. return ret;
  1358. }
  1359. #ifdef CONFIG_PM
  1360. static void rtsx_pci_shutdown(struct pci_dev *pcidev)
  1361. {
  1362. struct pcr_handle *handle;
  1363. struct rtsx_pcr *pcr;
  1364. dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
  1365. handle = pci_get_drvdata(pcidev);
  1366. pcr = handle->pcr;
  1367. rtsx_pci_power_off(pcr, HOST_ENTER_S1);
  1368. pci_disable_device(pcidev);
  1369. free_irq(pcr->irq, (void *)pcr);
  1370. if (pcr->msi_en)
  1371. pci_disable_msi(pcr->pci);
  1372. }
  1373. #else /* CONFIG_PM */
  1374. #define rtsx_pci_shutdown NULL
  1375. #endif /* CONFIG_PM */
  1376. static SIMPLE_DEV_PM_OPS(rtsx_pci_pm_ops, rtsx_pci_suspend, rtsx_pci_resume);
  1377. static struct pci_driver rtsx_pci_driver = {
  1378. .name = DRV_NAME_RTSX_PCI,
  1379. .id_table = rtsx_pci_ids,
  1380. .probe = rtsx_pci_probe,
  1381. .remove = rtsx_pci_remove,
  1382. .driver.pm = &rtsx_pci_pm_ops,
  1383. .shutdown = rtsx_pci_shutdown,
  1384. };
  1385. module_pci_driver(rtsx_pci_driver);
  1386. MODULE_LICENSE("GPL");
  1387. MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
  1388. MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");