rts5261.h 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Rui FENG <rui_feng@realsil.com.cn>
  8. * Wei WANG <wei_wang@realsil.com.cn>
  9. */
  10. #ifndef RTS5261_H
  11. #define RTS5261_H
  12. /*New add*/
  13. #define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000)
  14. #define rts5261_reg_to_aspm(reg) (((reg) >> 28) ^ 0x03)
  15. #define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04)
  16. #define rts5261_reg_to_card_drive_sel(reg) ((((reg) >> 6) & 0x01) << 6)
  17. #define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) ^ 0x03)
  18. #define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) ^ 0x03)
  19. #define RTS5261_AUTOLOAD_CFG0 0xFF7B
  20. #define RTS5261_AUTOLOAD_CFG1 0xFF7C
  21. #define RTS5261_AUTOLOAD_CFG2 0xFF7D
  22. #define RTS5261_AUTOLOAD_CFG3 0xFF7E
  23. #define RTS5261_AUTOLOAD_CFG4 0xFF7F
  24. #define RTS5261_FORCE_PRSNT_LOW (1 << 6)
  25. #define RTS5261_AUX_CLK_16M_EN (1 << 5)
  26. #define RTS5261_REG_VREF 0xFE97
  27. #define RTS5261_PWD_SUSPND_EN (1 << 4)
  28. #define RTS5261_PAD_H3L1 0xFF79
  29. #define PAD_GPIO_H3L1 (1 << 3)
  30. /* SSC_CTL2 0xFC12 */
  31. #define RTS5261_SSC_DEPTH_MASK 0x07
  32. #define RTS5261_SSC_DEPTH_DISALBE 0x00
  33. #define RTS5261_SSC_DEPTH_8M 0x01
  34. #define RTS5261_SSC_DEPTH_4M 0x02
  35. #define RTS5261_SSC_DEPTH_2M 0x03
  36. #define RTS5261_SSC_DEPTH_1M 0x04
  37. #define RTS5261_SSC_DEPTH_512K 0x05
  38. #define RTS5261_SSC_DEPTH_256K 0x06
  39. #define RTS5261_SSC_DEPTH_128K 0x07
  40. /* efuse control register*/
  41. #define RTS5261_EFUSE_CTL 0xFC30
  42. #define RTS5261_EFUSE_ENABLE 0x80
  43. /* EFUSE_MODE: 0=READ 1=PROGRAM */
  44. #define RTS5261_EFUSE_MODE_MASK 0x40
  45. #define RTS5261_EFUSE_PROGRAM 0x40
  46. #define RTS5261_EFUSE_ADDR 0xFC31
  47. #define RTS5261_EFUSE_ADDR_MASK 0x3F
  48. #define RTS5261_EFUSE_WRITE_DATA 0xFC32
  49. #define RTS5261_EFUSE_READ_DATA 0xFC34
  50. /* DMACTL 0xFE2C */
  51. #define RTS5261_DMA_PACK_SIZE_MASK 0xF0
  52. /* FW config info register */
  53. #define RTS5261_FW_CFG_INFO0 0xFF50
  54. #define RTS5261_FW_EXPRESS_TEST_MASK (0x01<<0)
  55. #define RTS5261_FW_EA_MODE_MASK (0x01<<5)
  56. /* FW config register */
  57. #define RTS5261_FW_CFG0 0xFF54
  58. #define RTS5261_FW_ENTER_EXPRESS (0x01<<0)
  59. #define RTS5261_FW_CFG1 0xFF55
  60. #define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01<<7)
  61. #define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01<<6)
  62. #define RTS5261_FAKE_MCU_CLOCK_GATING (0x01<<5)
  63. /*MCU_bus_mode_sel: 0=real 8051 1=fake mcu*/
  64. #define RTS5261_MCU_BUS_SEL_MASK (0x01<<4)
  65. /*MCU_clock_sel:VerA 00=aux16M 01=aux400K 1x=REFCLK100M*/
  66. /*MCU_clock_sel:VerB 00=aux400K 01=aux16M 10=REFCLK100M*/
  67. #define RTS5261_MCU_CLOCK_SEL_MASK (0x03<<2)
  68. #define RTS5261_MCU_CLOCK_SEL_16M (0x01<<2)
  69. #define RTS5261_MCU_CLOCK_GATING (0x01<<1)
  70. #define RTS5261_DRIVER_ENABLE_FW (0x01<<0)
  71. /* FW status register */
  72. #define RTS5261_FW_STATUS 0xFF56
  73. #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7)
  74. /* FW control register */
  75. #define RTS5261_FW_CTL 0xFF5F
  76. #define RTS5261_INFORM_RTD3_COLD (0x01<<5)
  77. #define RTS5261_REG_FPDCTL 0xFF60
  78. #define RTS5261_REG_LDO12_CFG 0xFF6E
  79. #define RTS5261_LDO12_VO_TUNE_MASK (0x07<<1)
  80. #define RTS5261_LDO12_115 (0x03<<1)
  81. #define RTS5261_LDO12_120 (0x04<<1)
  82. #define RTS5261_LDO12_125 (0x05<<1)
  83. #define RTS5261_LDO12_130 (0x06<<1)
  84. #define RTS5261_LDO12_135 (0x07<<1)
  85. /* LDO control register */
  86. #define RTS5261_CARD_PWR_CTL 0xFD50
  87. #define RTS5261_SD_CLK_ISO (0x01<<7)
  88. #define RTS5261_PAD_SD_DAT_FW_CTRL (0x01<<6)
  89. #define RTS5261_PUPDC (0x01<<5)
  90. #define RTS5261_SD_CMD_ISO (0x01<<4)
  91. #define RTS5261_SD_DAT_ISO_MASK (0x0F<<0)
  92. #define RTS5261_LDO1233318_POW_CTL 0xFF70
  93. #define RTS5261_LDO3318_POWERON (0x01<<3)
  94. #define RTS5261_LDO3_POWERON (0x01<<2)
  95. #define RTS5261_LDO2_POWERON (0x01<<1)
  96. #define RTS5261_LDO1_POWERON (0x01<<0)
  97. #define RTS5261_LDO_POWERON_MASK (0x0F<<0)
  98. #define RTS5261_DV3318_CFG 0xFF71
  99. #define RTS5261_DV3318_TUNE_MASK (0x07<<4)
  100. #define RTS5261_DV3318_18 (0x02<<4)
  101. #define RTS5261_DV3318_19 (0x04<<4)
  102. #define RTS5261_DV3318_33 (0x07<<4)
  103. #define RTS5261_LDO1_CFG0 0xFF72
  104. #define RTS5261_LDO1_OCP_THD_MASK (0x07<<5)
  105. #define RTS5261_LDO1_OCP_EN (0x01<<4)
  106. #define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03<<2)
  107. #define RTS5261_LDO1_OCP_LMT_EN (0x01<<1)
  108. /* CRD6603-433 190319 request changed */
  109. #define RTS5261_LDO1_OCP_THD_740 (0x00<<5)
  110. #define RTS5261_LDO1_OCP_THD_800 (0x01<<5)
  111. #define RTS5261_LDO1_OCP_THD_860 (0x02<<5)
  112. #define RTS5261_LDO1_OCP_THD_920 (0x03<<5)
  113. #define RTS5261_LDO1_OCP_THD_980 (0x04<<5)
  114. #define RTS5261_LDO1_OCP_THD_1040 (0x05<<5)
  115. #define RTS5261_LDO1_OCP_THD_1100 (0x06<<5)
  116. #define RTS5261_LDO1_OCP_THD_1160 (0x07<<5)
  117. #define RTS5261_LDO1_LMT_THD_450 (0x00<<2)
  118. #define RTS5261_LDO1_LMT_THD_1000 (0x01<<2)
  119. #define RTS5261_LDO1_LMT_THD_1500 (0x02<<2)
  120. #define RTS5261_LDO1_LMT_THD_2000 (0x03<<2)
  121. #define RTS5261_LDO1_CFG1 0xFF73
  122. #define RTS5261_LDO1_TUNE_MASK (0x07<<1)
  123. #define RTS5261_LDO1_18 (0x05<<1)
  124. #define RTS5261_LDO1_33 (0x07<<1)
  125. #define RTS5261_LDO1_PWD_MASK (0x01<<0)
  126. #define RTS5261_LDO2_CFG0 0xFF74
  127. #define RTS5261_LDO2_OCP_THD_MASK (0x07<<5)
  128. #define RTS5261_LDO2_OCP_EN (0x01<<4)
  129. #define RTS5261_LDO2_OCP_LMT_THD_MASK (0x03<<2)
  130. #define RTS5261_LDO2_OCP_LMT_EN (0x01<<1)
  131. #define RTS5261_LDO2_OCP_THD_620 (0x00<<5)
  132. #define RTS5261_LDO2_OCP_THD_650 (0x01<<5)
  133. #define RTS5261_LDO2_OCP_THD_680 (0x02<<5)
  134. #define RTS5261_LDO2_OCP_THD_720 (0x03<<5)
  135. #define RTS5261_LDO2_OCP_THD_750 (0x04<<5)
  136. #define RTS5261_LDO2_OCP_THD_780 (0x05<<5)
  137. #define RTS5261_LDO2_OCP_THD_810 (0x06<<5)
  138. #define RTS5261_LDO2_OCP_THD_840 (0x07<<5)
  139. #define RTS5261_LDO2_CFG1 0xFF75
  140. #define RTS5261_LDO2_TUNE_MASK (0x07<<1)
  141. #define RTS5261_LDO2_18 (0x05<<1)
  142. #define RTS5261_LDO2_33 (0x07<<1)
  143. #define RTS5261_LDO2_PWD_MASK (0x01<<0)
  144. #define RTS5261_LDO3_CFG0 0xFF76
  145. #define RTS5261_LDO3_OCP_THD_MASK (0x07<<5)
  146. #define RTS5261_LDO3_OCP_EN (0x01<<4)
  147. #define RTS5261_LDO3_OCP_LMT_THD_MASK (0x03<<2)
  148. #define RTS5261_LDO3_OCP_LMT_EN (0x01<<1)
  149. #define RTS5261_LDO3_OCP_THD_620 (0x00<<5)
  150. #define RTS5261_LDO3_OCP_THD_650 (0x01<<5)
  151. #define RTS5261_LDO3_OCP_THD_680 (0x02<<5)
  152. #define RTS5261_LDO3_OCP_THD_720 (0x03<<5)
  153. #define RTS5261_LDO3_OCP_THD_750 (0x04<<5)
  154. #define RTS5261_LDO3_OCP_THD_780 (0x05<<5)
  155. #define RTS5261_LDO3_OCP_THD_810 (0x06<<5)
  156. #define RTS5261_LDO3_OCP_THD_840 (0x07<<5)
  157. #define RTS5261_LDO3_CFG1 0xFF77
  158. #define RTS5261_LDO3_TUNE_MASK (0x07<<1)
  159. #define RTS5261_LDO3_18 (0x05<<1)
  160. #define RTS5261_LDO3_33 (0x07<<1)
  161. #define RTS5261_LDO3_PWD_MASK (0x01<<0)
  162. #define RTS5261_REG_PME_FORCE_CTL 0xFF78
  163. #define FORCE_PM_CONTROL 0x20
  164. #define FORCE_PM_VALUE 0x10
  165. #define REG_EFUSE_BYPASS 0x08
  166. #define REG_EFUSE_POR 0x04
  167. #define REG_EFUSE_POWER_MASK 0x03
  168. #define REG_EFUSE_POWERON 0x03
  169. #define REG_EFUSE_POWEROFF 0x00
  170. /* Single LUN, support SD/SD EXPRESS */
  171. #define DEFAULT_SINGLE 0
  172. #define SD_LUN 1
  173. #define SD_EXPRESS_LUN 2
  174. /* For Change_FPGA_SSCClock Function */
  175. #define MULTIPLY_BY_1 0x00
  176. #define MULTIPLY_BY_2 0x01
  177. #define MULTIPLY_BY_3 0x02
  178. #define MULTIPLY_BY_4 0x03
  179. #define MULTIPLY_BY_5 0x04
  180. #define MULTIPLY_BY_6 0x05
  181. #define MULTIPLY_BY_7 0x06
  182. #define MULTIPLY_BY_8 0x07
  183. #define MULTIPLY_BY_9 0x08
  184. #define MULTIPLY_BY_10 0x09
  185. #define DIVIDE_BY_2 0x01
  186. #define DIVIDE_BY_3 0x02
  187. #define DIVIDE_BY_4 0x03
  188. #define DIVIDE_BY_5 0x04
  189. #define DIVIDE_BY_6 0x05
  190. #define DIVIDE_BY_7 0x06
  191. #define DIVIDE_BY_8 0x07
  192. #define DIVIDE_BY_9 0x08
  193. #define DIVIDE_BY_10 0x09
  194. int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  195. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
  196. #endif /* RTS5261_H */