rts5261.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Rui FENG <rui_feng@realsil.com.cn>
  8. * Wei WANG <wei_wang@realsil.com.cn>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/rtsx_pci.h>
  13. #include "rts5261.h"
  14. #include "rtsx_pcr.h"
  15. static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
  16. {
  17. u8 val;
  18. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  19. return val & IC_VERSION_MASK;
  20. }
  21. static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  22. {
  23. u8 driving_3v3[4][3] = {
  24. {0x13, 0x13, 0x13},
  25. {0x96, 0x96, 0x96},
  26. {0x7F, 0x7F, 0x7F},
  27. {0x96, 0x96, 0x96},
  28. };
  29. u8 driving_1v8[4][3] = {
  30. {0x99, 0x99, 0x99},
  31. {0x3A, 0x3A, 0x3A},
  32. {0xE6, 0xE6, 0xE6},
  33. {0xB3, 0xB3, 0xB3},
  34. };
  35. u8 (*driving)[3], drive_sel;
  36. if (voltage == OUTPUT_3V3) {
  37. driving = driving_3v3;
  38. drive_sel = pcr->sd30_drive_sel_3v3;
  39. } else {
  40. driving = driving_1v8;
  41. drive_sel = pcr->sd30_drive_sel_1v8;
  42. }
  43. rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  44. 0xFF, driving[drive_sel][0]);
  45. rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  46. 0xFF, driving[drive_sel][1]);
  47. rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  48. 0xFF, driving[drive_sel][2]);
  49. }
  50. static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
  51. {
  52. struct pci_dev *pdev = pcr->pci;
  53. u32 reg;
  54. /* 0x814~0x817 */
  55. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  56. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  57. if (!rts5261_vendor_setting_valid(reg)) {
  58. pcr_dbg(pcr, "skip fetch vendor setting\n");
  59. return;
  60. }
  61. pcr->card_drive_sel &= 0x3F;
  62. pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
  63. if (rts5261_reg_check_reverse_socket(reg))
  64. pcr->flags |= PCR_REVERSE_SOCKET;
  65. /* 0x724~0x727 */
  66. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  67. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  68. pcr->aspm_en = rts5261_reg_to_aspm(reg);
  69. pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
  70. pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
  71. }
  72. static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  73. {
  74. /* Set relink_time to 0 */
  75. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  76. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  77. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  78. RELINK_TIME_MASK, 0);
  79. if (pm_state == HOST_ENTER_S3)
  80. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  81. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  82. rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
  83. SSC_POWER_DOWN, SSC_POWER_DOWN);
  84. }
  85. static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
  86. {
  87. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  88. LED_SHINE_MASK, LED_SHINE_EN);
  89. }
  90. static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
  91. {
  92. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  93. LED_SHINE_MASK, LED_SHINE_DISABLE);
  94. }
  95. static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
  96. {
  97. return rtsx_pci_write_register(pcr, GPIO_CTL,
  98. 0x02, 0x02);
  99. }
  100. static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
  101. {
  102. return rtsx_pci_write_register(pcr, GPIO_CTL,
  103. 0x02, 0x00);
  104. }
  105. /* SD Pull Control Enable:
  106. * SD_DAT[3:0] ==> pull up
  107. * SD_CD ==> pull up
  108. * SD_WP ==> pull up
  109. * SD_CMD ==> pull up
  110. * SD_CLK ==> pull down
  111. */
  112. static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
  113. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  114. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  115. 0,
  116. };
  117. /* SD Pull Control Disable:
  118. * SD_DAT[3:0] ==> pull down
  119. * SD_CD ==> pull up
  120. * SD_WP ==> pull down
  121. * SD_CMD ==> pull down
  122. * SD_CLK ==> pull down
  123. */
  124. static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
  125. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  126. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  127. 0,
  128. };
  129. static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
  130. {
  131. rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
  132. | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
  133. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
  134. rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
  135. CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
  136. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  137. return 0;
  138. }
  139. static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
  140. {
  141. struct rtsx_cr_option *option = &pcr->option;
  142. if (option->ocp_en)
  143. rtsx_pci_enable_ocp(pcr);
  144. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
  145. RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
  146. rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  147. RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
  148. rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  149. RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
  150. msleep(20);
  151. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
  152. /* Initialize SD_CFG1 register */
  153. rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
  154. SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
  155. rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
  156. 0xFF, SD20_RX_POS_EDGE);
  157. rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
  158. rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
  159. SD_STOP | SD_CLR_ERR);
  160. /* Reset SD_CFG3 register */
  161. rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
  162. rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
  163. SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
  164. SD30_CLK_STOP_CFG0, 0);
  165. if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
  166. pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
  167. rts5261_sd_set_sample_push_timing_sd30(pcr);
  168. return 0;
  169. }
  170. static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  171. {
  172. int err;
  173. u16 val = 0;
  174. rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
  175. RTS5261_PUPDC, RTS5261_PUPDC);
  176. switch (voltage) {
  177. case OUTPUT_3V3:
  178. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  179. val |= PHY_TUNE_SDBUS_33;
  180. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  181. if (err < 0)
  182. return err;
  183. rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
  184. RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
  185. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  186. SD_IO_USING_1V8, 0);
  187. break;
  188. case OUTPUT_1V8:
  189. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  190. val &= ~PHY_TUNE_SDBUS_33;
  191. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  192. if (err < 0)
  193. return err;
  194. rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
  195. RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
  196. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  197. SD_IO_USING_1V8, SD_IO_USING_1V8);
  198. break;
  199. default:
  200. return -EINVAL;
  201. }
  202. /* set pad drive */
  203. rts5261_fill_driving(pcr, voltage);
  204. return 0;
  205. }
  206. static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
  207. {
  208. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  209. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  210. rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
  211. RTS5260_DMA_RST | RTS5260_ADMA3_RST,
  212. RTS5260_DMA_RST | RTS5260_ADMA3_RST);
  213. rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
  214. }
  215. static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
  216. {
  217. rts5261_stop_cmd(pcr);
  218. rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
  219. }
  220. static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
  221. {
  222. u8 val = 0;
  223. val = SD_OCP_INT_EN | SD_DETECT_EN;
  224. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  225. }
  226. static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
  227. {
  228. u8 mask = 0;
  229. mask = SD_OCP_INT_EN | SD_DETECT_EN;
  230. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  231. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  232. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
  233. }
  234. static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
  235. {
  236. int err = 0;
  237. rts5261_card_before_power_off(pcr);
  238. err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  239. RTS5261_LDO_POWERON_MASK, 0);
  240. if (pcr->option.ocp_en)
  241. rtsx_pci_disable_ocp(pcr);
  242. return err;
  243. }
  244. static void rts5261_init_ocp(struct rtsx_pcr *pcr)
  245. {
  246. struct rtsx_cr_option *option = &pcr->option;
  247. if (option->ocp_en) {
  248. u8 mask, val;
  249. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  250. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
  251. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
  252. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  253. RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
  254. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  255. RTS5261_LDO1_OCP_LMT_THD_MASK,
  256. RTS5261_LDO1_LMT_THD_2000);
  257. mask = SD_OCP_GLITCH_MASK;
  258. val = pcr->hw_param.ocp_glitch;
  259. rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
  260. rts5261_enable_ocp(pcr);
  261. } else {
  262. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  263. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
  264. }
  265. }
  266. static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
  267. {
  268. u8 mask = 0;
  269. u8 val = 0;
  270. mask = SD_OCP_INT_CLR | SD_OC_CLR;
  271. val = SD_OCP_INT_CLR | SD_OC_CLR;
  272. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  273. udelay(10);
  274. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  275. }
  276. static void rts5261_process_ocp(struct rtsx_pcr *pcr)
  277. {
  278. if (!pcr->option.ocp_en)
  279. return;
  280. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  281. if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
  282. rts5261_card_power_off(pcr, RTSX_SD_CARD);
  283. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  284. rts5261_clear_ocpstat(pcr);
  285. pcr->ocp_stat = 0;
  286. }
  287. }
  288. static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
  289. {
  290. struct pci_dev *pdev = pcr->pci;
  291. int retval;
  292. u32 lval, i;
  293. u8 valid, efuse_valid, tmp;
  294. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  295. REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
  296. REG_EFUSE_POR | REG_EFUSE_POWERON);
  297. udelay(1);
  298. rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
  299. RTS5261_EFUSE_ADDR_MASK, 0x00);
  300. rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
  301. RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
  302. RTS5261_EFUSE_ENABLE);
  303. /* Wait transfer end */
  304. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  305. rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
  306. if ((tmp & 0x80) == 0)
  307. break;
  308. }
  309. rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
  310. efuse_valid = ((tmp & 0x0C) >> 2);
  311. pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
  312. if (efuse_valid == 0) {
  313. retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
  314. if (retval != 0)
  315. pcr_dbg(pcr, "read 0x814 DW fail\n");
  316. pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
  317. /* 0x816 */
  318. valid = (u8)((lval >> 16) & 0x03);
  319. pcr_dbg(pcr, "0x816: %d\n", valid);
  320. }
  321. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  322. REG_EFUSE_POR, 0);
  323. pcr_dbg(pcr, "Disable efuse por!\n");
  324. pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
  325. lval = lval & 0x00FFFFFF;
  326. retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
  327. if (retval != 0)
  328. pcr_dbg(pcr, "write config fail\n");
  329. return retval;
  330. }
  331. static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
  332. {
  333. struct pci_dev *pdev = pcr->pci;
  334. int l1ss;
  335. u32 lval;
  336. struct rtsx_cr_option *option = &pcr->option;
  337. l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  338. if (!l1ss)
  339. return;
  340. pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  341. if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
  342. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  343. else
  344. rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
  345. if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
  346. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  347. else
  348. rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
  349. if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
  350. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  351. else
  352. rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
  353. if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
  354. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  355. else
  356. rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
  357. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
  358. if (option->ltr_en) {
  359. u16 val;
  360. pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
  361. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  362. option->ltr_enabled = true;
  363. option->ltr_active = true;
  364. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  365. } else {
  366. option->ltr_enabled = false;
  367. }
  368. }
  369. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  370. | PM_L1_1_EN | PM_L1_2_EN))
  371. option->force_clkreq_0 = false;
  372. else
  373. option->force_clkreq_0 = true;
  374. }
  375. static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
  376. {
  377. struct rtsx_cr_option *option = &pcr->option;
  378. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
  379. CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
  380. rts5261_init_from_cfg(pcr);
  381. rts5261_init_from_hw(pcr);
  382. /* power off efuse */
  383. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  384. REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
  385. rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
  386. AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
  387. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
  388. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
  389. RTS5261_AUX_CLK_16M_EN, 0);
  390. /* Release PRSNT# */
  391. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
  392. RTS5261_FORCE_PRSNT_LOW, 0);
  393. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  394. FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
  395. rtsx_pci_write_register(pcr, PCLK_CTL,
  396. PCLK_MODE_SEL, PCLK_MODE_SEL);
  397. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  398. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
  399. /* LED shine disabled, set initial shine cycle period */
  400. rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
  401. /* Configure driving */
  402. rts5261_fill_driving(pcr, OUTPUT_3V3);
  403. /*
  404. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  405. * to drive low, and we forcibly request clock.
  406. */
  407. if (option->force_clkreq_0)
  408. rtsx_pci_write_register(pcr, PETXCFG,
  409. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  410. else
  411. rtsx_pci_write_register(pcr, PETXCFG,
  412. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  413. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
  414. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  415. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  416. /* Clear Enter RTD3_cold Information*/
  417. rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
  418. RTS5261_INFORM_RTD3_COLD, 0);
  419. return 0;
  420. }
  421. static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
  422. {
  423. if (pcr->aspm_enabled == enable)
  424. return;
  425. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  426. PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
  427. pcr->aspm_enabled = enable;
  428. }
  429. static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
  430. {
  431. if (pcr->aspm_enabled == enable)
  432. return;
  433. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  434. PCI_EXP_LNKCTL_ASPMC, 0);
  435. rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
  436. udelay(10);
  437. pcr->aspm_enabled = enable;
  438. }
  439. static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
  440. {
  441. if (enable)
  442. rts5261_enable_aspm(pcr, true);
  443. else
  444. rts5261_disable_aspm(pcr, false);
  445. }
  446. static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  447. {
  448. struct rtsx_cr_option *option = &pcr->option;
  449. int aspm_L1_1, aspm_L1_2;
  450. u8 val = 0;
  451. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  452. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  453. if (active) {
  454. /* run, latency: 60us */
  455. if (aspm_L1_1)
  456. val = option->ltr_l1off_snooze_sspwrgate;
  457. } else {
  458. /* l1off, latency: 300us */
  459. if (aspm_L1_2)
  460. val = option->ltr_l1off_sspwrgate;
  461. }
  462. rtsx_set_l1off_sub(pcr, val);
  463. }
  464. static const struct pcr_ops rts5261_pcr_ops = {
  465. .fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
  466. .turn_on_led = rts5261_turn_on_led,
  467. .turn_off_led = rts5261_turn_off_led,
  468. .extra_init_hw = rts5261_extra_init_hw,
  469. .enable_auto_blink = rts5261_enable_auto_blink,
  470. .disable_auto_blink = rts5261_disable_auto_blink,
  471. .card_power_on = rts5261_card_power_on,
  472. .card_power_off = rts5261_card_power_off,
  473. .switch_output_voltage = rts5261_switch_output_voltage,
  474. .force_power_down = rts5261_force_power_down,
  475. .stop_cmd = rts5261_stop_cmd,
  476. .set_aspm = rts5261_set_aspm,
  477. .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
  478. .enable_ocp = rts5261_enable_ocp,
  479. .disable_ocp = rts5261_disable_ocp,
  480. .init_ocp = rts5261_init_ocp,
  481. .process_ocp = rts5261_process_ocp,
  482. .clear_ocpstat = rts5261_clear_ocpstat,
  483. };
  484. static inline u8 double_ssc_depth(u8 depth)
  485. {
  486. return ((depth > 1) ? (depth - 1) : depth);
  487. }
  488. int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  489. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  490. {
  491. int err, clk;
  492. u16 n;
  493. u8 clk_divider, mcu_cnt, div;
  494. static const u8 depth[] = {
  495. [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
  496. [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
  497. [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
  498. [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
  499. };
  500. if (initial_mode) {
  501. /* We use 250k(around) here, in initial stage */
  502. if (is_version(pcr, PID_5261, IC_VER_D)) {
  503. clk_divider = SD_CLK_DIVIDE_256;
  504. card_clock = 60000000;
  505. } else {
  506. clk_divider = SD_CLK_DIVIDE_128;
  507. card_clock = 30000000;
  508. }
  509. } else {
  510. clk_divider = SD_CLK_DIVIDE_0;
  511. }
  512. err = rtsx_pci_write_register(pcr, SD_CFG1,
  513. SD_CLK_DIVIDE_MASK, clk_divider);
  514. if (err < 0)
  515. return err;
  516. card_clock /= 1000000;
  517. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  518. clk = card_clock;
  519. if (!initial_mode && double_clk)
  520. clk = card_clock * 2;
  521. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  522. clk, pcr->cur_clock);
  523. if (clk == pcr->cur_clock)
  524. return 0;
  525. if (pcr->ops->conv_clk_and_div_n)
  526. n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  527. else
  528. n = clk - 4;
  529. if ((clk <= 4) || (n > 396))
  530. return -EINVAL;
  531. mcu_cnt = 125/clk + 3;
  532. if (mcu_cnt > 15)
  533. mcu_cnt = 15;
  534. div = CLK_DIV_1;
  535. while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
  536. if (pcr->ops->conv_clk_and_div_n) {
  537. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  538. DIV_N_TO_CLK) * 2;
  539. n = pcr->ops->conv_clk_and_div_n(dbl_clk,
  540. CLK_TO_DIV_N);
  541. } else {
  542. n = (n + 4) * 2 - 4;
  543. }
  544. div++;
  545. }
  546. n = (n / 2);
  547. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  548. ssc_depth = depth[ssc_depth];
  549. if (double_clk)
  550. ssc_depth = double_ssc_depth(ssc_depth);
  551. if (ssc_depth) {
  552. if (div == CLK_DIV_2) {
  553. if (ssc_depth > 1)
  554. ssc_depth -= 1;
  555. else
  556. ssc_depth = RTS5261_SSC_DEPTH_8M;
  557. } else if (div == CLK_DIV_4) {
  558. if (ssc_depth > 2)
  559. ssc_depth -= 2;
  560. else
  561. ssc_depth = RTS5261_SSC_DEPTH_8M;
  562. } else if (div == CLK_DIV_8) {
  563. if (ssc_depth > 3)
  564. ssc_depth -= 3;
  565. else
  566. ssc_depth = RTS5261_SSC_DEPTH_8M;
  567. }
  568. } else {
  569. ssc_depth = 0;
  570. }
  571. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  572. rtsx_pci_init_cmd(pcr);
  573. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  574. CLK_LOW_FREQ, CLK_LOW_FREQ);
  575. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  576. 0xFF, (div << 4) | mcu_cnt);
  577. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  578. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  579. SSC_DEPTH_MASK, ssc_depth);
  580. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  581. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  582. if (vpclk) {
  583. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  584. PHASE_NOT_RESET, 0);
  585. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  586. PHASE_NOT_RESET, 0);
  587. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  588. PHASE_NOT_RESET, PHASE_NOT_RESET);
  589. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  590. PHASE_NOT_RESET, PHASE_NOT_RESET);
  591. }
  592. err = rtsx_pci_send_cmd(pcr, 2000);
  593. if (err < 0)
  594. return err;
  595. /* Wait SSC clock stable */
  596. udelay(SSC_CLOCK_STABLE_WAIT);
  597. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  598. if (err < 0)
  599. return err;
  600. pcr->cur_clock = clk;
  601. return 0;
  602. }
  603. void rts5261_init_params(struct rtsx_pcr *pcr)
  604. {
  605. struct rtsx_cr_option *option = &pcr->option;
  606. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  607. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  608. pcr->num_slots = 1;
  609. pcr->ops = &rts5261_pcr_ops;
  610. pcr->flags = 0;
  611. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  612. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  613. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  614. pcr->aspm_en = ASPM_L1_EN;
  615. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
  616. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  617. pcr->ic_version = rts5261_get_ic_version(pcr);
  618. pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
  619. pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
  620. pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
  621. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  622. | LTR_L1SS_PWR_GATE_EN);
  623. option->ltr_en = true;
  624. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  625. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  626. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  627. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  628. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  629. option->ltr_l1off_sspwrgate = 0x7F;
  630. option->ltr_l1off_snooze_sspwrgate = 0x78;
  631. option->ocp_en = 1;
  632. hw_param->interrupt_en |= SD_OC_INT_EN;
  633. hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
  634. option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
  635. }