rts5260.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Steven FENG <steven_feng@realsil.com.cn>
  8. * Rui FENG <rui_feng@realsil.com.cn>
  9. * Wei WANG <wei_wang@realsil.com.cn>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/delay.h>
  13. #include <linux/rtsx_pci.h>
  14. #include "rts5260.h"
  15. #include "rtsx_pcr.h"
  16. static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
  17. {
  18. u8 val;
  19. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  20. return val & IC_VERSION_MASK;
  21. }
  22. static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  23. {
  24. u8 driving_3v3[4][3] = {
  25. {0x11, 0x11, 0x11},
  26. {0x22, 0x22, 0x22},
  27. {0x55, 0x55, 0x55},
  28. {0x33, 0x33, 0x33},
  29. };
  30. u8 driving_1v8[4][3] = {
  31. {0x35, 0x33, 0x33},
  32. {0x8A, 0x88, 0x88},
  33. {0xBD, 0xBB, 0xBB},
  34. {0x9B, 0x99, 0x99},
  35. };
  36. u8 (*driving)[3], drive_sel;
  37. if (voltage == OUTPUT_3V3) {
  38. driving = driving_3v3;
  39. drive_sel = pcr->sd30_drive_sel_3v3;
  40. } else {
  41. driving = driving_1v8;
  42. drive_sel = pcr->sd30_drive_sel_1v8;
  43. }
  44. rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  45. 0xFF, driving[drive_sel][0]);
  46. rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  47. 0xFF, driving[drive_sel][1]);
  48. rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  49. 0xFF, driving[drive_sel][2]);
  50. }
  51. static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  52. {
  53. struct pci_dev *pdev = pcr->pci;
  54. u32 reg;
  55. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  56. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  57. if (!rtsx_vendor_setting_valid(reg)) {
  58. pcr_dbg(pcr, "skip fetch vendor setting\n");
  59. return;
  60. }
  61. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  62. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  63. pcr->card_drive_sel &= 0x3F;
  64. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  65. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  66. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  67. if (rtsx_check_mmc_support(reg))
  68. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  69. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  70. if (rtsx_reg_check_reverse_socket(reg))
  71. pcr->flags |= PCR_REVERSE_SOCKET;
  72. }
  73. static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
  74. {
  75. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  76. LED_SHINE_MASK, LED_SHINE_EN);
  77. }
  78. static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
  79. {
  80. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  81. LED_SHINE_MASK, LED_SHINE_DISABLE);
  82. }
  83. static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
  84. {
  85. return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
  86. RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_ON);
  87. }
  88. static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
  89. {
  90. return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
  91. RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_OFF);
  92. }
  93. /* SD Pull Control Enable:
  94. * SD_DAT[3:0] ==> pull up
  95. * SD_CD ==> pull up
  96. * SD_WP ==> pull up
  97. * SD_CMD ==> pull up
  98. * SD_CLK ==> pull down
  99. */
  100. static const u32 rts5260_sd_pull_ctl_enable_tbl[] = {
  101. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  102. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  103. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  104. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  105. 0,
  106. };
  107. /* SD Pull Control Disable:
  108. * SD_DAT[3:0] ==> pull down
  109. * SD_CD ==> pull up
  110. * SD_WP ==> pull down
  111. * SD_CMD ==> pull down
  112. * SD_CLK ==> pull down
  113. */
  114. static const u32 rts5260_sd_pull_ctl_disable_tbl[] = {
  115. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  116. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  117. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  118. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  119. 0,
  120. };
  121. /* MS Pull Control Enable:
  122. * MS CD ==> pull up
  123. * others ==> pull down
  124. */
  125. static const u32 rts5260_ms_pull_ctl_enable_tbl[] = {
  126. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  127. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  128. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  129. 0,
  130. };
  131. /* MS Pull Control Disable:
  132. * MS CD ==> pull up
  133. * others ==> pull down
  134. */
  135. static const u32 rts5260_ms_pull_ctl_disable_tbl[] = {
  136. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  137. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  138. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  139. 0,
  140. };
  141. static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
  142. {
  143. rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
  144. | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
  145. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
  146. rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
  147. CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
  148. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  149. return 0;
  150. }
  151. static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
  152. {
  153. struct rtsx_cr_option *option = &pcr->option;
  154. if (option->ocp_en)
  155. rtsx_pci_enable_ocp(pcr);
  156. rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
  157. rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
  158. RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
  159. rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
  160. LDO_POW_SDVDD1_ON);
  161. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  162. DV331812_POWERON, DV331812_POWERON);
  163. msleep(20);
  164. if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
  165. pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
  166. sd_set_sample_push_timing_sd30(pcr);
  167. /* Initialize SD_CFG1 register */
  168. rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
  169. SD_CLK_DIVIDE_128 | SD_20_MODE);
  170. rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
  171. 0xFF, SD20_RX_POS_EDGE);
  172. rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
  173. rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
  174. SD_STOP | SD_CLR_ERR);
  175. /* Reset SD_CFG3 register */
  176. rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
  177. rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
  178. SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
  179. SD30_CLK_STOP_CFG0, 0);
  180. rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
  181. return 0;
  182. }
  183. static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  184. {
  185. switch (voltage) {
  186. case OUTPUT_3V3:
  187. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  188. DV331812_VDD1, DV331812_VDD1);
  189. rtsx_pci_write_register(pcr, LDO_DV18_CFG,
  190. DV331812_MASK, DV331812_33);
  191. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
  192. break;
  193. case OUTPUT_1V8:
  194. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  195. DV331812_VDD1, DV331812_VDD1);
  196. rtsx_pci_write_register(pcr, LDO_DV18_CFG,
  197. DV331812_MASK, DV331812_17);
  198. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
  199. SD_IO_USING_1V8);
  200. break;
  201. default:
  202. return -EINVAL;
  203. }
  204. /* set pad drive */
  205. rts5260_fill_driving(pcr, voltage);
  206. return 0;
  207. }
  208. static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
  209. {
  210. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  211. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  212. rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
  213. RTS5260_DMA_RST | RTS5260_ADMA3_RST,
  214. RTS5260_DMA_RST | RTS5260_ADMA3_RST);
  215. rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
  216. }
  217. static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
  218. {
  219. rts5260_stop_cmd(pcr);
  220. rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
  221. }
  222. static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
  223. {
  224. int err = 0;
  225. rts5260_card_before_power_off(pcr);
  226. err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
  227. LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
  228. err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
  229. DV331812_POWERON, DV331812_POWEROFF);
  230. if (pcr->option.ocp_en)
  231. rtsx_pci_disable_ocp(pcr);
  232. return err;
  233. }
  234. static void rts5260_init_ocp(struct rtsx_pcr *pcr)
  235. {
  236. struct rtsx_cr_option *option = &pcr->option;
  237. if (option->ocp_en) {
  238. u8 mask, val;
  239. rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
  240. RTS5260_DVCC_OCP_THD_MASK,
  241. option->sd_800mA_ocp_thd);
  242. rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
  243. RTS5260_DV331812_OCP_THD_MASK,
  244. RTS5260_DV331812_OCP_THD_270);
  245. mask = SD_OCP_GLITCH_MASK;
  246. val = pcr->hw_param.ocp_glitch;
  247. rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
  248. rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
  249. RTS5260_DVCC_OCP_EN |
  250. RTS5260_DVCC_OCP_CL_EN,
  251. RTS5260_DVCC_OCP_EN |
  252. RTS5260_DVCC_OCP_CL_EN);
  253. rtsx_pci_enable_ocp(pcr);
  254. } else {
  255. rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
  256. RTS5260_DVCC_OCP_EN |
  257. RTS5260_DVCC_OCP_CL_EN, 0);
  258. }
  259. }
  260. static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
  261. {
  262. u8 val = 0;
  263. val = SD_OCP_INT_EN | SD_DETECT_EN;
  264. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  265. }
  266. static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
  267. {
  268. u8 mask = 0;
  269. mask = SD_OCP_INT_EN | SD_DETECT_EN;
  270. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  271. }
  272. static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
  273. {
  274. return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
  275. }
  276. static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
  277. {
  278. return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
  279. }
  280. static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
  281. {
  282. u8 mask = 0;
  283. u8 val = 0;
  284. mask = SD_OCP_INT_CLR | SD_OC_CLR;
  285. val = SD_OCP_INT_CLR | SD_OC_CLR;
  286. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  287. rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
  288. DV3318_OCP_INT_CLR | DV3318_OCP_CLR,
  289. DV3318_OCP_INT_CLR | DV3318_OCP_CLR);
  290. udelay(10);
  291. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  292. rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
  293. DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);
  294. }
  295. static void rts5260_process_ocp(struct rtsx_pcr *pcr)
  296. {
  297. if (!pcr->option.ocp_en)
  298. return;
  299. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  300. rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
  301. if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
  302. (pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
  303. rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
  304. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  305. rtsx_pci_clear_ocpstat(pcr);
  306. pcr->ocp_stat = 0;
  307. pcr->ocp_stat2 = 0;
  308. }
  309. }
  310. static int rts5260_init_hw(struct rtsx_pcr *pcr)
  311. {
  312. int err;
  313. rtsx_pci_init_cmd(pcr);
  314. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
  315. AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
  316. /* Rest L1SUB Config */
  317. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
  318. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
  319. CLK_PM_EN, CLK_PM_EN);
  320. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
  321. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  322. PWR_GATE_EN, PWR_GATE_EN);
  323. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
  324. PWD_SUSPND_EN, PWD_SUSPND_EN);
  325. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
  326. U_AUTO_DMA_EN_MASK, U_AUTO_DMA_DISABLE);
  327. if (pcr->flags & PCR_REVERSE_SOCKET)
  328. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
  329. else
  330. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
  331. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
  332. OBFF_EN_MASK, OBFF_DISABLE);
  333. err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
  334. if (err < 0)
  335. return err;
  336. rtsx_pci_init_ocp(pcr);
  337. return 0;
  338. }
  339. static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
  340. {
  341. int lss_l1_1, lss_l1_2;
  342. lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
  343. | rtsx_check_dev_flag(pcr, PM_L1_1_EN);
  344. lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
  345. | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
  346. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
  347. if (lss_l1_2) {
  348. pcr_dbg(pcr, "Set parameters for L1.2.");
  349. rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
  350. 0xFF, PCIE_L1_2_EN);
  351. rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
  352. RTS5260_DVCC_OCP_EN |
  353. RTS5260_DVCC_OCP_CL_EN,
  354. RTS5260_DVCC_OCP_EN |
  355. RTS5260_DVCC_OCP_CL_EN);
  356. rtsx_pci_write_register(pcr, PWR_FE_CTL,
  357. 0xFF, PCIE_L1_2_PD_FE_EN);
  358. } else if (lss_l1_1) {
  359. pcr_dbg(pcr, "Set parameters for L1.1.");
  360. rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
  361. 0xFF, PCIE_L1_1_EN);
  362. rtsx_pci_write_register(pcr, PWR_FE_CTL,
  363. 0xFF, PCIE_L1_1_PD_FE_EN);
  364. } else {
  365. pcr_dbg(pcr, "Set parameters for L1.");
  366. rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
  367. 0xFF, PCIE_L1_0_EN);
  368. rtsx_pci_write_register(pcr, PWR_FE_CTL,
  369. 0xFF, PCIE_L1_0_PD_FE_EN);
  370. }
  371. rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
  372. 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
  373. rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
  374. 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
  375. rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
  376. 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
  377. rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
  378. 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
  379. rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
  380. 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
  381. /*Option cut APHY*/
  382. rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
  383. 0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);
  384. rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
  385. 0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);
  386. rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
  387. 0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);
  388. rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
  389. 0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);
  390. /*CDR DEC*/
  391. rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
  392. /*PWMPFM*/
  393. rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
  394. 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
  395. /*No Power Saving WA*/
  396. rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
  397. 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
  398. }
  399. static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
  400. {
  401. struct pci_dev *pdev = pcr->pci;
  402. int l1ss;
  403. struct rtsx_cr_option *option = &pcr->option;
  404. u32 lval;
  405. l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  406. if (!l1ss)
  407. return;
  408. pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  409. if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
  410. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  411. if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
  412. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  413. if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
  414. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  415. if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
  416. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  417. rts5260_pwr_saving_setting(pcr);
  418. if (option->ltr_en) {
  419. u16 val;
  420. pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
  421. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  422. option->ltr_enabled = true;
  423. option->ltr_active = true;
  424. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  425. } else {
  426. option->ltr_enabled = false;
  427. }
  428. }
  429. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  430. | PM_L1_1_EN | PM_L1_2_EN))
  431. option->force_clkreq_0 = false;
  432. else
  433. option->force_clkreq_0 = true;
  434. }
  435. static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
  436. {
  437. struct rtsx_cr_option *option = &pcr->option;
  438. /* Set mcu_cnt to 7 to ensure data can be sampled properly */
  439. rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
  440. rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
  441. rts5260_init_from_cfg(pcr);
  442. /* force no MDIO*/
  443. rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
  444. 0xFF, RTS5260_MIMO_DISABLE);
  445. /*Modify SDVCC Tune Default Parameters!*/
  446. rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
  447. RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
  448. rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
  449. rts5260_init_hw(pcr);
  450. /*
  451. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  452. * to drive low, and we forcibly request clock.
  453. */
  454. if (option->force_clkreq_0)
  455. rtsx_pci_write_register(pcr, PETXCFG,
  456. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  457. else
  458. rtsx_pci_write_register(pcr, PETXCFG,
  459. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  460. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
  461. return 0;
  462. }
  463. static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  464. {
  465. struct rtsx_cr_option *option = &pcr->option;
  466. u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
  467. int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
  468. int aspm_L1_1, aspm_L1_2;
  469. u8 val = 0;
  470. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  471. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  472. if (active) {
  473. /* run, latency: 60us */
  474. if (aspm_L1_1)
  475. val = option->ltr_l1off_snooze_sspwrgate;
  476. } else {
  477. /* l1off, latency: 300us */
  478. if (aspm_L1_2)
  479. val = option->ltr_l1off_sspwrgate;
  480. }
  481. if (aspm_L1_1 || aspm_L1_2) {
  482. if (rtsx_check_dev_flag(pcr,
  483. LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
  484. if (card_exist)
  485. val &= ~L1OFF_MBIAS2_EN_5250;
  486. else
  487. val |= L1OFF_MBIAS2_EN_5250;
  488. }
  489. }
  490. rtsx_set_l1off_sub(pcr, val);
  491. }
  492. static const struct pcr_ops rts5260_pcr_ops = {
  493. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  494. .turn_on_led = rts5260_turn_on_led,
  495. .turn_off_led = rts5260_turn_off_led,
  496. .extra_init_hw = rts5260_extra_init_hw,
  497. .enable_auto_blink = rtsx_base_enable_auto_blink,
  498. .disable_auto_blink = rtsx_base_disable_auto_blink,
  499. .card_power_on = rts5260_card_power_on,
  500. .card_power_off = rts5260_card_power_off,
  501. .switch_output_voltage = rts5260_switch_output_voltage,
  502. .stop_cmd = rts5260_stop_cmd,
  503. .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
  504. .enable_ocp = rts5260_enable_ocp,
  505. .disable_ocp = rts5260_disable_ocp,
  506. .init_ocp = rts5260_init_ocp,
  507. .process_ocp = rts5260_process_ocp,
  508. .get_ocpstat = rts5260_get_ocpstat,
  509. .clear_ocpstat = rts5260_clear_ocpstat,
  510. };
  511. void rts5260_init_params(struct rtsx_pcr *pcr)
  512. {
  513. struct rtsx_cr_option *option = &pcr->option;
  514. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  515. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  516. pcr->num_slots = 2;
  517. pcr->flags = 0;
  518. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  519. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  520. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  521. pcr->aspm_en = ASPM_L1_EN;
  522. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
  523. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  524. pcr->ic_version = rts5260_get_ic_version(pcr);
  525. pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
  526. pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
  527. pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
  528. pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
  529. pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
  530. pcr->ops = &rts5260_pcr_ops;
  531. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  532. | LTR_L1SS_PWR_GATE_EN);
  533. option->ltr_en = true;
  534. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  535. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  536. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  537. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  538. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  539. option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
  540. option->ltr_l1off_snooze_sspwrgate =
  541. LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
  542. option->ocp_en = 1;
  543. if (option->ocp_en)
  544. hw_param->interrupt_en |= SD_OC_INT_EN;
  545. hw_param->ocp_glitch = SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
  546. option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
  547. option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
  548. }