rts5249.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/rtsx_pci.h>
  12. #include "rtsx_pcr.h"
  13. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  14. {
  15. u8 val;
  16. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  17. return val & 0x0F;
  18. }
  19. static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  20. {
  21. u8 driving_3v3[4][3] = {
  22. {0x11, 0x11, 0x18},
  23. {0x55, 0x55, 0x5C},
  24. {0xFF, 0xFF, 0xFF},
  25. {0x96, 0x96, 0x96},
  26. };
  27. u8 driving_1v8[4][3] = {
  28. {0xC4, 0xC4, 0xC4},
  29. {0x3C, 0x3C, 0x3C},
  30. {0xFE, 0xFE, 0xFE},
  31. {0xB3, 0xB3, 0xB3},
  32. };
  33. u8 (*driving)[3], drive_sel;
  34. if (voltage == OUTPUT_3V3) {
  35. driving = driving_3v3;
  36. drive_sel = pcr->sd30_drive_sel_3v3;
  37. } else {
  38. driving = driving_1v8;
  39. drive_sel = pcr->sd30_drive_sel_1v8;
  40. }
  41. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  42. 0xFF, driving[drive_sel][0]);
  43. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  44. 0xFF, driving[drive_sel][1]);
  45. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  46. 0xFF, driving[drive_sel][2]);
  47. }
  48. static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  49. {
  50. struct pci_dev *pdev = pcr->pci;
  51. u32 reg;
  52. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  53. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  54. if (!rtsx_vendor_setting_valid(reg)) {
  55. pcr_dbg(pcr, "skip fetch vendor setting\n");
  56. return;
  57. }
  58. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  59. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  60. pcr->card_drive_sel &= 0x3F;
  61. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  62. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  63. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  64. if (rtsx_check_mmc_support(reg))
  65. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  66. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  67. if (rtsx_reg_check_reverse_socket(reg))
  68. pcr->flags |= PCR_REVERSE_SOCKET;
  69. }
  70. static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  71. {
  72. struct pci_dev *pdev = pcr->pci;
  73. int l1ss;
  74. struct rtsx_cr_option *option = &(pcr->option);
  75. u32 lval;
  76. l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  77. if (!l1ss)
  78. return;
  79. pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  80. if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
  81. if (0 == (lval & 0x0F))
  82. rtsx_pci_enable_oobs_polling(pcr);
  83. else
  84. rtsx_pci_disable_oobs_polling(pcr);
  85. }
  86. if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
  87. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  88. if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
  89. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  90. if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
  91. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  92. if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
  93. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  94. if (option->ltr_en) {
  95. u16 val;
  96. pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
  97. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  98. option->ltr_enabled = true;
  99. option->ltr_active = true;
  100. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  101. } else {
  102. option->ltr_enabled = false;
  103. }
  104. }
  105. }
  106. static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
  107. {
  108. struct rtsx_cr_option *option = &(pcr->option);
  109. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  110. | PM_L1_1_EN | PM_L1_2_EN))
  111. option->force_clkreq_0 = false;
  112. else
  113. option->force_clkreq_0 = true;
  114. return 0;
  115. }
  116. static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
  117. {
  118. u8 cnt, sv;
  119. u16 j = 0;
  120. u8 tmp;
  121. u8 val;
  122. int i;
  123. rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
  124. REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
  125. udelay(1);
  126. pcr_dbg(pcr, "Enable efuse por!");
  127. pcr_dbg(pcr, "save efuse to autoload");
  128. rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
  129. rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
  130. REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
  131. /* Wait transfer end */
  132. for (j = 0; j < 1024; j++) {
  133. rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
  134. if ((tmp & 0x80) == 0)
  135. break;
  136. }
  137. rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
  138. cnt = val & 0x0F;
  139. sv = val & 0x10;
  140. if (sv) {
  141. for (i = 0; i < 4; i++) {
  142. rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
  143. REG_EFUSE_ADD_MASK, 0x04 + i);
  144. rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
  145. REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
  146. /* Wait transfer end */
  147. for (j = 0; j < 1024; j++) {
  148. rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
  149. if ((tmp & 0x80) == 0)
  150. break;
  151. }
  152. rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
  153. rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
  154. }
  155. } else {
  156. rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
  157. rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
  158. rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
  159. rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
  160. }
  161. for (i = 0; i < cnt * 4; i++) {
  162. if (sv)
  163. rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
  164. REG_EFUSE_ADD_MASK, 0x08 + i);
  165. else
  166. rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
  167. REG_EFUSE_ADD_MASK, 0x04 + i);
  168. rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
  169. REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
  170. /* Wait transfer end */
  171. for (j = 0; j < 1024; j++) {
  172. rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
  173. if ((tmp & 0x80) == 0)
  174. break;
  175. }
  176. rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
  177. rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
  178. }
  179. rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
  180. rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
  181. REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
  182. pcr_dbg(pcr, "Disable efuse por!");
  183. }
  184. static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
  185. {
  186. u8 val;
  187. rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
  188. if (val & 0x02) {
  189. rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
  190. if (val & RTS525A_LOAD_BIOS_FLAG) {
  191. rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
  192. RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
  193. rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
  194. REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
  195. pcr_dbg(pcr, "Power ON efuse!");
  196. mdelay(1);
  197. rts52xa_save_content_from_efuse(pcr);
  198. } else {
  199. rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
  200. if (!(val & 0x08))
  201. rts52xa_save_content_from_efuse(pcr);
  202. }
  203. } else {
  204. pcr_dbg(pcr, "Load from autoload");
  205. rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
  206. rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
  207. rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
  208. rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
  209. rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
  210. }
  211. }
  212. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  213. {
  214. struct rtsx_cr_option *option = &(pcr->option);
  215. rts5249_init_from_cfg(pcr);
  216. rts5249_init_from_hw(pcr);
  217. rtsx_pci_init_cmd(pcr);
  218. if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
  219. rts52xa_save_content_to_autoload_space(pcr);
  220. /* Rest L1SUB Config */
  221. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
  222. /* Configure GPIO as output */
  223. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  224. /* Reset ASPM state to default value */
  225. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  226. /* Switch LDO3318 source from DV33 to card_3v3 */
  227. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  228. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  229. /* LED shine disabled, set initial shine cycle period */
  230. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  231. /* Configure driving */
  232. rts5249_fill_driving(pcr, OUTPUT_3V3);
  233. if (pcr->flags & PCR_REVERSE_SOCKET)
  234. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
  235. else
  236. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
  237. rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
  238. if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
  239. rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
  240. rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
  241. rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
  242. } else {
  243. rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
  244. rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
  245. }
  246. /*
  247. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  248. * to drive low, and we forcibly request clock.
  249. */
  250. if (option->force_clkreq_0)
  251. rtsx_pci_write_register(pcr, PETXCFG,
  252. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  253. else
  254. rtsx_pci_write_register(pcr, PETXCFG,
  255. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  256. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
  257. if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
  258. rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
  259. REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
  260. pcr_dbg(pcr, "Power OFF efuse!");
  261. }
  262. return 0;
  263. }
  264. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  265. {
  266. int err;
  267. err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
  268. if (err < 0)
  269. return err;
  270. err = rtsx_pci_write_phy_register(pcr, PHY_REV,
  271. PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
  272. PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
  273. PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
  274. PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
  275. PHY_REV_STOP_CLKWR);
  276. if (err < 0)
  277. return err;
  278. msleep(1);
  279. err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
  280. PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
  281. PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
  282. if (err < 0)
  283. return err;
  284. err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
  285. PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
  286. PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
  287. PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
  288. if (err < 0)
  289. return err;
  290. err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
  291. PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
  292. PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
  293. PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
  294. if (err < 0)
  295. return err;
  296. err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
  297. PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
  298. PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
  299. PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
  300. PHY_FLD4_BER_CHK_EN);
  301. if (err < 0)
  302. return err;
  303. err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
  304. PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
  305. if (err < 0)
  306. return err;
  307. err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
  308. PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
  309. if (err < 0)
  310. return err;
  311. err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
  312. PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
  313. PHY_FLD3_RXDELINK);
  314. if (err < 0)
  315. return err;
  316. return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
  317. PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
  318. PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
  319. PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
  320. }
  321. static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
  322. {
  323. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  324. }
  325. static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
  326. {
  327. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  328. }
  329. static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
  330. {
  331. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  332. }
  333. static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
  334. {
  335. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  336. }
  337. static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
  338. {
  339. int err;
  340. struct rtsx_cr_option *option = &pcr->option;
  341. if (option->ocp_en)
  342. rtsx_pci_enable_ocp(pcr);
  343. rtsx_pci_init_cmd(pcr);
  344. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  345. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  346. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  347. LDO3318_PWR_MASK, 0x02);
  348. err = rtsx_pci_send_cmd(pcr, 100);
  349. if (err < 0)
  350. return err;
  351. msleep(5);
  352. rtsx_pci_init_cmd(pcr);
  353. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  354. SD_POWER_MASK, SD_VCC_POWER_ON);
  355. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  356. LDO3318_PWR_MASK, 0x06);
  357. return rtsx_pci_send_cmd(pcr, 100);
  358. }
  359. static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
  360. {
  361. struct rtsx_cr_option *option = &pcr->option;
  362. if (option->ocp_en)
  363. rtsx_pci_disable_ocp(pcr);
  364. rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
  365. rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
  366. return 0;
  367. }
  368. static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  369. {
  370. int err;
  371. u16 append;
  372. switch (voltage) {
  373. case OUTPUT_3V3:
  374. err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
  375. PHY_TUNE_VOLTAGE_3V3);
  376. if (err < 0)
  377. return err;
  378. break;
  379. case OUTPUT_1V8:
  380. append = PHY_TUNE_D18_1V8;
  381. if (CHK_PCI_PID(pcr, 0x5249)) {
  382. err = rtsx_pci_update_phy(pcr, PHY_BACR,
  383. PHY_BACR_BASIC_MASK, 0);
  384. if (err < 0)
  385. return err;
  386. append = PHY_TUNE_D18_1V7;
  387. }
  388. err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
  389. append);
  390. if (err < 0)
  391. return err;
  392. break;
  393. default:
  394. pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
  395. return -EINVAL;
  396. }
  397. /* set pad drive */
  398. rtsx_pci_init_cmd(pcr);
  399. rts5249_fill_driving(pcr, voltage);
  400. return rtsx_pci_send_cmd(pcr, 100);
  401. }
  402. static const struct pcr_ops rts5249_pcr_ops = {
  403. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  404. .extra_init_hw = rts5249_extra_init_hw,
  405. .optimize_phy = rts5249_optimize_phy,
  406. .turn_on_led = rtsx_base_turn_on_led,
  407. .turn_off_led = rtsx_base_turn_off_led,
  408. .enable_auto_blink = rtsx_base_enable_auto_blink,
  409. .disable_auto_blink = rtsx_base_disable_auto_blink,
  410. .card_power_on = rtsx_base_card_power_on,
  411. .card_power_off = rtsx_base_card_power_off,
  412. .switch_output_voltage = rtsx_base_switch_output_voltage,
  413. };
  414. /* SD Pull Control Enable:
  415. * SD_DAT[3:0] ==> pull up
  416. * SD_CD ==> pull up
  417. * SD_WP ==> pull up
  418. * SD_CMD ==> pull up
  419. * SD_CLK ==> pull down
  420. */
  421. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  422. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  423. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  424. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  425. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  426. 0,
  427. };
  428. /* SD Pull Control Disable:
  429. * SD_DAT[3:0] ==> pull down
  430. * SD_CD ==> pull up
  431. * SD_WP ==> pull down
  432. * SD_CMD ==> pull down
  433. * SD_CLK ==> pull down
  434. */
  435. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  436. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  437. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  438. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  439. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  440. 0,
  441. };
  442. /* MS Pull Control Enable:
  443. * MS CD ==> pull up
  444. * others ==> pull down
  445. */
  446. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  447. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  448. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  449. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  450. 0,
  451. };
  452. /* MS Pull Control Disable:
  453. * MS CD ==> pull up
  454. * others ==> pull down
  455. */
  456. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  457. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  458. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  459. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  460. 0,
  461. };
  462. void rts5249_init_params(struct rtsx_pcr *pcr)
  463. {
  464. struct rtsx_cr_option *option = &(pcr->option);
  465. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  466. pcr->num_slots = 2;
  467. pcr->ops = &rts5249_pcr_ops;
  468. pcr->flags = 0;
  469. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  470. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  471. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  472. pcr->aspm_en = ASPM_L1_EN;
  473. pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
  474. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  475. pcr->ic_version = rts5249_get_ic_version(pcr);
  476. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  477. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  478. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  479. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  480. pcr->reg_pm_ctrl3 = PM_CTRL3;
  481. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  482. | LTR_L1SS_PWR_GATE_EN);
  483. option->ltr_en = true;
  484. /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  485. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  486. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  487. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  488. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  489. option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
  490. option->ltr_l1off_snooze_sspwrgate =
  491. LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
  492. }
  493. static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
  494. {
  495. addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
  496. return __rtsx_pci_write_phy_register(pcr, addr, val);
  497. }
  498. static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  499. {
  500. addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
  501. return __rtsx_pci_read_phy_register(pcr, addr, val);
  502. }
  503. static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
  504. {
  505. int err;
  506. err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
  507. D3_DELINK_MODE_EN, 0x00);
  508. if (err < 0)
  509. return err;
  510. rtsx_pci_write_phy_register(pcr, PHY_PCR,
  511. PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
  512. PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
  513. rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
  514. PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
  515. if (is_version(pcr, 0x524A, IC_VER_A)) {
  516. rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
  517. PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
  518. rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
  519. PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
  520. PHY_SSCCR2_TIME2_WIDTH);
  521. rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
  522. PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
  523. PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
  524. rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
  525. PHY_ANA1D_DEBUG_ADDR);
  526. rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
  527. PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
  528. PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
  529. PHY_DIG1E_RCLK_TX_EN_KEEP |
  530. PHY_DIG1E_RCLK_TX_TERM_KEEP |
  531. PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
  532. PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
  533. PHY_DIG1E_RX_EN_KEEP);
  534. }
  535. rtsx_pci_write_phy_register(pcr, PHY_ANA08,
  536. PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
  537. PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
  538. return 0;
  539. }
  540. static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
  541. {
  542. rts5249_extra_init_hw(pcr);
  543. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  544. FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
  545. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  546. rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
  547. LDO_VCC_LMT_EN);
  548. rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
  549. if (is_version(pcr, 0x524A, IC_VER_A)) {
  550. rtsx_pci_write_register(pcr, LDO_DV18_CFG,
  551. LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
  552. rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
  553. LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
  554. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  555. LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
  556. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  557. LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
  558. rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
  559. LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
  560. rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
  561. SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
  562. }
  563. return 0;
  564. }
  565. static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  566. {
  567. struct rtsx_cr_option *option = &(pcr->option);
  568. u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
  569. int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
  570. int aspm_L1_1, aspm_L1_2;
  571. u8 val = 0;
  572. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  573. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  574. if (active) {
  575. /* Run, latency: 60us */
  576. if (aspm_L1_1)
  577. val = option->ltr_l1off_snooze_sspwrgate;
  578. } else {
  579. /* L1off, latency: 300us */
  580. if (aspm_L1_2)
  581. val = option->ltr_l1off_sspwrgate;
  582. }
  583. if (aspm_L1_1 || aspm_L1_2) {
  584. if (rtsx_check_dev_flag(pcr,
  585. LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
  586. if (card_exist)
  587. val &= ~L1OFF_MBIAS2_EN_5250;
  588. else
  589. val |= L1OFF_MBIAS2_EN_5250;
  590. }
  591. }
  592. rtsx_set_l1off_sub(pcr, val);
  593. }
  594. static const struct pcr_ops rts524a_pcr_ops = {
  595. .write_phy = rts524a_write_phy,
  596. .read_phy = rts524a_read_phy,
  597. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  598. .extra_init_hw = rts524a_extra_init_hw,
  599. .optimize_phy = rts524a_optimize_phy,
  600. .turn_on_led = rtsx_base_turn_on_led,
  601. .turn_off_led = rtsx_base_turn_off_led,
  602. .enable_auto_blink = rtsx_base_enable_auto_blink,
  603. .disable_auto_blink = rtsx_base_disable_auto_blink,
  604. .card_power_on = rtsx_base_card_power_on,
  605. .card_power_off = rtsx_base_card_power_off,
  606. .switch_output_voltage = rtsx_base_switch_output_voltage,
  607. .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
  608. };
  609. void rts524a_init_params(struct rtsx_pcr *pcr)
  610. {
  611. rts5249_init_params(pcr);
  612. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
  613. pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
  614. pcr->option.ltr_l1off_snooze_sspwrgate =
  615. LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
  616. pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
  617. pcr->ops = &rts524a_pcr_ops;
  618. pcr->option.ocp_en = 1;
  619. if (pcr->option.ocp_en)
  620. pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
  621. pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
  622. pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
  623. }
  624. static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
  625. {
  626. rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
  627. LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
  628. return rtsx_base_card_power_on(pcr, card);
  629. }
  630. static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  631. {
  632. switch (voltage) {
  633. case OUTPUT_3V3:
  634. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  635. LDO_D3318_MASK, LDO_D3318_33V);
  636. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
  637. break;
  638. case OUTPUT_1V8:
  639. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  640. LDO_D3318_MASK, LDO_D3318_18V);
  641. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
  642. SD_IO_USING_1V8);
  643. break;
  644. default:
  645. return -EINVAL;
  646. }
  647. rtsx_pci_init_cmd(pcr);
  648. rts5249_fill_driving(pcr, voltage);
  649. return rtsx_pci_send_cmd(pcr, 100);
  650. }
  651. static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
  652. {
  653. int err;
  654. err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
  655. D3_DELINK_MODE_EN, 0x00);
  656. if (err < 0)
  657. return err;
  658. rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
  659. _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
  660. _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
  661. _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
  662. rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
  663. _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
  664. _PHY_CMU_DEBUG_EN);
  665. if (is_version(pcr, 0x525A, IC_VER_A))
  666. rtsx_pci_write_phy_register(pcr, _PHY_REV0,
  667. _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
  668. _PHY_REV0_CDR_RX_IDLE_BYPASS);
  669. return 0;
  670. }
  671. static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
  672. {
  673. rts5249_extra_init_hw(pcr);
  674. rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
  675. rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
  676. if (is_version(pcr, 0x525A, IC_VER_A)) {
  677. rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
  678. L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
  679. rtsx_pci_write_register(pcr, RREF_CFG,
  680. RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
  681. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  682. LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
  683. rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
  684. LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
  685. rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
  686. LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
  687. rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
  688. LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
  689. rtsx_pci_write_register(pcr, OOBS_CONFIG,
  690. OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
  691. }
  692. return 0;
  693. }
  694. static const struct pcr_ops rts525a_pcr_ops = {
  695. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  696. .extra_init_hw = rts525a_extra_init_hw,
  697. .optimize_phy = rts525a_optimize_phy,
  698. .turn_on_led = rtsx_base_turn_on_led,
  699. .turn_off_led = rtsx_base_turn_off_led,
  700. .enable_auto_blink = rtsx_base_enable_auto_blink,
  701. .disable_auto_blink = rtsx_base_disable_auto_blink,
  702. .card_power_on = rts525a_card_power_on,
  703. .card_power_off = rtsx_base_card_power_off,
  704. .switch_output_voltage = rts525a_switch_output_voltage,
  705. .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
  706. };
  707. void rts525a_init_params(struct rtsx_pcr *pcr)
  708. {
  709. rts5249_init_params(pcr);
  710. pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
  711. pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
  712. pcr->option.ltr_l1off_snooze_sspwrgate =
  713. LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
  714. pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
  715. pcr->ops = &rts525a_pcr_ops;
  716. pcr->option.ocp_en = 1;
  717. if (pcr->option.ocp_en)
  718. pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
  719. pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
  720. pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
  721. }