rts5229.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/rtsx_pci.h>
  12. #include "rtsx_pcr.h"
  13. static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
  14. {
  15. u8 val;
  16. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  17. return val & 0x0F;
  18. }
  19. static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
  20. {
  21. struct pci_dev *pdev = pcr->pci;
  22. u32 reg;
  23. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  24. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  25. if (!rtsx_vendor_setting_valid(reg))
  26. return;
  27. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  28. pcr->sd30_drive_sel_1v8 =
  29. map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
  30. pcr->card_drive_sel &= 0x3F;
  31. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  32. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  33. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  34. pcr->sd30_drive_sel_3v3 =
  35. map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg));
  36. }
  37. static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  38. {
  39. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  40. }
  41. static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
  42. {
  43. rtsx_pci_init_cmd(pcr);
  44. /* Configure GPIO as output */
  45. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  46. /* Reset ASPM state to default value */
  47. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  48. /* Force CLKREQ# PIN to drive 0 to request clock */
  49. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
  50. /* Switch LDO3318 source from DV33 to card_3v3 */
  51. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  52. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  53. /* LED shine disabled, set initial shine cycle period */
  54. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  55. /* Configure driving */
  56. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
  57. 0xFF, pcr->sd30_drive_sel_3v3);
  58. return rtsx_pci_send_cmd(pcr, 100);
  59. }
  60. static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
  61. {
  62. /* Optimize RX sensitivity */
  63. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  64. }
  65. static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
  66. {
  67. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  68. }
  69. static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
  70. {
  71. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  72. }
  73. static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
  74. {
  75. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  76. }
  77. static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
  78. {
  79. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  80. }
  81. static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card)
  82. {
  83. int err;
  84. rtsx_pci_init_cmd(pcr);
  85. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  86. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  87. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  88. LDO3318_PWR_MASK, 0x02);
  89. err = rtsx_pci_send_cmd(pcr, 100);
  90. if (err < 0)
  91. return err;
  92. /* To avoid too large in-rush current */
  93. udelay(150);
  94. rtsx_pci_init_cmd(pcr);
  95. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  96. SD_POWER_MASK, SD_POWER_ON);
  97. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  98. LDO3318_PWR_MASK, 0x06);
  99. return rtsx_pci_send_cmd(pcr, 100);
  100. }
  101. static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card)
  102. {
  103. rtsx_pci_init_cmd(pcr);
  104. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  105. SD_POWER_MASK | PMOS_STRG_MASK,
  106. SD_POWER_OFF | PMOS_STRG_400mA);
  107. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  108. LDO3318_PWR_MASK, 0x00);
  109. return rtsx_pci_send_cmd(pcr, 100);
  110. }
  111. static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  112. {
  113. int err;
  114. if (voltage == OUTPUT_3V3) {
  115. err = rtsx_pci_write_register(pcr,
  116. SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
  117. if (err < 0)
  118. return err;
  119. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  120. if (err < 0)
  121. return err;
  122. } else if (voltage == OUTPUT_1V8) {
  123. err = rtsx_pci_write_register(pcr,
  124. SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
  125. if (err < 0)
  126. return err;
  127. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
  128. if (err < 0)
  129. return err;
  130. } else {
  131. return -EINVAL;
  132. }
  133. return 0;
  134. }
  135. static const struct pcr_ops rts5229_pcr_ops = {
  136. .fetch_vendor_settings = rts5229_fetch_vendor_settings,
  137. .extra_init_hw = rts5229_extra_init_hw,
  138. .optimize_phy = rts5229_optimize_phy,
  139. .turn_on_led = rts5229_turn_on_led,
  140. .turn_off_led = rts5229_turn_off_led,
  141. .enable_auto_blink = rts5229_enable_auto_blink,
  142. .disable_auto_blink = rts5229_disable_auto_blink,
  143. .card_power_on = rts5229_card_power_on,
  144. .card_power_off = rts5229_card_power_off,
  145. .switch_output_voltage = rts5229_switch_output_voltage,
  146. .cd_deglitch = NULL,
  147. .conv_clk_and_div_n = NULL,
  148. .force_power_down = rts5229_force_power_down,
  149. };
  150. /* SD Pull Control Enable:
  151. * SD_DAT[3:0] ==> pull up
  152. * SD_CD ==> pull up
  153. * SD_WP ==> pull up
  154. * SD_CMD ==> pull up
  155. * SD_CLK ==> pull down
  156. */
  157. static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = {
  158. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  159. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  160. 0,
  161. };
  162. /* For RTS5229 version C */
  163. static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = {
  164. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  165. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9),
  166. 0,
  167. };
  168. /* SD Pull Control Disable:
  169. * SD_DAT[3:0] ==> pull down
  170. * SD_CD ==> pull up
  171. * SD_WP ==> pull down
  172. * SD_CMD ==> pull down
  173. * SD_CLK ==> pull down
  174. */
  175. static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = {
  176. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  177. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  178. 0,
  179. };
  180. /* For RTS5229 version C */
  181. static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = {
  182. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  183. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5),
  184. 0,
  185. };
  186. /* MS Pull Control Enable:
  187. * MS CD ==> pull up
  188. * others ==> pull down
  189. */
  190. static const u32 rts5229_ms_pull_ctl_enable_tbl[] = {
  191. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  192. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  193. 0,
  194. };
  195. /* MS Pull Control Disable:
  196. * MS CD ==> pull up
  197. * others ==> pull down
  198. */
  199. static const u32 rts5229_ms_pull_ctl_disable_tbl[] = {
  200. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  201. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  202. 0,
  203. };
  204. void rts5229_init_params(struct rtsx_pcr *pcr)
  205. {
  206. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  207. pcr->num_slots = 2;
  208. pcr->ops = &rts5229_pcr_ops;
  209. pcr->flags = 0;
  210. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  211. pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
  212. pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
  213. pcr->aspm_en = ASPM_L1_EN;
  214. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
  215. pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);
  216. pcr->ic_version = rts5229_get_ic_version(pcr);
  217. if (pcr->ic_version == IC_VER_C) {
  218. pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2;
  219. pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2;
  220. } else {
  221. pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1;
  222. pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1;
  223. }
  224. pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl;
  225. pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl;
  226. }