rts5228.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Ricky WU <ricky_wu@realtek.com>
  8. * Rui FENG <rui_feng@realsil.com.cn>
  9. * Wei WANG <wei_wang@realsil.com.cn>
  10. */
  11. #ifndef RTS5228_H
  12. #define RTS5228_H
  13. #define RTS5228_AUTOLOAD_CFG0 0xFF7B
  14. #define RTS5228_AUTOLOAD_CFG1 0xFF7C
  15. #define RTS5228_AUTOLOAD_CFG2 0xFF7D
  16. #define RTS5228_AUTOLOAD_CFG3 0xFF7E
  17. #define RTS5228_AUTOLOAD_CFG4 0xFF7F
  18. #define RTS5228_REG_VREF 0xFE97
  19. #define RTS5228_PWD_SUSPND_EN (1 << 4)
  20. #define RTS5228_PAD_H3L1 0xFF79
  21. #define PAD_GPIO_H3L1 (1 << 3)
  22. /* SSC_CTL2 0xFC12 */
  23. #define RTS5228_SSC_DEPTH_MASK 0x07
  24. #define RTS5228_SSC_DEPTH_DISALBE 0x00
  25. #define RTS5228_SSC_DEPTH_8M 0x01
  26. #define RTS5228_SSC_DEPTH_4M 0x02
  27. #define RTS5228_SSC_DEPTH_2M 0x03
  28. #define RTS5228_SSC_DEPTH_1M 0x04
  29. #define RTS5228_SSC_DEPTH_512K 0x05
  30. #define RTS5228_SSC_DEPTH_256K 0x06
  31. #define RTS5228_SSC_DEPTH_128K 0x07
  32. /* DMACTL 0xFE2C */
  33. #define RTS5228_DMA_PACK_SIZE_MASK 0xF0
  34. #define RTS5228_REG_LDO12_CFG 0xFF6E
  35. #define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1)
  36. #define RTS5228_LDO12_100 (0x00<<1)
  37. #define RTS5228_LDO12_105 (0x01<<1)
  38. #define RTS5228_LDO12_110 (0x02<<1)
  39. #define RTS5228_LDO12_115 (0x03<<1)
  40. #define RTS5228_LDO12_120 (0x04<<1)
  41. #define RTS5228_LDO12_125 (0x05<<1)
  42. #define RTS5228_LDO12_130 (0x06<<1)
  43. #define RTS5228_LDO12_135 (0x07<<1)
  44. #define RTS5228_REG_PWD_LDO12 (0x01<<0)
  45. #define RTS5228_REG_LDO12_L12 0xFF6F
  46. #define RTS5228_LDO12_L12_MASK (0x07<<4)
  47. #define RTS5228_LDO12_L12_120 (0x04<<4)
  48. /* LDO control register */
  49. #define RTS5228_CARD_PWR_CTL 0xFD50
  50. #define RTS5228_PUPDC (0x01<<5)
  51. #define RTS5228_LDO1233318_POW_CTL 0xFF70
  52. #define RTS5228_LDO3318_POWERON (0x01<<3)
  53. #define RTS5228_LDO1_POWEROFF (0x00<<0)
  54. #define RTS5228_LDO1_SOFTSTART (0x01<<0)
  55. #define RTS5228_LDO1_FULLON (0x03<<0)
  56. #define RTS5228_LDO1_POWERON_MASK (0x03<<0)
  57. #define RTS5228_LDO_POWERON_MASK (0x0F<<0)
  58. #define RTS5228_DV3318_CFG 0xFF71
  59. #define RTS5228_DV3318_TUNE_MASK (0x07<<4)
  60. #define RTS5228_DV3318_17 (0x00<<4)
  61. #define RTS5228_DV3318_1V75 (0x01<<4)
  62. #define RTS5228_DV3318_18 (0x02<<4)
  63. #define RTS5228_DV3318_1V85 (0x03<<4)
  64. #define RTS5228_DV3318_19 (0x04<<4)
  65. #define RTS5228_DV3318_33 (0x07<<4)
  66. #define RTS5228_DV3318_SR_MASK (0x03<<2)
  67. #define RTS5228_DV3318_SR_0 (0x00<<2)
  68. #define RTS5228_DV3318_SR_250 (0x01<<2)
  69. #define RTS5228_DV3318_SR_500 (0x02<<2)
  70. #define RTS5228_DV3318_SR_1000 (0x03<<2)
  71. #define RTS5228_LDO1_CFG0 0xFF72
  72. #define RTS5228_LDO1_OCP_THD_MASK (0x07<<5)
  73. #define RTS5228_LDO1_OCP_EN (0x01<<4)
  74. #define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2)
  75. #define RTS5228_LDO1_OCP_LMT_EN (0x01<<1)
  76. #define RTS5228_LDO1_OCP_THD_730 (0x00<<5)
  77. #define RTS5228_LDO1_OCP_THD_780 (0x01<<5)
  78. #define RTS5228_LDO1_OCP_THD_860 (0x02<<5)
  79. #define RTS5228_LDO1_OCP_THD_930 (0x03<<5)
  80. #define RTS5228_LDO1_OCP_THD_1000 (0x04<<5)
  81. #define RTS5228_LDO1_OCP_THD_1070 (0x05<<5)
  82. #define RTS5228_LDO1_OCP_THD_1140 (0x06<<5)
  83. #define RTS5228_LDO1_OCP_THD_1220 (0x07<<5)
  84. #define RTS5228_LDO1_LMT_THD_450 (0x00<<2)
  85. #define RTS5228_LDO1_LMT_THD_1000 (0x01<<2)
  86. #define RTS5228_LDO1_LMT_THD_1500 (0x02<<2)
  87. #define RTS5228_LDO1_LMT_THD_2000 (0x03<<2)
  88. #define RTS5228_LDO1_CFG1 0xFF73
  89. #define RTS5228_LDO1_SR_TIME_MASK (0x03<<6)
  90. #define RTS5228_LDO1_SR_0_0 (0x00<<6)
  91. #define RTS5228_LDO1_SR_0_25 (0x01<<6)
  92. #define RTS5228_LDO1_SR_0_5 (0x02<<6)
  93. #define RTS5228_LDO1_SR_1_0 (0x03<<6)
  94. #define RTS5228_LDO1_TUNE_MASK (0x07<<1)
  95. #define RTS5228_LDO1_18 (0x05<<1)
  96. #define RTS5228_LDO1_33 (0x07<<1)
  97. #define RTS5228_LDO1_PWD_MASK (0x01<<0)
  98. #define RTS5228_AUXCLK_GAT_CTL 0xFF74
  99. #define RTS5228_REG_RREF_CTL_0 0xFF75
  100. #define RTS5228_FORCE_RREF_EXTL (0x01<<7)
  101. #define RTS5228_REG_BG33_MASK (0x07<<0)
  102. #define RTS5228_RREF_12_1V (0x04<<0)
  103. #define RTS5228_RREF_12_3V (0x05<<0)
  104. #define RTS5228_REG_RREF_CTL_1 0xFF76
  105. #define RTS5228_REG_RREF_CTL_2 0xFF77
  106. #define RTS5228_TEST_INTL_RREF (0x01<<7)
  107. #define RTS5228_DGLCH_TIME_MASK (0x03<<5)
  108. #define RTS5228_DGLCH_TIME_50 (0x00<<5)
  109. #define RTS5228_DGLCH_TIME_75 (0x01<<5)
  110. #define RTS5228_DGLCH_TIME_100 (0x02<<5)
  111. #define RTS5228_DGLCH_TIME_125 (0x03<<5)
  112. #define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0)
  113. #define RTS5228_REG_PME_FORCE_CTL 0xFF78
  114. #define FORCE_PM_CONTROL 0x20
  115. #define FORCE_PM_VALUE 0x10
  116. /* Single LUN, support SD */
  117. #define DEFAULT_SINGLE 0
  118. #define SD_LUN 1
  119. /* For Change_FPGA_SSCClock Function */
  120. #define MULTIPLY_BY_1 0x00
  121. #define MULTIPLY_BY_2 0x01
  122. #define MULTIPLY_BY_3 0x02
  123. #define MULTIPLY_BY_4 0x03
  124. #define MULTIPLY_BY_5 0x04
  125. #define MULTIPLY_BY_6 0x05
  126. #define MULTIPLY_BY_7 0x06
  127. #define MULTIPLY_BY_8 0x07
  128. #define MULTIPLY_BY_9 0x08
  129. #define MULTIPLY_BY_10 0x09
  130. #define DIVIDE_BY_2 0x01
  131. #define DIVIDE_BY_3 0x02
  132. #define DIVIDE_BY_4 0x03
  133. #define DIVIDE_BY_5 0x04
  134. #define DIVIDE_BY_6 0x05
  135. #define DIVIDE_BY_7 0x06
  136. #define DIVIDE_BY_8 0x07
  137. #define DIVIDE_BY_9 0x08
  138. #define DIVIDE_BY_10 0x09
  139. int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  140. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
  141. #endif /* RTS5228_H */