rts5228.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Ricky WU <ricky_wu@realtek.com>
  8. * Rui FENG <rui_feng@realsil.com.cn>
  9. * Wei WANG <wei_wang@realsil.com.cn>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/delay.h>
  13. #include <linux/rtsx_pci.h>
  14. #include "rts5228.h"
  15. #include "rtsx_pcr.h"
  16. static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
  17. {
  18. u8 val;
  19. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  20. return val & IC_VERSION_MASK;
  21. }
  22. static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  23. {
  24. u8 driving_3v3[4][3] = {
  25. {0x13, 0x13, 0x13},
  26. {0x96, 0x96, 0x96},
  27. {0x7F, 0x7F, 0x7F},
  28. {0x96, 0x96, 0x96},
  29. };
  30. u8 driving_1v8[4][3] = {
  31. {0x99, 0x99, 0x99},
  32. {0xB5, 0xB5, 0xB5},
  33. {0xE6, 0x7E, 0xFE},
  34. {0x6B, 0x6B, 0x6B},
  35. };
  36. u8 (*driving)[3], drive_sel;
  37. if (voltage == OUTPUT_3V3) {
  38. driving = driving_3v3;
  39. drive_sel = pcr->sd30_drive_sel_3v3;
  40. } else {
  41. driving = driving_1v8;
  42. drive_sel = pcr->sd30_drive_sel_1v8;
  43. }
  44. rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  45. 0xFF, driving[drive_sel][0]);
  46. rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  47. 0xFF, driving[drive_sel][1]);
  48. rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  49. 0xFF, driving[drive_sel][2]);
  50. }
  51. static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
  52. {
  53. struct pci_dev *pdev = pcr->pci;
  54. u32 reg;
  55. /* 0x724~0x727 */
  56. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  57. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  58. if (!rtsx_vendor_setting_valid(reg)) {
  59. pcr_dbg(pcr, "skip fetch vendor setting\n");
  60. return;
  61. }
  62. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  63. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  64. /* 0x814~0x817 */
  65. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  66. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  67. pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
  68. if (rtsx_check_mmc_support(reg))
  69. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  70. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  71. if (rtsx_reg_check_reverse_socket(reg))
  72. pcr->flags |= PCR_REVERSE_SOCKET;
  73. }
  74. static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
  75. {
  76. return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
  77. }
  78. static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  79. {
  80. /* Set relink_time to 0 */
  81. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  83. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  84. RELINK_TIME_MASK, 0);
  85. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  86. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  87. rtsx_pci_write_register(pcr, FPDCTL,
  88. SSC_POWER_DOWN, SSC_POWER_DOWN);
  89. }
  90. static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
  91. {
  92. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  93. LED_SHINE_MASK, LED_SHINE_EN);
  94. }
  95. static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
  96. {
  97. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  98. LED_SHINE_MASK, LED_SHINE_DISABLE);
  99. }
  100. static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
  101. {
  102. return rtsx_pci_write_register(pcr, GPIO_CTL,
  103. 0x02, 0x02);
  104. }
  105. static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
  106. {
  107. return rtsx_pci_write_register(pcr, GPIO_CTL,
  108. 0x02, 0x00);
  109. }
  110. /* SD Pull Control Enable:
  111. * SD_DAT[3:0] ==> pull up
  112. * SD_CD ==> pull up
  113. * SD_WP ==> pull up
  114. * SD_CMD ==> pull up
  115. * SD_CLK ==> pull down
  116. */
  117. static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
  118. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  119. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  120. 0,
  121. };
  122. /* SD Pull Control Disable:
  123. * SD_DAT[3:0] ==> pull down
  124. * SD_CD ==> pull up
  125. * SD_WP ==> pull down
  126. * SD_CMD ==> pull down
  127. * SD_CLK ==> pull down
  128. */
  129. static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
  130. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  131. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  132. 0,
  133. };
  134. static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
  135. {
  136. rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
  137. | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
  138. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
  139. rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
  140. CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
  141. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  142. return 0;
  143. }
  144. static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
  145. {
  146. struct rtsx_cr_option *option = &pcr->option;
  147. if (option->ocp_en)
  148. rtsx_pci_enable_ocp(pcr);
  149. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
  150. CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
  151. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
  152. RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
  153. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  154. RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
  155. mdelay(2);
  156. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  157. RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
  158. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  159. RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
  160. msleep(20);
  161. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
  162. /* Initialize SD_CFG1 register */
  163. rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
  164. SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
  165. rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
  166. 0xFF, SD20_RX_POS_EDGE);
  167. rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
  168. rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
  169. SD_STOP | SD_CLR_ERR);
  170. /* Reset SD_CFG3 register */
  171. rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
  172. rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
  173. SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
  174. SD30_CLK_STOP_CFG0, 0);
  175. if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
  176. pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
  177. rts5228_sd_set_sample_push_timing_sd30(pcr);
  178. return 0;
  179. }
  180. static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  181. {
  182. int err;
  183. u16 val = 0;
  184. rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
  185. RTS5228_PUPDC, RTS5228_PUPDC);
  186. switch (voltage) {
  187. case OUTPUT_3V3:
  188. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  189. val |= PHY_TUNE_SDBUS_33;
  190. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  191. if (err < 0)
  192. return err;
  193. rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
  194. RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
  195. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  196. SD_IO_USING_1V8, 0);
  197. break;
  198. case OUTPUT_1V8:
  199. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  200. val &= ~PHY_TUNE_SDBUS_33;
  201. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  202. if (err < 0)
  203. return err;
  204. rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
  205. RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
  206. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  207. SD_IO_USING_1V8, SD_IO_USING_1V8);
  208. break;
  209. default:
  210. return -EINVAL;
  211. }
  212. /* set pad drive */
  213. rts5228_fill_driving(pcr, voltage);
  214. return 0;
  215. }
  216. static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
  217. {
  218. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  219. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  220. rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
  221. RTS5260_DMA_RST | RTS5260_ADMA3_RST,
  222. RTS5260_DMA_RST | RTS5260_ADMA3_RST);
  223. rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
  224. }
  225. static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
  226. {
  227. rts5228_stop_cmd(pcr);
  228. rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
  229. }
  230. static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
  231. {
  232. u8 val = 0;
  233. val = SD_OCP_INT_EN | SD_DETECT_EN;
  234. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  235. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  236. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
  237. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
  238. }
  239. static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
  240. {
  241. u8 mask = 0;
  242. mask = SD_OCP_INT_EN | SD_DETECT_EN;
  243. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  244. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  245. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
  246. }
  247. static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
  248. {
  249. int err = 0;
  250. rts5228_card_before_power_off(pcr);
  251. err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  252. RTS5228_LDO_POWERON_MASK, 0);
  253. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
  254. if (pcr->option.ocp_en)
  255. rtsx_pci_disable_ocp(pcr);
  256. return err;
  257. }
  258. static void rts5228_init_ocp(struct rtsx_pcr *pcr)
  259. {
  260. struct rtsx_cr_option *option = &pcr->option;
  261. if (option->ocp_en) {
  262. u8 mask, val;
  263. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  264. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
  265. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
  266. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  267. RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
  268. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  269. RTS5228_LDO1_OCP_LMT_THD_MASK,
  270. RTS5228_LDO1_LMT_THD_1500);
  271. rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
  272. mask = SD_OCP_GLITCH_MASK;
  273. val = pcr->hw_param.ocp_glitch;
  274. rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
  275. rts5228_enable_ocp(pcr);
  276. } else {
  277. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  278. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
  279. }
  280. }
  281. static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
  282. {
  283. u8 mask = 0;
  284. u8 val = 0;
  285. mask = SD_OCP_INT_CLR | SD_OC_CLR;
  286. val = SD_OCP_INT_CLR | SD_OC_CLR;
  287. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  288. udelay(1000);
  289. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  290. }
  291. static void rts5228_process_ocp(struct rtsx_pcr *pcr)
  292. {
  293. if (!pcr->option.ocp_en)
  294. return;
  295. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  296. if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
  297. rts5228_clear_ocpstat(pcr);
  298. rts5228_card_power_off(pcr, RTSX_SD_CARD);
  299. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  300. pcr->ocp_stat = 0;
  301. }
  302. }
  303. static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
  304. {
  305. struct pci_dev *pdev = pcr->pci;
  306. int l1ss;
  307. u32 lval;
  308. struct rtsx_cr_option *option = &pcr->option;
  309. l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  310. if (!l1ss)
  311. return;
  312. pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  313. if (0 == (lval & 0x0F))
  314. rtsx_pci_enable_oobs_polling(pcr);
  315. else
  316. rtsx_pci_disable_oobs_polling(pcr);
  317. if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
  318. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  319. else
  320. rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
  321. if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
  322. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  323. else
  324. rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
  325. if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
  326. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  327. else
  328. rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
  329. if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
  330. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  331. else
  332. rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
  333. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
  334. if (option->ltr_en) {
  335. u16 val;
  336. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
  337. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  338. option->ltr_enabled = true;
  339. option->ltr_active = true;
  340. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  341. } else {
  342. option->ltr_enabled = false;
  343. }
  344. }
  345. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  346. | PM_L1_1_EN | PM_L1_2_EN))
  347. option->force_clkreq_0 = false;
  348. else
  349. option->force_clkreq_0 = true;
  350. }
  351. static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
  352. {
  353. struct rtsx_cr_option *option = &pcr->option;
  354. rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
  355. CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
  356. rts5228_init_from_cfg(pcr);
  357. rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
  358. AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
  359. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
  360. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  361. FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
  362. rtsx_pci_write_register(pcr, PCLK_CTL,
  363. PCLK_MODE_SEL, PCLK_MODE_SEL);
  364. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  365. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
  366. /* LED shine disabled, set initial shine cycle period */
  367. rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
  368. /* Configure driving */
  369. rts5228_fill_driving(pcr, OUTPUT_3V3);
  370. if (pcr->flags & PCR_REVERSE_SOCKET)
  371. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
  372. else
  373. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
  374. /*
  375. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  376. * to drive low, and we forcibly request clock.
  377. */
  378. if (option->force_clkreq_0)
  379. rtsx_pci_write_register(pcr, PETXCFG,
  380. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  381. else
  382. rtsx_pci_write_register(pcr, PETXCFG,
  383. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  384. rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
  385. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
  386. rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
  387. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  388. return 0;
  389. }
  390. static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
  391. {
  392. u8 mask, val;
  393. if (pcr->aspm_enabled == enable)
  394. return;
  395. mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  396. val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  397. val |= (pcr->aspm_en & 0x02);
  398. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  399. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  400. PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
  401. pcr->aspm_enabled = enable;
  402. }
  403. static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
  404. {
  405. u8 mask, val;
  406. if (pcr->aspm_enabled == enable)
  407. return;
  408. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  409. PCI_EXP_LNKCTL_ASPMC, 0);
  410. mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  411. val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  412. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  413. rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
  414. mdelay(10);
  415. pcr->aspm_enabled = enable;
  416. }
  417. static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
  418. {
  419. if (enable)
  420. rts5228_enable_aspm(pcr, true);
  421. else
  422. rts5228_disable_aspm(pcr, false);
  423. }
  424. static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  425. {
  426. struct rtsx_cr_option *option = &pcr->option;
  427. int aspm_L1_1, aspm_L1_2;
  428. u8 val = 0;
  429. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  430. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  431. if (active) {
  432. /* run, latency: 60us */
  433. if (aspm_L1_1)
  434. val = option->ltr_l1off_snooze_sspwrgate;
  435. } else {
  436. /* l1off, latency: 300us */
  437. if (aspm_L1_2)
  438. val = option->ltr_l1off_sspwrgate;
  439. }
  440. rtsx_set_l1off_sub(pcr, val);
  441. }
  442. static const struct pcr_ops rts5228_pcr_ops = {
  443. .fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
  444. .turn_on_led = rts5228_turn_on_led,
  445. .turn_off_led = rts5228_turn_off_led,
  446. .extra_init_hw = rts5228_extra_init_hw,
  447. .enable_auto_blink = rts5228_enable_auto_blink,
  448. .disable_auto_blink = rts5228_disable_auto_blink,
  449. .card_power_on = rts5228_card_power_on,
  450. .card_power_off = rts5228_card_power_off,
  451. .switch_output_voltage = rts5228_switch_output_voltage,
  452. .force_power_down = rts5228_force_power_down,
  453. .stop_cmd = rts5228_stop_cmd,
  454. .set_aspm = rts5228_set_aspm,
  455. .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
  456. .enable_ocp = rts5228_enable_ocp,
  457. .disable_ocp = rts5228_disable_ocp,
  458. .init_ocp = rts5228_init_ocp,
  459. .process_ocp = rts5228_process_ocp,
  460. .clear_ocpstat = rts5228_clear_ocpstat,
  461. .optimize_phy = rts5228_optimize_phy,
  462. };
  463. static inline u8 double_ssc_depth(u8 depth)
  464. {
  465. return ((depth > 1) ? (depth - 1) : depth);
  466. }
  467. int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  468. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  469. {
  470. int err, clk;
  471. u16 n;
  472. u8 clk_divider, mcu_cnt, div;
  473. static const u8 depth[] = {
  474. [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
  475. [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
  476. [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
  477. [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
  478. };
  479. if (initial_mode) {
  480. /* We use 250k(around) here, in initial stage */
  481. clk_divider = SD_CLK_DIVIDE_128;
  482. card_clock = 30000000;
  483. } else {
  484. clk_divider = SD_CLK_DIVIDE_0;
  485. }
  486. err = rtsx_pci_write_register(pcr, SD_CFG1,
  487. SD_CLK_DIVIDE_MASK, clk_divider);
  488. if (err < 0)
  489. return err;
  490. card_clock /= 1000000;
  491. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  492. clk = card_clock;
  493. if (!initial_mode && double_clk)
  494. clk = card_clock * 2;
  495. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  496. clk, pcr->cur_clock);
  497. if (clk == pcr->cur_clock)
  498. return 0;
  499. if (pcr->ops->conv_clk_and_div_n)
  500. n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  501. else
  502. n = clk - 4;
  503. if ((clk <= 4) || (n > 396))
  504. return -EINVAL;
  505. mcu_cnt = 125/clk + 3;
  506. if (mcu_cnt > 15)
  507. mcu_cnt = 15;
  508. div = CLK_DIV_1;
  509. while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
  510. if (pcr->ops->conv_clk_and_div_n) {
  511. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  512. DIV_N_TO_CLK) * 2;
  513. n = pcr->ops->conv_clk_and_div_n(dbl_clk,
  514. CLK_TO_DIV_N);
  515. } else {
  516. n = (n + 4) * 2 - 4;
  517. }
  518. div++;
  519. }
  520. n = (n / 2) - 1;
  521. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  522. ssc_depth = depth[ssc_depth];
  523. if (double_clk)
  524. ssc_depth = double_ssc_depth(ssc_depth);
  525. if (ssc_depth) {
  526. if (div == CLK_DIV_2) {
  527. if (ssc_depth > 1)
  528. ssc_depth -= 1;
  529. else
  530. ssc_depth = RTS5228_SSC_DEPTH_8M;
  531. } else if (div == CLK_DIV_4) {
  532. if (ssc_depth > 2)
  533. ssc_depth -= 2;
  534. else
  535. ssc_depth = RTS5228_SSC_DEPTH_8M;
  536. } else if (div == CLK_DIV_8) {
  537. if (ssc_depth > 3)
  538. ssc_depth -= 3;
  539. else
  540. ssc_depth = RTS5228_SSC_DEPTH_8M;
  541. }
  542. } else {
  543. ssc_depth = 0;
  544. }
  545. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  546. rtsx_pci_init_cmd(pcr);
  547. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  548. CLK_LOW_FREQ, CLK_LOW_FREQ);
  549. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  550. 0xFF, (div << 4) | mcu_cnt);
  551. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  552. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  553. SSC_DEPTH_MASK, ssc_depth);
  554. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  555. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  556. if (vpclk) {
  557. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  558. PHASE_NOT_RESET, 0);
  559. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  560. PHASE_NOT_RESET, 0);
  561. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  562. PHASE_NOT_RESET, PHASE_NOT_RESET);
  563. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  564. PHASE_NOT_RESET, PHASE_NOT_RESET);
  565. }
  566. err = rtsx_pci_send_cmd(pcr, 2000);
  567. if (err < 0)
  568. return err;
  569. /* Wait SSC clock stable */
  570. udelay(SSC_CLOCK_STABLE_WAIT);
  571. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  572. if (err < 0)
  573. return err;
  574. pcr->cur_clock = clk;
  575. return 0;
  576. }
  577. void rts5228_init_params(struct rtsx_pcr *pcr)
  578. {
  579. struct rtsx_cr_option *option = &pcr->option;
  580. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  581. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  582. pcr->num_slots = 1;
  583. pcr->ops = &rts5228_pcr_ops;
  584. pcr->flags = 0;
  585. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  586. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  587. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  588. pcr->aspm_en = ASPM_L1_EN;
  589. pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
  590. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  591. pcr->ic_version = rts5228_get_ic_version(pcr);
  592. pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
  593. pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
  594. pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
  595. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  596. | LTR_L1SS_PWR_GATE_EN);
  597. option->ltr_en = true;
  598. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  599. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  600. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  601. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  602. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  603. option->ltr_l1off_sspwrgate = 0x7F;
  604. option->ltr_l1off_snooze_sspwrgate = 0x78;
  605. option->ocp_en = 1;
  606. hw_param->interrupt_en |= SD_OC_INT_EN;
  607. hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
  608. option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930;
  609. }