rts5227.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. * Roger Tseng <rogerable@realtek.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/rtsx_pci.h>
  13. #include "rtsx_pcr.h"
  14. static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  15. {
  16. u8 val;
  17. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  18. return val & 0x0F;
  19. }
  20. static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  21. {
  22. u8 driving_3v3[4][3] = {
  23. {0x13, 0x13, 0x13},
  24. {0x96, 0x96, 0x96},
  25. {0x7F, 0x7F, 0x7F},
  26. {0x96, 0x96, 0x96},
  27. };
  28. u8 driving_1v8[4][3] = {
  29. {0x99, 0x99, 0x99},
  30. {0xAA, 0xAA, 0xAA},
  31. {0xFE, 0xFE, 0xFE},
  32. {0xB3, 0xB3, 0xB3},
  33. };
  34. u8 (*driving)[3], drive_sel;
  35. if (voltage == OUTPUT_3V3) {
  36. driving = driving_3v3;
  37. drive_sel = pcr->sd30_drive_sel_3v3;
  38. } else {
  39. driving = driving_1v8;
  40. drive_sel = pcr->sd30_drive_sel_1v8;
  41. }
  42. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  43. 0xFF, driving[drive_sel][0]);
  44. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  45. 0xFF, driving[drive_sel][1]);
  46. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  47. 0xFF, driving[drive_sel][2]);
  48. }
  49. static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  50. {
  51. struct pci_dev *pdev = pcr->pci;
  52. u32 reg;
  53. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  54. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  55. if (!rtsx_vendor_setting_valid(reg))
  56. return;
  57. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  58. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  59. pcr->card_drive_sel &= 0x3F;
  60. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  61. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  62. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  63. if (rtsx_check_mmc_support(reg))
  64. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  65. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  66. if (rtsx_reg_check_reverse_socket(reg))
  67. pcr->flags |= PCR_REVERSE_SOCKET;
  68. }
  69. static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
  70. {
  71. struct pci_dev *pdev = pcr->pci;
  72. int l1ss;
  73. u32 lval;
  74. struct rtsx_cr_option *option = &pcr->option;
  75. l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  76. if (!l1ss)
  77. return;
  78. pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  79. if (CHK_PCI_PID(pcr, 0x522A)) {
  80. if (0 == (lval & 0x0F))
  81. rtsx_pci_enable_oobs_polling(pcr);
  82. else
  83. rtsx_pci_disable_oobs_polling(pcr);
  84. }
  85. if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
  86. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  87. else
  88. rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
  89. if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
  90. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  91. else
  92. rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
  93. if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
  94. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  95. else
  96. rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
  97. if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
  98. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  99. else
  100. rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
  101. if (option->ltr_en) {
  102. u16 val;
  103. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
  104. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  105. option->ltr_enabled = true;
  106. option->ltr_active = true;
  107. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  108. } else {
  109. option->ltr_enabled = false;
  110. }
  111. }
  112. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  113. | PM_L1_1_EN | PM_L1_2_EN))
  114. option->force_clkreq_0 = false;
  115. else
  116. option->force_clkreq_0 = true;
  117. }
  118. static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
  119. {
  120. u16 cap;
  121. struct rtsx_cr_option *option = &pcr->option;
  122. rts5227_init_from_cfg(pcr);
  123. rtsx_pci_init_cmd(pcr);
  124. /* Configure GPIO as output */
  125. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  126. /* Reset ASPM state to default value */
  127. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  128. /* Switch LDO3318 source from DV33 to card_3v3 */
  129. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  130. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  131. /* LED shine disabled, set initial shine cycle period */
  132. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  133. /* Configure LTR */
  134. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
  135. if (cap & PCI_EXP_DEVCTL2_LTR_EN)
  136. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
  137. /* Configure OBFF */
  138. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
  139. /* Configure driving */
  140. rts5227_fill_driving(pcr, OUTPUT_3V3);
  141. /* Configure force_clock_req */
  142. if (pcr->flags & PCR_REVERSE_SOCKET)
  143. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
  144. else
  145. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
  146. if (option->force_clkreq_0)
  147. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  148. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  149. else
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  151. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  152. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
  153. return rtsx_pci_send_cmd(pcr, 100);
  154. }
  155. static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
  156. {
  157. int err;
  158. err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
  159. if (err < 0)
  160. return err;
  161. /* Optimize RX sensitivity */
  162. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  163. }
  164. static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
  165. {
  166. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  167. }
  168. static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
  169. {
  170. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  171. }
  172. static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
  173. {
  174. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  175. }
  176. static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
  177. {
  178. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  179. }
  180. static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
  181. {
  182. int err;
  183. if (pcr->option.ocp_en)
  184. rtsx_pci_enable_ocp(pcr);
  185. rtsx_pci_init_cmd(pcr);
  186. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  187. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  188. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  189. LDO3318_PWR_MASK, 0x02);
  190. err = rtsx_pci_send_cmd(pcr, 100);
  191. if (err < 0)
  192. return err;
  193. /* To avoid too large in-rush current */
  194. msleep(20);
  195. rtsx_pci_init_cmd(pcr);
  196. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  197. SD_POWER_MASK, SD_POWER_ON);
  198. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  199. LDO3318_PWR_MASK, 0x06);
  200. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
  201. SD_OUTPUT_EN, SD_OUTPUT_EN);
  202. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
  203. MS_OUTPUT_EN, MS_OUTPUT_EN);
  204. return rtsx_pci_send_cmd(pcr, 100);
  205. }
  206. static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
  207. {
  208. if (pcr->option.ocp_en)
  209. rtsx_pci_disable_ocp(pcr);
  210. rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
  211. PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
  212. rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
  213. return 0;
  214. }
  215. static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  216. {
  217. int err;
  218. if (voltage == OUTPUT_3V3) {
  219. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  220. if (err < 0)
  221. return err;
  222. } else if (voltage == OUTPUT_1V8) {
  223. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  224. if (err < 0)
  225. return err;
  226. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
  227. if (err < 0)
  228. return err;
  229. } else {
  230. return -EINVAL;
  231. }
  232. /* set pad drive */
  233. rtsx_pci_init_cmd(pcr);
  234. rts5227_fill_driving(pcr, voltage);
  235. return rtsx_pci_send_cmd(pcr, 100);
  236. }
  237. static const struct pcr_ops rts5227_pcr_ops = {
  238. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  239. .extra_init_hw = rts5227_extra_init_hw,
  240. .optimize_phy = rts5227_optimize_phy,
  241. .turn_on_led = rts5227_turn_on_led,
  242. .turn_off_led = rts5227_turn_off_led,
  243. .enable_auto_blink = rts5227_enable_auto_blink,
  244. .disable_auto_blink = rts5227_disable_auto_blink,
  245. .card_power_on = rts5227_card_power_on,
  246. .card_power_off = rts5227_card_power_off,
  247. .switch_output_voltage = rts5227_switch_output_voltage,
  248. .cd_deglitch = NULL,
  249. .conv_clk_and_div_n = NULL,
  250. };
  251. /* SD Pull Control Enable:
  252. * SD_DAT[3:0] ==> pull up
  253. * SD_CD ==> pull up
  254. * SD_WP ==> pull up
  255. * SD_CMD ==> pull up
  256. * SD_CLK ==> pull down
  257. */
  258. static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
  259. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  260. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  261. 0,
  262. };
  263. /* SD Pull Control Disable:
  264. * SD_DAT[3:0] ==> pull down
  265. * SD_CD ==> pull up
  266. * SD_WP ==> pull down
  267. * SD_CMD ==> pull down
  268. * SD_CLK ==> pull down
  269. */
  270. static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
  271. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  272. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  273. 0,
  274. };
  275. /* MS Pull Control Enable:
  276. * MS CD ==> pull up
  277. * others ==> pull down
  278. */
  279. static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
  280. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  281. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  282. 0,
  283. };
  284. /* MS Pull Control Disable:
  285. * MS CD ==> pull up
  286. * others ==> pull down
  287. */
  288. static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
  289. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  290. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  291. 0,
  292. };
  293. void rts5227_init_params(struct rtsx_pcr *pcr)
  294. {
  295. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  296. pcr->num_slots = 2;
  297. pcr->ops = &rts5227_pcr_ops;
  298. pcr->flags = 0;
  299. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  300. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  301. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  302. pcr->aspm_en = ASPM_L1_EN;
  303. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
  304. pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
  305. pcr->ic_version = rts5227_get_ic_version(pcr);
  306. pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
  307. pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
  308. pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
  309. pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
  310. pcr->reg_pm_ctrl3 = PM_CTRL3;
  311. }
  312. static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
  313. {
  314. int err;
  315. err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
  316. 0x00);
  317. if (err < 0)
  318. return err;
  319. if (is_version(pcr, 0x522A, IC_VER_A)) {
  320. err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
  321. PHY_RCR2_INIT_27S);
  322. if (err)
  323. return err;
  324. rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
  325. rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
  326. rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
  327. rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
  328. }
  329. return 0;
  330. }
  331. static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
  332. {
  333. rts5227_extra_init_hw(pcr);
  334. /* Power down OCP for power consumption */
  335. if (!pcr->card_exist)
  336. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
  337. OC_POWER_DOWN);
  338. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
  339. FUNC_FORCE_UPME_XMT_DBG);
  340. rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
  341. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  342. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
  343. return 0;
  344. }
  345. static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  346. {
  347. int err;
  348. if (voltage == OUTPUT_3V3) {
  349. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
  350. if (err < 0)
  351. return err;
  352. } else if (voltage == OUTPUT_1V8) {
  353. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  354. if (err < 0)
  355. return err;
  356. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
  357. if (err < 0)
  358. return err;
  359. } else {
  360. return -EINVAL;
  361. }
  362. /* set pad drive */
  363. rtsx_pci_init_cmd(pcr);
  364. rts5227_fill_driving(pcr, voltage);
  365. return rtsx_pci_send_cmd(pcr, 100);
  366. }
  367. static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  368. {
  369. struct rtsx_cr_option *option = &pcr->option;
  370. int aspm_L1_1, aspm_L1_2;
  371. u8 val = 0;
  372. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  373. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  374. if (active) {
  375. /* run, latency: 60us */
  376. if (aspm_L1_1)
  377. val = option->ltr_l1off_snooze_sspwrgate;
  378. } else {
  379. /* l1off, latency: 300us */
  380. if (aspm_L1_2)
  381. val = option->ltr_l1off_sspwrgate;
  382. }
  383. rtsx_set_l1off_sub(pcr, val);
  384. }
  385. /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
  386. */
  387. static const struct pcr_ops rts522a_pcr_ops = {
  388. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  389. .extra_init_hw = rts522a_extra_init_hw,
  390. .optimize_phy = rts522a_optimize_phy,
  391. .turn_on_led = rts5227_turn_on_led,
  392. .turn_off_led = rts5227_turn_off_led,
  393. .enable_auto_blink = rts5227_enable_auto_blink,
  394. .disable_auto_blink = rts5227_disable_auto_blink,
  395. .card_power_on = rts5227_card_power_on,
  396. .card_power_off = rts5227_card_power_off,
  397. .switch_output_voltage = rts522a_switch_output_voltage,
  398. .cd_deglitch = NULL,
  399. .conv_clk_and_div_n = NULL,
  400. .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
  401. };
  402. void rts522a_init_params(struct rtsx_pcr *pcr)
  403. {
  404. struct rtsx_cr_option *option = &pcr->option;
  405. rts5227_init_params(pcr);
  406. pcr->ops = &rts522a_pcr_ops;
  407. pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
  408. pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
  409. option->dev_flags = LTR_L1SS_PWR_GATE_EN;
  410. option->ltr_en = true;
  411. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  412. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  413. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  414. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  415. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  416. option->ltr_l1off_sspwrgate = 0x7F;
  417. option->ltr_l1off_snooze_sspwrgate = 0x78;
  418. pcr->option.ocp_en = 1;
  419. if (pcr->option.ocp_en)
  420. pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
  421. pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
  422. pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
  423. }