rtl8411.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. * Roger Tseng <rogerable@realtek.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. #include <linux/rtsx_pci.h>
  14. #include "rtsx_pcr.h"
  15. static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
  16. {
  17. u8 val;
  18. rtsx_pci_read_register(pcr, SYS_VER, &val);
  19. return val & 0x0F;
  20. }
  21. static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
  22. {
  23. u8 val = 0;
  24. rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
  25. if (val & 0x2)
  26. return 1;
  27. else
  28. return 0;
  29. }
  30. static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
  31. {
  32. struct pci_dev *pdev = pcr->pci;
  33. u32 reg1 = 0;
  34. u8 reg3 = 0;
  35. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg1);
  36. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
  37. if (!rtsx_vendor_setting_valid(reg1))
  38. return;
  39. pcr->aspm_en = rtsx_reg_to_aspm(reg1);
  40. pcr->sd30_drive_sel_1v8 =
  41. map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1));
  42. pcr->card_drive_sel &= 0x3F;
  43. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
  44. pci_read_config_byte(pdev, PCR_SETTING_REG3, &reg3);
  45. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
  46. pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
  47. }
  48. static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
  49. {
  50. struct pci_dev *pdev = pcr->pci;
  51. u32 reg = 0;
  52. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  53. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  54. if (!rtsx_vendor_setting_valid(reg))
  55. return;
  56. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  57. pcr->sd30_drive_sel_1v8 =
  58. map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
  59. pcr->sd30_drive_sel_3v3 =
  60. map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg));
  61. }
  62. static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  63. {
  64. rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
  65. }
  66. static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
  67. {
  68. rtsx_pci_init_cmd(pcr);
  69. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
  70. 0xFF, pcr->sd30_drive_sel_3v3);
  71. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
  72. CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
  73. return rtsx_pci_send_cmd(pcr, 100);
  74. }
  75. static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
  76. {
  77. rtsx_pci_init_cmd(pcr);
  78. if (rtl8411b_is_qfn48(pcr))
  79. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  80. CARD_PULL_CTL3, 0xFF, 0xF5);
  81. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
  82. 0xFF, pcr->sd30_drive_sel_3v3);
  83. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
  84. CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
  85. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL,
  86. 0x06, 0x00);
  87. return rtsx_pci_send_cmd(pcr, 100);
  88. }
  89. static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
  90. {
  91. return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
  92. }
  93. static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
  94. {
  95. return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
  96. }
  97. static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
  98. {
  99. return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
  100. }
  101. static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
  102. {
  103. return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
  104. }
  105. static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
  106. {
  107. int err;
  108. rtsx_pci_init_cmd(pcr);
  109. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  110. BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
  111. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
  112. BPP_LDO_POWB, BPP_LDO_SUSPEND);
  113. err = rtsx_pci_send_cmd(pcr, 100);
  114. if (err < 0)
  115. return err;
  116. /* To avoid too large in-rush current */
  117. udelay(150);
  118. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  119. BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
  120. if (err < 0)
  121. return err;
  122. udelay(150);
  123. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  124. BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
  125. if (err < 0)
  126. return err;
  127. udelay(150);
  128. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  129. BPP_POWER_MASK, BPP_POWER_ON);
  130. if (err < 0)
  131. return err;
  132. return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
  133. }
  134. static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
  135. {
  136. int err;
  137. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  138. BPP_POWER_MASK, BPP_POWER_OFF);
  139. if (err < 0)
  140. return err;
  141. return rtsx_pci_write_register(pcr, LDO_CTL,
  142. BPP_LDO_POWB, BPP_LDO_SUSPEND);
  143. }
  144. static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage,
  145. int bpp_tuned18_shift, int bpp_asic_1v8)
  146. {
  147. u8 mask, val;
  148. int err;
  149. mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK;
  150. if (voltage == OUTPUT_3V3) {
  151. err = rtsx_pci_write_register(pcr,
  152. SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
  153. if (err < 0)
  154. return err;
  155. val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3;
  156. } else if (voltage == OUTPUT_1V8) {
  157. err = rtsx_pci_write_register(pcr,
  158. SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
  159. if (err < 0)
  160. return err;
  161. val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8;
  162. } else {
  163. return -EINVAL;
  164. }
  165. return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
  166. }
  167. static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  168. {
  169. return rtl8411_do_switch_output_voltage(pcr, voltage,
  170. BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8);
  171. }
  172. static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  173. {
  174. return rtl8411_do_switch_output_voltage(pcr, voltage,
  175. BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0);
  176. }
  177. static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
  178. {
  179. unsigned int card_exist;
  180. card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
  181. card_exist &= CARD_EXIST;
  182. if (!card_exist) {
  183. /* Enable card CD */
  184. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  185. CD_DISABLE_MASK, CD_ENABLE);
  186. /* Enable card interrupt */
  187. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
  188. return 0;
  189. }
  190. if (hweight32(card_exist) > 1) {
  191. rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  192. BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
  193. msleep(100);
  194. card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
  195. if (card_exist & MS_EXIST)
  196. card_exist = MS_EXIST;
  197. else if (card_exist & SD_EXIST)
  198. card_exist = SD_EXIST;
  199. else
  200. card_exist = 0;
  201. rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  202. BPP_POWER_MASK, BPP_POWER_OFF);
  203. pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
  204. card_exist);
  205. }
  206. if (card_exist & MS_EXIST) {
  207. /* Disable SD interrupt */
  208. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
  209. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  210. CD_DISABLE_MASK, MS_CD_EN_ONLY);
  211. } else if (card_exist & SD_EXIST) {
  212. /* Disable MS interrupt */
  213. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
  214. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  215. CD_DISABLE_MASK, SD_CD_EN_ONLY);
  216. }
  217. return card_exist;
  218. }
  219. static int rtl8411_conv_clk_and_div_n(int input, int dir)
  220. {
  221. int output;
  222. if (dir == CLK_TO_DIV_N)
  223. output = input * 4 / 5 - 2;
  224. else
  225. output = (input + 2) * 5 / 4;
  226. return output;
  227. }
  228. static const struct pcr_ops rtl8411_pcr_ops = {
  229. .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
  230. .extra_init_hw = rtl8411_extra_init_hw,
  231. .optimize_phy = NULL,
  232. .turn_on_led = rtl8411_turn_on_led,
  233. .turn_off_led = rtl8411_turn_off_led,
  234. .enable_auto_blink = rtl8411_enable_auto_blink,
  235. .disable_auto_blink = rtl8411_disable_auto_blink,
  236. .card_power_on = rtl8411_card_power_on,
  237. .card_power_off = rtl8411_card_power_off,
  238. .switch_output_voltage = rtl8411_switch_output_voltage,
  239. .cd_deglitch = rtl8411_cd_deglitch,
  240. .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
  241. .force_power_down = rtl8411_force_power_down,
  242. };
  243. static const struct pcr_ops rtl8402_pcr_ops = {
  244. .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
  245. .extra_init_hw = rtl8411_extra_init_hw,
  246. .optimize_phy = NULL,
  247. .turn_on_led = rtl8411_turn_on_led,
  248. .turn_off_led = rtl8411_turn_off_led,
  249. .enable_auto_blink = rtl8411_enable_auto_blink,
  250. .disable_auto_blink = rtl8411_disable_auto_blink,
  251. .card_power_on = rtl8411_card_power_on,
  252. .card_power_off = rtl8411_card_power_off,
  253. .switch_output_voltage = rtl8402_switch_output_voltage,
  254. .cd_deglitch = rtl8411_cd_deglitch,
  255. .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
  256. .force_power_down = rtl8411_force_power_down,
  257. };
  258. static const struct pcr_ops rtl8411b_pcr_ops = {
  259. .fetch_vendor_settings = rtl8411b_fetch_vendor_settings,
  260. .extra_init_hw = rtl8411b_extra_init_hw,
  261. .optimize_phy = NULL,
  262. .turn_on_led = rtl8411_turn_on_led,
  263. .turn_off_led = rtl8411_turn_off_led,
  264. .enable_auto_blink = rtl8411_enable_auto_blink,
  265. .disable_auto_blink = rtl8411_disable_auto_blink,
  266. .card_power_on = rtl8411_card_power_on,
  267. .card_power_off = rtl8411_card_power_off,
  268. .switch_output_voltage = rtl8411_switch_output_voltage,
  269. .cd_deglitch = rtl8411_cd_deglitch,
  270. .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
  271. .force_power_down = rtl8411_force_power_down,
  272. };
  273. /* SD Pull Control Enable:
  274. * SD_DAT[3:0] ==> pull up
  275. * SD_CD ==> pull up
  276. * SD_WP ==> pull up
  277. * SD_CMD ==> pull up
  278. * SD_CLK ==> pull down
  279. */
  280. static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
  281. RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
  282. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  283. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
  284. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  285. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
  286. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  287. 0,
  288. };
  289. /* SD Pull Control Disable:
  290. * SD_DAT[3:0] ==> pull down
  291. * SD_CD ==> pull up
  292. * SD_WP ==> pull down
  293. * SD_CMD ==> pull down
  294. * SD_CLK ==> pull down
  295. */
  296. static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
  297. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  298. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  299. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  300. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  301. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  302. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  303. 0,
  304. };
  305. /* MS Pull Control Enable:
  306. * MS CD ==> pull up
  307. * others ==> pull down
  308. */
  309. static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
  310. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  311. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  312. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  313. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
  314. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  315. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  316. 0,
  317. };
  318. /* MS Pull Control Disable:
  319. * MS CD ==> pull up
  320. * others ==> pull down
  321. */
  322. static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
  323. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  324. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  325. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  326. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  327. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  328. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  329. 0,
  330. };
  331. static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = {
  332. RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
  333. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  334. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0),
  335. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  336. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  337. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  338. 0,
  339. };
  340. static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = {
  341. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  342. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90),
  343. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11),
  344. 0,
  345. };
  346. static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = {
  347. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  348. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  349. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  350. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  351. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  352. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  353. 0,
  354. };
  355. static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = {
  356. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  357. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  358. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  359. 0,
  360. };
  361. static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = {
  362. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  363. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  364. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  365. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50),
  366. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  367. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  368. 0,
  369. };
  370. static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = {
  371. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  372. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  373. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  374. 0,
  375. };
  376. static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = {
  377. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  378. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  379. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  380. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  381. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  382. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  383. 0,
  384. };
  385. static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = {
  386. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  387. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  388. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  389. 0,
  390. };
  391. static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
  392. {
  393. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  394. pcr->num_slots = 2;
  395. pcr->flags = 0;
  396. pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT;
  397. pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
  398. pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
  399. pcr->aspm_en = ASPM_L1_EN;
  400. pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
  401. pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
  402. pcr->ic_version = rtl8411_get_ic_version(pcr);
  403. }
  404. void rtl8411_init_params(struct rtsx_pcr *pcr)
  405. {
  406. rtl8411_init_common_params(pcr);
  407. pcr->ops = &rtl8411_pcr_ops;
  408. set_pull_ctrl_tables(pcr, rtl8411);
  409. }
  410. void rtl8411b_init_params(struct rtsx_pcr *pcr)
  411. {
  412. rtl8411_init_common_params(pcr);
  413. pcr->ops = &rtl8411b_pcr_ops;
  414. if (rtl8411b_is_qfn48(pcr))
  415. set_pull_ctrl_tables(pcr, rtl8411b_qfn48);
  416. else
  417. set_pull_ctrl_tables(pcr, rtl8411b_qfn64);
  418. }
  419. void rtl8402_init_params(struct rtsx_pcr *pcr)
  420. {
  421. rtl8411_init_common_params(pcr);
  422. pcr->ops = &rtl8402_pcr_ops;
  423. set_pull_ctrl_tables(pcr, rtl8411);
  424. }