alcor_pci.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
  4. *
  5. * Driver for Alcor Micro AU6601 and AU6621 controllers
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/irq.h>
  11. #include <linux/mfd/core.h>
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm.h>
  16. #include <linux/alcor_pci.h>
  17. #define DRV_NAME_ALCOR_PCI "alcor_pci"
  18. static DEFINE_IDA(alcor_pci_idr);
  19. static struct mfd_cell alcor_pci_cells[] = {
  20. [ALCOR_SD_CARD] = {
  21. .name = DRV_NAME_ALCOR_PCI_SDMMC,
  22. },
  23. [ALCOR_MS_CARD] = {
  24. .name = DRV_NAME_ALCOR_PCI_MS,
  25. },
  26. };
  27. static const struct alcor_dev_cfg alcor_cfg = {
  28. .dma = 0,
  29. };
  30. static const struct alcor_dev_cfg au6621_cfg = {
  31. .dma = 1,
  32. };
  33. static const struct alcor_dev_cfg au6625_cfg = {
  34. .dma = 0,
  35. };
  36. static const struct pci_device_id pci_ids[] = {
  37. { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6601),
  38. .driver_data = (kernel_ulong_t)&alcor_cfg },
  39. { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6621),
  40. .driver_data = (kernel_ulong_t)&au6621_cfg },
  41. { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6625),
  42. .driver_data = (kernel_ulong_t)&au6625_cfg },
  43. {},
  44. };
  45. MODULE_DEVICE_TABLE(pci, pci_ids);
  46. void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr)
  47. {
  48. writeb(val, priv->iobase + addr);
  49. }
  50. EXPORT_SYMBOL_GPL(alcor_write8);
  51. void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr)
  52. {
  53. writew(val, priv->iobase + addr);
  54. }
  55. EXPORT_SYMBOL_GPL(alcor_write16);
  56. void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
  57. {
  58. writel(val, priv->iobase + addr);
  59. }
  60. EXPORT_SYMBOL_GPL(alcor_write32);
  61. void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
  62. {
  63. iowrite32be(val, priv->iobase + addr);
  64. }
  65. EXPORT_SYMBOL_GPL(alcor_write32be);
  66. u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr)
  67. {
  68. return readb(priv->iobase + addr);
  69. }
  70. EXPORT_SYMBOL_GPL(alcor_read8);
  71. u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr)
  72. {
  73. return readl(priv->iobase + addr);
  74. }
  75. EXPORT_SYMBOL_GPL(alcor_read32);
  76. u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr)
  77. {
  78. return ioread32be(priv->iobase + addr);
  79. }
  80. EXPORT_SYMBOL_GPL(alcor_read32be);
  81. static int alcor_pci_find_cap_offset(struct alcor_pci_priv *priv,
  82. struct pci_dev *pci)
  83. {
  84. int where;
  85. u8 val8;
  86. u32 val32;
  87. where = ALCOR_CAP_START_OFFSET;
  88. pci_read_config_byte(pci, where, &val8);
  89. if (!val8)
  90. return 0;
  91. where = (int)val8;
  92. while (1) {
  93. pci_read_config_dword(pci, where, &val32);
  94. if (val32 == 0xffffffff) {
  95. dev_dbg(priv->dev, "find_cap_offset invalid value %x.\n",
  96. val32);
  97. return 0;
  98. }
  99. if ((val32 & 0xff) == 0x10) {
  100. dev_dbg(priv->dev, "pcie cap offset: %x\n", where);
  101. return where;
  102. }
  103. if ((val32 & 0xff00) == 0x00) {
  104. dev_dbg(priv->dev, "pci_find_cap_offset invalid value %x.\n",
  105. val32);
  106. break;
  107. }
  108. where = (int)((val32 >> 8) & 0xff);
  109. }
  110. return 0;
  111. }
  112. static void alcor_pci_init_check_aspm(struct alcor_pci_priv *priv)
  113. {
  114. struct pci_dev *pci;
  115. int where;
  116. u32 val32;
  117. priv->pdev_cap_off = alcor_pci_find_cap_offset(priv, priv->pdev);
  118. /*
  119. * A device might be attached to root complex directly and
  120. * priv->parent_pdev will be NULL. In this case we don't check its
  121. * capability and disable ASPM completely.
  122. */
  123. if (priv->parent_pdev)
  124. priv->parent_cap_off = alcor_pci_find_cap_offset(priv,
  125. priv->parent_pdev);
  126. if ((priv->pdev_cap_off == 0) || (priv->parent_cap_off == 0)) {
  127. dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
  128. priv->pdev_cap_off, priv->parent_cap_off);
  129. return;
  130. }
  131. /* link capability */
  132. pci = priv->pdev;
  133. where = priv->pdev_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
  134. pci_read_config_dword(pci, where, &val32);
  135. priv->pdev_aspm_cap = (u8)(val32 >> 10) & 0x03;
  136. pci = priv->parent_pdev;
  137. where = priv->parent_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
  138. pci_read_config_dword(pci, where, &val32);
  139. priv->parent_aspm_cap = (u8)(val32 >> 10) & 0x03;
  140. if (priv->pdev_aspm_cap != priv->parent_aspm_cap) {
  141. u8 aspm_cap;
  142. dev_dbg(priv->dev, "pdev_aspm_cap: %x, parent_aspm_cap: %x\n",
  143. priv->pdev_aspm_cap, priv->parent_aspm_cap);
  144. aspm_cap = priv->pdev_aspm_cap & priv->parent_aspm_cap;
  145. priv->pdev_aspm_cap = aspm_cap;
  146. priv->parent_aspm_cap = aspm_cap;
  147. }
  148. dev_dbg(priv->dev, "ext_config_dev_aspm: %x, pdev_aspm_cap: %x\n",
  149. priv->ext_config_dev_aspm, priv->pdev_aspm_cap);
  150. priv->ext_config_dev_aspm &= priv->pdev_aspm_cap;
  151. }
  152. static void alcor_pci_aspm_ctrl(struct alcor_pci_priv *priv, u8 aspm_enable)
  153. {
  154. struct pci_dev *pci;
  155. u8 aspm_ctrl, i;
  156. int where;
  157. u32 val32;
  158. if ((!priv->pdev_cap_off) || (!priv->parent_cap_off)) {
  159. dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
  160. priv->pdev_cap_off, priv->parent_cap_off);
  161. return;
  162. }
  163. if (!priv->pdev_aspm_cap)
  164. return;
  165. aspm_ctrl = 0;
  166. if (aspm_enable) {
  167. aspm_ctrl = priv->ext_config_dev_aspm;
  168. if (!aspm_ctrl) {
  169. dev_dbg(priv->dev, "aspm_ctrl == 0\n");
  170. return;
  171. }
  172. }
  173. for (i = 0; i < 2; i++) {
  174. if (i) {
  175. pci = priv->parent_pdev;
  176. where = priv->parent_cap_off
  177. + ALCOR_PCIE_LINK_CTRL_OFFSET;
  178. } else {
  179. pci = priv->pdev;
  180. where = priv->pdev_cap_off
  181. + ALCOR_PCIE_LINK_CTRL_OFFSET;
  182. }
  183. pci_read_config_dword(pci, where, &val32);
  184. val32 &= (~0x03);
  185. val32 |= (aspm_ctrl & priv->pdev_aspm_cap);
  186. pci_write_config_byte(pci, where, (u8)val32);
  187. }
  188. }
  189. static inline void alcor_mask_sd_irqs(struct alcor_pci_priv *priv)
  190. {
  191. alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
  192. }
  193. static inline void alcor_unmask_sd_irqs(struct alcor_pci_priv *priv)
  194. {
  195. alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
  196. AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
  197. AU6601_INT_OVER_CURRENT_ERR,
  198. AU6601_REG_INT_ENABLE);
  199. }
  200. static inline void alcor_mask_ms_irqs(struct alcor_pci_priv *priv)
  201. {
  202. alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
  203. }
  204. static inline void alcor_unmask_ms_irqs(struct alcor_pci_priv *priv)
  205. {
  206. alcor_write32(priv, 0x3d00fa, AU6601_MS_INT_ENABLE);
  207. }
  208. static int alcor_pci_probe(struct pci_dev *pdev,
  209. const struct pci_device_id *ent)
  210. {
  211. struct alcor_dev_cfg *cfg;
  212. struct alcor_pci_priv *priv;
  213. int ret, i, bar = 0;
  214. cfg = (void *)ent->driver_data;
  215. ret = pcim_enable_device(pdev);
  216. if (ret)
  217. return ret;
  218. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  219. if (!priv)
  220. return -ENOMEM;
  221. ret = ida_alloc(&alcor_pci_idr, GFP_KERNEL);
  222. if (ret < 0)
  223. return ret;
  224. priv->id = ret;
  225. priv->pdev = pdev;
  226. priv->parent_pdev = pdev->bus->self;
  227. priv->dev = &pdev->dev;
  228. priv->cfg = cfg;
  229. priv->irq = pdev->irq;
  230. ret = pci_request_regions(pdev, DRV_NAME_ALCOR_PCI);
  231. if (ret) {
  232. dev_err(&pdev->dev, "Cannot request region\n");
  233. ret = -ENOMEM;
  234. goto error_free_ida;
  235. }
  236. if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
  237. dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
  238. ret = -ENODEV;
  239. goto error_release_regions;
  240. }
  241. priv->iobase = pcim_iomap(pdev, bar, 0);
  242. if (!priv->iobase) {
  243. ret = -ENOMEM;
  244. goto error_release_regions;
  245. }
  246. /* make sure irqs are disabled */
  247. alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
  248. alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
  249. ret = dma_set_mask_and_coherent(priv->dev, AU6601_SDMA_MASK);
  250. if (ret) {
  251. dev_err(priv->dev, "Failed to set DMA mask\n");
  252. goto error_release_regions;
  253. }
  254. pci_set_master(pdev);
  255. pci_set_drvdata(pdev, priv);
  256. alcor_pci_init_check_aspm(priv);
  257. for (i = 0; i < ARRAY_SIZE(alcor_pci_cells); i++) {
  258. alcor_pci_cells[i].platform_data = priv;
  259. alcor_pci_cells[i].pdata_size = sizeof(*priv);
  260. }
  261. ret = mfd_add_devices(&pdev->dev, priv->id, alcor_pci_cells,
  262. ARRAY_SIZE(alcor_pci_cells), NULL, 0, NULL);
  263. if (ret < 0)
  264. goto error_release_regions;
  265. alcor_pci_aspm_ctrl(priv, 0);
  266. return 0;
  267. error_release_regions:
  268. pci_release_regions(pdev);
  269. error_free_ida:
  270. ida_free(&alcor_pci_idr, priv->id);
  271. return ret;
  272. }
  273. static void alcor_pci_remove(struct pci_dev *pdev)
  274. {
  275. struct alcor_pci_priv *priv;
  276. priv = pci_get_drvdata(pdev);
  277. alcor_pci_aspm_ctrl(priv, 1);
  278. mfd_remove_devices(&pdev->dev);
  279. ida_free(&alcor_pci_idr, priv->id);
  280. pci_release_regions(pdev);
  281. pci_set_drvdata(pdev, NULL);
  282. }
  283. #ifdef CONFIG_PM_SLEEP
  284. static int alcor_suspend(struct device *dev)
  285. {
  286. struct alcor_pci_priv *priv = dev_get_drvdata(dev);
  287. alcor_pci_aspm_ctrl(priv, 1);
  288. return 0;
  289. }
  290. static int alcor_resume(struct device *dev)
  291. {
  292. struct alcor_pci_priv *priv = dev_get_drvdata(dev);
  293. alcor_pci_aspm_ctrl(priv, 0);
  294. return 0;
  295. }
  296. #endif /* CONFIG_PM_SLEEP */
  297. static SIMPLE_DEV_PM_OPS(alcor_pci_pm_ops, alcor_suspend, alcor_resume);
  298. static struct pci_driver alcor_driver = {
  299. .name = DRV_NAME_ALCOR_PCI,
  300. .id_table = pci_ids,
  301. .probe = alcor_pci_probe,
  302. .remove = alcor_pci_remove,
  303. .driver = {
  304. .pm = &alcor_pci_pm_ops
  305. },
  306. };
  307. module_pci_driver(alcor_driver);
  308. MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
  309. MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
  310. MODULE_LICENSE("GPL");