wm8994-regmap.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8994-regmap.c -- Register map data for WM8994 series devices
  4. *
  5. * Copyright 2011 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/mfd/wm8994/core.h>
  10. #include <linux/mfd/wm8994/registers.h>
  11. #include <linux/regmap.h>
  12. #include <linux/device.h>
  13. #include "wm8994.h"
  14. static const struct reg_default wm1811_defaults[] = {
  15. { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
  16. { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
  17. { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
  18. { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
  19. { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
  20. { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
  21. { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
  22. { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
  23. { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
  24. { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
  25. { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
  26. { 0x001C, 0x006D }, /* R28 - Left Output Volume */
  27. { 0x001D, 0x006D }, /* R29 - Right Output Volume */
  28. { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
  29. { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
  30. { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
  31. { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
  32. { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
  33. { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
  34. { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
  35. { 0x0025, 0x0140 }, /* R37 - ClassD */
  36. { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
  37. { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
  38. { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
  39. { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
  40. { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
  41. { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
  42. { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
  43. { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
  44. { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
  45. { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
  46. { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
  47. { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
  48. { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
  49. { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
  50. { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
  51. { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
  52. { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
  53. { 0x0037, 0x0000 }, /* R55 - Additional Control */
  54. { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
  55. { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
  56. { 0x003B, 0x000D }, /* R59 - LDO 1 */
  57. { 0x003C, 0x0003 }, /* R60 - LDO 2 */
  58. { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
  59. { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
  60. { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
  61. { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
  62. { 0x0051, 0x0004 }, /* R81 - Class W (1) */
  63. { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
  64. { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */
  65. { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
  66. { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
  67. { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */
  68. { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
  69. { 0x0101, 0x8004 }, /* R257 - Control Interface */
  70. { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
  71. { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
  72. { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
  73. { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
  74. { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
  75. { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
  76. { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
  77. { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
  78. { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
  79. { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
  80. { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
  81. { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
  82. { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
  83. { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
  84. { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
  85. { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
  86. { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
  87. { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
  88. { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
  89. { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
  90. { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
  91. { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
  92. { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
  93. { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
  94. { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
  95. { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
  96. { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
  97. { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
  98. { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
  99. { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
  100. { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
  101. { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
  102. { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
  103. { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
  104. { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
  105. { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
  106. { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
  107. { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
  108. { 0x0318, 0x0003 }, /* R792 - AIF2TX Control */
  109. { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
  110. { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
  111. { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
  112. { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
  113. { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
  114. { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
  115. { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
  116. { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
  117. { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
  118. { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
  119. { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
  120. { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
  121. { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
  122. { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
  123. { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
  124. { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
  125. { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
  126. { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
  127. { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
  128. { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
  129. { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
  130. { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
  131. { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
  132. { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
  133. { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
  134. { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
  135. { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
  136. { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
  137. { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
  138. { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
  139. { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
  140. { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
  141. { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
  142. { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
  143. { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
  144. { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
  145. { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
  146. { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
  147. { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
  148. { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
  149. { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
  150. { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
  151. { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
  152. { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
  153. { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
  154. { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
  155. { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
  156. { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
  157. { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
  158. { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
  159. { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
  160. { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
  161. { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
  162. { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
  163. { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
  164. { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
  165. { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
  166. { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
  167. { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
  168. { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
  169. { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
  170. { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
  171. { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
  172. { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
  173. { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
  174. { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
  175. { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
  176. { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2 EQ Band 1 C */
  177. { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
  178. { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
  179. { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
  180. { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
  181. { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
  182. { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
  183. { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
  184. { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
  185. { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
  186. { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
  187. { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
  188. { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
  189. { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
  190. { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
  191. { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
  192. { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
  193. { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
  194. { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
  195. { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
  196. { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
  197. { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
  198. { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
  199. { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
  200. { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
  201. { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
  202. { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
  203. { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
  204. { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
  205. { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
  206. { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
  207. { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
  208. { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
  209. { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
  210. { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
  211. { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
  212. { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
  213. { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
  214. { 0x0603, 0x0000 }, /* R1539 - AIF2ADC Mixer Volumes */
  215. { 0x0604, 0x0000 }, /* R1540 - AIF2ADC Left Mixer Routing */
  216. { 0x0605, 0x0000 }, /* R1541 - AIF2ADC Right Mixer Routing */
  217. { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
  218. { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
  219. { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
  220. { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right Mixer Routing */
  221. { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
  222. { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
  223. { 0x0612, 0x02C0 }, /* R1554 - AIF2TX Left Volume */
  224. { 0x0613, 0x02C0 }, /* R1555 - AIF2TX Right Volume */
  225. { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
  226. { 0x0620, 0x0002 }, /* R1568 - Oversampling */
  227. { 0x0621, 0x0000 }, /* R1569 - Sidetone */
  228. { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
  229. { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
  230. { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
  231. { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
  232. { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
  233. { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
  234. { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
  235. { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
  236. { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
  237. { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
  238. { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
  239. { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */
  240. { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
  241. { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */
  242. { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
  243. { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
  244. };
  245. static const struct reg_default wm8994_defaults[] = {
  246. { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
  247. { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
  248. { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
  249. { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
  250. { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
  251. { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
  252. { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
  253. { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
  254. { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
  255. { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
  256. { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
  257. { 0x001C, 0x006D }, /* R28 - Left Output Volume */
  258. { 0x001D, 0x006D }, /* R29 - Right Output Volume */
  259. { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
  260. { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
  261. { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
  262. { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
  263. { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
  264. { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
  265. { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
  266. { 0x0025, 0x0140 }, /* R37 - ClassD */
  267. { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
  268. { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
  269. { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
  270. { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
  271. { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
  272. { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
  273. { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
  274. { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
  275. { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
  276. { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
  277. { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
  278. { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
  279. { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
  280. { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
  281. { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
  282. { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
  283. { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
  284. { 0x0037, 0x0000 }, /* R55 - Additional Control */
  285. { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
  286. { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
  287. { 0x003A, 0x0000 }, /* R58 - MICBIAS */
  288. { 0x003B, 0x000D }, /* R59 - LDO 1 */
  289. { 0x003C, 0x0003 }, /* R60 - LDO 2 */
  290. { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
  291. { 0x0051, 0x0004 }, /* R81 - Class W (1) */
  292. { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
  293. { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
  294. { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
  295. { 0x0101, 0x8004 }, /* R257 - Control Interface */
  296. { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
  297. { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
  298. { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
  299. { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
  300. { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
  301. { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
  302. { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
  303. { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
  304. { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
  305. { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
  306. { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
  307. { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
  308. { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
  309. { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
  310. { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
  311. { 0x0240, 0x0000 }, /* R576 - FLL2 Control (1) */
  312. { 0x0241, 0x0000 }, /* R577 - FLL2 Control (2) */
  313. { 0x0242, 0x0000 }, /* R578 - FLL2 Control (3) */
  314. { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
  315. { 0x0244, 0x0C80 }, /* R580 - FLL2 Control (5) */
  316. { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
  317. { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
  318. { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
  319. { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
  320. { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
  321. { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
  322. { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
  323. { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
  324. { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
  325. { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
  326. { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
  327. { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
  328. { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
  329. { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
  330. { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
  331. { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
  332. { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
  333. { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
  334. { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
  335. { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
  336. { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
  337. { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
  338. { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
  339. { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
  340. { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
  341. { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
  342. { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
  343. { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
  344. { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
  345. { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
  346. { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
  347. { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
  348. { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
  349. { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
  350. { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
  351. { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
  352. { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
  353. { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
  354. { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
  355. { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
  356. { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
  357. { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
  358. { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
  359. { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
  360. { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
  361. { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
  362. { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
  363. { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
  364. { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
  365. { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
  366. { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
  367. { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
  368. { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
  369. { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
  370. { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
  371. { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
  372. { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
  373. { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
  374. { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
  375. { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
  376. { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
  377. { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
  378. { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
  379. { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
  380. { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
  381. { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
  382. { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
  383. { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
  384. { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
  385. { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
  386. { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
  387. { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
  388. { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
  389. { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
  390. { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
  391. { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
  392. { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
  393. { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
  394. { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
  395. { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
  396. { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
  397. { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
  398. { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
  399. { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
  400. { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
  401. { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
  402. { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
  403. { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
  404. { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
  405. { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
  406. { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
  407. { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
  408. { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
  409. { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
  410. { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
  411. { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
  412. { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
  413. { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
  414. { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
  415. { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
  416. { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
  417. { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
  418. { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
  419. { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
  420. { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
  421. { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
  422. { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
  423. { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
  424. { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
  425. { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
  426. { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
  427. { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
  428. { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
  429. { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
  430. { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
  431. { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
  432. { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
  433. { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
  434. { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
  435. { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
  436. { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
  437. { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
  438. { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
  439. { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
  440. { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
  441. { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
  442. { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
  443. { 0x0620, 0x0002 }, /* R1568 - Oversampling */
  444. { 0x0621, 0x0000 }, /* R1569 - Sidetone */
  445. { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
  446. { 0x0701, 0xA101 }, /* R1793 - GPIO 2 */
  447. { 0x0702, 0xA101 }, /* R1794 - GPIO 3 */
  448. { 0x0703, 0xA101 }, /* R1795 - GPIO 4 */
  449. { 0x0704, 0xA101 }, /* R1796 - GPIO 5 */
  450. { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
  451. { 0x0706, 0xA101 }, /* R1798 - GPIO 7 */
  452. { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
  453. { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
  454. { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
  455. { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
  456. { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
  457. { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
  458. { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
  459. { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */
  460. { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
  461. { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
  462. };
  463. static const struct reg_default wm8958_defaults[] = {
  464. { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
  465. { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
  466. { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
  467. { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
  468. { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
  469. { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
  470. { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
  471. { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
  472. { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
  473. { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
  474. { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
  475. { 0x001C, 0x006D }, /* R28 - Left Output Volume */
  476. { 0x001D, 0x006D }, /* R29 - Right Output Volume */
  477. { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
  478. { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
  479. { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
  480. { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
  481. { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
  482. { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
  483. { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
  484. { 0x0025, 0x0140 }, /* R37 - ClassD */
  485. { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
  486. { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
  487. { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
  488. { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
  489. { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
  490. { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
  491. { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
  492. { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
  493. { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
  494. { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
  495. { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
  496. { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
  497. { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
  498. { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
  499. { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
  500. { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
  501. { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
  502. { 0x0037, 0x0000 }, /* R55 - Additional Control */
  503. { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
  504. { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */
  505. { 0x003B, 0x000D }, /* R59 - LDO 1 */
  506. { 0x003C, 0x0005 }, /* R60 - LDO 2 */
  507. { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
  508. { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
  509. { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
  510. { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
  511. { 0x0051, 0x0004 }, /* R81 - Class W (1) */
  512. { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
  513. { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
  514. { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
  515. { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
  516. { 0x00D0, 0x5600 }, /* R208 - Mic Detect 1 */
  517. { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
  518. { 0x0101, 0x8004 }, /* R257 - Control Interface */
  519. { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
  520. { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
  521. { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
  522. { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
  523. { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
  524. { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
  525. { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
  526. { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
  527. { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
  528. { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
  529. { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
  530. { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
  531. { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
  532. { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
  533. { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
  534. { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
  535. { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
  536. { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
  537. { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
  538. { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
  539. { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
  540. { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
  541. { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
  542. { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
  543. { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
  544. { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
  545. { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
  546. { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
  547. { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
  548. { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
  549. { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
  550. { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
  551. { 0x0310, 0x4053 }, /* R784 - AIF2 Control (1) */
  552. { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
  553. { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
  554. { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
  555. { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
  556. { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
  557. { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
  558. { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
  559. { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
  560. { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
  561. { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
  562. { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
  563. { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
  564. { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
  565. { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
  566. { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
  567. { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
  568. { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
  569. { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
  570. { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
  571. { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
  572. { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
  573. { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
  574. { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
  575. { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
  576. { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
  577. { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
  578. { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
  579. { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
  580. { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
  581. { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
  582. { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
  583. { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
  584. { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
  585. { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
  586. { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
  587. { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
  588. { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
  589. { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
  590. { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
  591. { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
  592. { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
  593. { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
  594. { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
  595. { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
  596. { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
  597. { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
  598. { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
  599. { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
  600. { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
  601. { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
  602. { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
  603. { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
  604. { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
  605. { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
  606. { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
  607. { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
  608. { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
  609. { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
  610. { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
  611. { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
  612. { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
  613. { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
  614. { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
  615. { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
  616. { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
  617. { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
  618. { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
  619. { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
  620. { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
  621. { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
  622. { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
  623. { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
  624. { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
  625. { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
  626. { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
  627. { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
  628. { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
  629. { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
  630. { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2EQ Band 1 C */
  631. { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
  632. { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
  633. { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
  634. { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
  635. { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
  636. { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
  637. { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
  638. { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
  639. { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
  640. { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
  641. { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
  642. { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
  643. { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
  644. { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
  645. { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
  646. { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
  647. { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
  648. { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
  649. { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
  650. { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
  651. { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
  652. { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
  653. { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
  654. { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
  655. { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
  656. { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
  657. { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
  658. { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
  659. { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
  660. { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
  661. { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
  662. { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
  663. { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
  664. { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
  665. { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
  666. { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
  667. { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
  668. { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
  669. { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
  670. { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
  671. { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
  672. { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
  673. { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
  674. { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
  675. { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
  676. { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
  677. { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
  678. { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
  679. { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
  680. { 0x0620, 0x0002 }, /* R1568 - Oversampling */
  681. { 0x0621, 0x0000 }, /* R1569 - Sidetone */
  682. { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
  683. { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
  684. { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
  685. { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
  686. { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
  687. { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
  688. { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
  689. { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
  690. { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
  691. { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
  692. { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
  693. { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
  694. { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
  695. { 0x0739, 0xFFEF }, /* R1849 - Interrupt Status 2 Mask */
  696. { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
  697. { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
  698. { 0x0900, 0x1C00 }, /* R2304 - DSP2_Program */
  699. { 0x0901, 0x0000 }, /* R2305 - DSP2_Config */
  700. { 0x0A0D, 0x0000 }, /* R2573 - DSP2_ExecControl */
  701. { 0x2400, 0x003F }, /* R9216 - MBC Band 1 K (1) */
  702. { 0x2401, 0x8BD8 }, /* R9217 - MBC Band 1 K (2) */
  703. { 0x2402, 0x0032 }, /* R9218 - MBC Band 1 N1 (1) */
  704. { 0x2403, 0xF52D }, /* R9219 - MBC Band 1 N1 (2) */
  705. { 0x2404, 0x0065 }, /* R9220 - MBC Band 1 N2 (1) */
  706. { 0x2405, 0xAC8C }, /* R9221 - MBC Band 1 N2 (2) */
  707. { 0x2406, 0x006B }, /* R9222 - MBC Band 1 N3 (1) */
  708. { 0x2407, 0xE087 }, /* R9223 - MBC Band 1 N3 (2) */
  709. { 0x2408, 0x0072 }, /* R9224 - MBC Band 1 N4 (1) */
  710. { 0x2409, 0x1483 }, /* R9225 - MBC Band 1 N4 (2) */
  711. { 0x240A, 0x0072 }, /* R9226 - MBC Band 1 N5 (1) */
  712. { 0x240B, 0x1483 }, /* R9227 - MBC Band 1 N5 (2) */
  713. { 0x240C, 0x0043 }, /* R9228 - MBC Band 1 X1 (1) */
  714. { 0x240D, 0x3525 }, /* R9229 - MBC Band 1 X1 (2) */
  715. { 0x240E, 0x0006 }, /* R9230 - MBC Band 1 X2 (1) */
  716. { 0x240F, 0x6A4A }, /* R9231 - MBC Band 1 X2 (2) */
  717. { 0x2410, 0x0043 }, /* R9232 - MBC Band 1 X3 (1) */
  718. { 0x2411, 0x6079 }, /* R9233 - MBC Band 1 X3 (2) */
  719. { 0x2412, 0x000C }, /* R9234 - MBC Band 1 Attack (1) */
  720. { 0x2413, 0xCCCD }, /* R9235 - MBC Band 1 Attack (2) */
  721. { 0x2414, 0x0000 }, /* R9236 - MBC Band 1 Decay (1) */
  722. { 0x2415, 0x0800 }, /* R9237 - MBC Band 1 Decay (2) */
  723. { 0x2416, 0x003F }, /* R9238 - MBC Band 2 K (1) */
  724. { 0x2417, 0x8BD8 }, /* R9239 - MBC Band 2 K (2) */
  725. { 0x2418, 0x0032 }, /* R9240 - MBC Band 2 N1 (1) */
  726. { 0x2419, 0xF52D }, /* R9241 - MBC Band 2 N1 (2) */
  727. { 0x241A, 0x0065 }, /* R9242 - MBC Band 2 N2 (1) */
  728. { 0x241B, 0xAC8C }, /* R9243 - MBC Band 2 N2 (2) */
  729. { 0x241C, 0x006B }, /* R9244 - MBC Band 2 N3 (1) */
  730. { 0x241D, 0xE087 }, /* R9245 - MBC Band 2 N3 (2) */
  731. { 0x241E, 0x0072 }, /* R9246 - MBC Band 2 N4 (1) */
  732. { 0x241F, 0x1483 }, /* R9247 - MBC Band 2 N4 (2) */
  733. { 0x2420, 0x0072 }, /* R9248 - MBC Band 2 N5 (1) */
  734. { 0x2421, 0x1483 }, /* R9249 - MBC Band 2 N5 (2) */
  735. { 0x2422, 0x0043 }, /* R9250 - MBC Band 2 X1 (1) */
  736. { 0x2423, 0x3525 }, /* R9251 - MBC Band 2 X1 (2) */
  737. { 0x2424, 0x0006 }, /* R9252 - MBC Band 2 X2 (1) */
  738. { 0x2425, 0x6A4A }, /* R9253 - MBC Band 2 X2 (2) */
  739. { 0x2426, 0x0043 }, /* R9254 - MBC Band 2 X3 (1) */
  740. { 0x2427, 0x6079 }, /* R9255 - MBC Band 2 X3 (2) */
  741. { 0x2428, 0x000C }, /* R9256 - MBC Band 2 Attack (1) */
  742. { 0x2429, 0xCCCD }, /* R9257 - MBC Band 2 Attack (2) */
  743. { 0x242A, 0x0000 }, /* R9258 - MBC Band 2 Decay (1) */
  744. { 0x242B, 0x0800 }, /* R9259 - MBC Band 2 Decay (2) */
  745. { 0x242C, 0x005A }, /* R9260 - MBC_B2_PG2 (1) */
  746. { 0x242D, 0x7EFA }, /* R9261 - MBC_B2_PG2 (2) */
  747. { 0x242E, 0x005A }, /* R9262 - MBC_B1_PG2 (1) */
  748. { 0x242F, 0x7EFA }, /* R9263 - MBC_B1_PG2 (2) */
  749. { 0x2600, 0x00A7 }, /* R9728 - MBC Crossover (1) */
  750. { 0x2601, 0x0D1C }, /* R9729 - MBC Crossover (2) */
  751. { 0x2602, 0x0083 }, /* R9730 - MBC HPF (1) */
  752. { 0x2603, 0x98AD }, /* R9731 - MBC HPF (2) */
  753. { 0x2606, 0x0008 }, /* R9734 - MBC LPF (1) */
  754. { 0x2607, 0xE7A2 }, /* R9735 - MBC LPF (2) */
  755. { 0x260A, 0x0055 }, /* R9738 - MBC RMS Limit (1) */
  756. { 0x260B, 0x8C4B }, /* R9739 - MBC RMS Limit (2) */
  757. };
  758. static bool wm1811_readable_register(struct device *dev, unsigned int reg)
  759. {
  760. switch (reg) {
  761. case WM8994_SOFTWARE_RESET:
  762. case WM8994_POWER_MANAGEMENT_1:
  763. case WM8994_POWER_MANAGEMENT_2:
  764. case WM8994_POWER_MANAGEMENT_3:
  765. case WM8994_POWER_MANAGEMENT_4:
  766. case WM8994_POWER_MANAGEMENT_5:
  767. case WM8994_POWER_MANAGEMENT_6:
  768. case WM8994_INPUT_MIXER_1:
  769. case WM8994_LEFT_LINE_INPUT_1_2_VOLUME:
  770. case WM8994_LEFT_LINE_INPUT_3_4_VOLUME:
  771. case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME:
  772. case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME:
  773. case WM8994_LEFT_OUTPUT_VOLUME:
  774. case WM8994_RIGHT_OUTPUT_VOLUME:
  775. case WM8994_LINE_OUTPUTS_VOLUME:
  776. case WM8994_HPOUT2_VOLUME:
  777. case WM8994_LEFT_OPGA_VOLUME:
  778. case WM8994_RIGHT_OPGA_VOLUME:
  779. case WM8994_SPKMIXL_ATTENUATION:
  780. case WM8994_SPKMIXR_ATTENUATION:
  781. case WM8994_SPKOUT_MIXERS:
  782. case WM8994_CLASSD:
  783. case WM8994_SPEAKER_VOLUME_LEFT:
  784. case WM8994_SPEAKER_VOLUME_RIGHT:
  785. case WM8994_INPUT_MIXER_2:
  786. case WM8994_INPUT_MIXER_3:
  787. case WM8994_INPUT_MIXER_4:
  788. case WM8994_INPUT_MIXER_5:
  789. case WM8994_INPUT_MIXER_6:
  790. case WM8994_OUTPUT_MIXER_1:
  791. case WM8994_OUTPUT_MIXER_2:
  792. case WM8994_OUTPUT_MIXER_3:
  793. case WM8994_OUTPUT_MIXER_4:
  794. case WM8994_OUTPUT_MIXER_5:
  795. case WM8994_OUTPUT_MIXER_6:
  796. case WM8994_HPOUT2_MIXER:
  797. case WM8994_LINE_MIXER_1:
  798. case WM8994_LINE_MIXER_2:
  799. case WM8994_SPEAKER_MIXER:
  800. case WM8994_ADDITIONAL_CONTROL:
  801. case WM8994_ANTIPOP_1:
  802. case WM8994_ANTIPOP_2:
  803. case WM8994_LDO_1:
  804. case WM8994_LDO_2:
  805. case WM8958_MICBIAS1:
  806. case WM8958_MICBIAS2:
  807. case WM8994_CHARGE_PUMP_1:
  808. case WM8958_CHARGE_PUMP_2:
  809. case WM8994_CLASS_W_1:
  810. case WM8994_DC_SERVO_1:
  811. case WM8994_DC_SERVO_2:
  812. case WM8994_DC_SERVO_READBACK:
  813. case WM8994_DC_SERVO_4:
  814. case WM8994_DC_SERVO_4E:
  815. case WM8994_ANALOGUE_HP_1:
  816. case WM8958_MIC_DETECT_1:
  817. case WM8958_MIC_DETECT_2:
  818. case WM8958_MIC_DETECT_3:
  819. case WM8994_CHIP_REVISION:
  820. case WM8994_CONTROL_INTERFACE:
  821. case WM8994_AIF1_CLOCKING_1:
  822. case WM8994_AIF1_CLOCKING_2:
  823. case WM8994_AIF2_CLOCKING_1:
  824. case WM8994_AIF2_CLOCKING_2:
  825. case WM8994_CLOCKING_1:
  826. case WM8994_CLOCKING_2:
  827. case WM8994_AIF1_RATE:
  828. case WM8994_AIF2_RATE:
  829. case WM8994_RATE_STATUS:
  830. case WM8994_FLL1_CONTROL_1:
  831. case WM8994_FLL1_CONTROL_2:
  832. case WM8994_FLL1_CONTROL_3:
  833. case WM8994_FLL1_CONTROL_4:
  834. case WM8994_FLL1_CONTROL_5:
  835. case WM8958_FLL1_EFS_1:
  836. case WM8958_FLL1_EFS_2:
  837. case WM8994_FLL2_CONTROL_1:
  838. case WM8994_FLL2_CONTROL_2:
  839. case WM8994_FLL2_CONTROL_3:
  840. case WM8994_FLL2_CONTROL_4:
  841. case WM8994_FLL2_CONTROL_5:
  842. case WM8958_FLL2_EFS_1:
  843. case WM8958_FLL2_EFS_2:
  844. case WM8994_AIF1_CONTROL_1:
  845. case WM8994_AIF1_CONTROL_2:
  846. case WM8994_AIF1_MASTER_SLAVE:
  847. case WM8994_AIF1_BCLK:
  848. case WM8994_AIF1ADC_LRCLK:
  849. case WM8994_AIF1DAC_LRCLK:
  850. case WM8994_AIF1DAC_DATA:
  851. case WM8994_AIF1ADC_DATA:
  852. case WM8994_AIF2_CONTROL_1:
  853. case WM8994_AIF2_CONTROL_2:
  854. case WM8994_AIF2_MASTER_SLAVE:
  855. case WM8994_AIF2_BCLK:
  856. case WM8994_AIF2ADC_LRCLK:
  857. case WM8994_AIF2DAC_LRCLK:
  858. case WM8994_AIF2DAC_DATA:
  859. case WM8994_AIF2ADC_DATA:
  860. case WM1811_AIF2TX_CONTROL:
  861. case WM8958_AIF3_CONTROL_1:
  862. case WM8958_AIF3_CONTROL_2:
  863. case WM8958_AIF3DAC_DATA:
  864. case WM8958_AIF3ADC_DATA:
  865. case WM8994_AIF1_ADC1_LEFT_VOLUME:
  866. case WM8994_AIF1_ADC1_RIGHT_VOLUME:
  867. case WM8994_AIF1_DAC1_LEFT_VOLUME:
  868. case WM8994_AIF1_DAC1_RIGHT_VOLUME:
  869. case WM8994_AIF1_ADC1_FILTERS:
  870. case WM8994_AIF1_ADC2_FILTERS:
  871. case WM8994_AIF1_DAC1_FILTERS_1:
  872. case WM8994_AIF1_DAC1_FILTERS_2:
  873. case WM8994_AIF1_DAC2_FILTERS_1:
  874. case WM8994_AIF1_DAC2_FILTERS_2:
  875. case WM8958_AIF1_DAC1_NOISE_GATE:
  876. case WM8958_AIF1_DAC2_NOISE_GATE:
  877. case WM8994_AIF1_DRC1_1:
  878. case WM8994_AIF1_DRC1_2:
  879. case WM8994_AIF1_DRC1_3:
  880. case WM8994_AIF1_DRC1_4:
  881. case WM8994_AIF1_DRC1_5:
  882. case WM8994_AIF1_DRC2_1:
  883. case WM8994_AIF1_DRC2_2:
  884. case WM8994_AIF1_DRC2_3:
  885. case WM8994_AIF1_DRC2_4:
  886. case WM8994_AIF1_DRC2_5:
  887. case WM8994_AIF1_DAC1_EQ_GAINS_1:
  888. case WM8994_AIF1_DAC1_EQ_GAINS_2:
  889. case WM8994_AIF1_DAC1_EQ_BAND_1_A:
  890. case WM8994_AIF1_DAC1_EQ_BAND_1_B:
  891. case WM8994_AIF1_DAC1_EQ_BAND_1_PG:
  892. case WM8994_AIF1_DAC1_EQ_BAND_2_A:
  893. case WM8994_AIF1_DAC1_EQ_BAND_2_B:
  894. case WM8994_AIF1_DAC1_EQ_BAND_2_C:
  895. case WM8994_AIF1_DAC1_EQ_BAND_2_PG:
  896. case WM8994_AIF1_DAC1_EQ_BAND_3_A:
  897. case WM8994_AIF1_DAC1_EQ_BAND_3_B:
  898. case WM8994_AIF1_DAC1_EQ_BAND_3_C:
  899. case WM8994_AIF1_DAC1_EQ_BAND_3_PG:
  900. case WM8994_AIF1_DAC1_EQ_BAND_4_A:
  901. case WM8994_AIF1_DAC1_EQ_BAND_4_B:
  902. case WM8994_AIF1_DAC1_EQ_BAND_4_C:
  903. case WM8994_AIF1_DAC1_EQ_BAND_4_PG:
  904. case WM8994_AIF1_DAC1_EQ_BAND_5_A:
  905. case WM8994_AIF1_DAC1_EQ_BAND_5_B:
  906. case WM8994_AIF1_DAC1_EQ_BAND_5_PG:
  907. case WM8994_AIF1_DAC1_EQ_BAND_1_C:
  908. case WM8994_AIF1_DAC2_EQ_GAINS_1:
  909. case WM8994_AIF1_DAC2_EQ_GAINS_2:
  910. case WM8994_AIF1_DAC2_EQ_BAND_1_A:
  911. case WM8994_AIF1_DAC2_EQ_BAND_1_B:
  912. case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
  913. case WM8994_AIF1_DAC2_EQ_BAND_2_A:
  914. case WM8994_AIF1_DAC2_EQ_BAND_2_B:
  915. case WM8994_AIF1_DAC2_EQ_BAND_2_C:
  916. case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
  917. case WM8994_AIF1_DAC2_EQ_BAND_3_A:
  918. case WM8994_AIF1_DAC2_EQ_BAND_3_B:
  919. case WM8994_AIF1_DAC2_EQ_BAND_3_C:
  920. case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
  921. case WM8994_AIF1_DAC2_EQ_BAND_4_A:
  922. case WM8994_AIF1_DAC2_EQ_BAND_4_B:
  923. case WM8994_AIF1_DAC2_EQ_BAND_4_C:
  924. case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
  925. case WM8994_AIF1_DAC2_EQ_BAND_5_A:
  926. case WM8994_AIF1_DAC2_EQ_BAND_5_B:
  927. case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
  928. case WM8994_AIF1_DAC2_EQ_BAND_1_C:
  929. case WM8994_AIF2_ADC_LEFT_VOLUME:
  930. case WM8994_AIF2_ADC_RIGHT_VOLUME:
  931. case WM8994_AIF2_DAC_LEFT_VOLUME:
  932. case WM8994_AIF2_DAC_RIGHT_VOLUME:
  933. case WM8994_AIF2_ADC_FILTERS:
  934. case WM8994_AIF2_DAC_FILTERS_1:
  935. case WM8994_AIF2_DAC_FILTERS_2:
  936. case WM8958_AIF2_DAC_NOISE_GATE:
  937. case WM8994_AIF2_DRC_1:
  938. case WM8994_AIF2_DRC_2:
  939. case WM8994_AIF2_DRC_3:
  940. case WM8994_AIF2_DRC_4:
  941. case WM8994_AIF2_DRC_5:
  942. case WM8994_AIF2_EQ_GAINS_1:
  943. case WM8994_AIF2_EQ_GAINS_2:
  944. case WM8994_AIF2_EQ_BAND_1_A:
  945. case WM8994_AIF2_EQ_BAND_1_B:
  946. case WM8994_AIF2_EQ_BAND_1_PG:
  947. case WM8994_AIF2_EQ_BAND_2_A:
  948. case WM8994_AIF2_EQ_BAND_2_B:
  949. case WM8994_AIF2_EQ_BAND_2_C:
  950. case WM8994_AIF2_EQ_BAND_2_PG:
  951. case WM8994_AIF2_EQ_BAND_3_A:
  952. case WM8994_AIF2_EQ_BAND_3_B:
  953. case WM8994_AIF2_EQ_BAND_3_C:
  954. case WM8994_AIF2_EQ_BAND_3_PG:
  955. case WM8994_AIF2_EQ_BAND_4_A:
  956. case WM8994_AIF2_EQ_BAND_4_B:
  957. case WM8994_AIF2_EQ_BAND_4_C:
  958. case WM8994_AIF2_EQ_BAND_4_PG:
  959. case WM8994_AIF2_EQ_BAND_5_A:
  960. case WM8994_AIF2_EQ_BAND_5_B:
  961. case WM8994_AIF2_EQ_BAND_5_PG:
  962. case WM8994_AIF2_EQ_BAND_1_C:
  963. case WM8994_DAC1_MIXER_VOLUMES:
  964. case WM8994_DAC1_LEFT_MIXER_ROUTING:
  965. case WM8994_DAC1_RIGHT_MIXER_ROUTING:
  966. case WM8994_DAC2_MIXER_VOLUMES:
  967. case WM8994_DAC2_LEFT_MIXER_ROUTING:
  968. case WM8994_DAC2_RIGHT_MIXER_ROUTING:
  969. case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING:
  970. case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING:
  971. case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
  972. case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
  973. case WM8994_DAC1_LEFT_VOLUME:
  974. case WM8994_DAC1_RIGHT_VOLUME:
  975. case WM8994_DAC2_LEFT_VOLUME:
  976. case WM8994_DAC2_RIGHT_VOLUME:
  977. case WM8994_DAC_SOFTMUTE:
  978. case WM8994_OVERSAMPLING:
  979. case WM8994_SIDETONE:
  980. case WM8994_GPIO_1:
  981. case WM8994_GPIO_2:
  982. case WM8994_GPIO_3:
  983. case WM8994_GPIO_4:
  984. case WM8994_GPIO_5:
  985. case WM8994_GPIO_6:
  986. case WM8994_GPIO_8:
  987. case WM8994_GPIO_9:
  988. case WM8994_GPIO_10:
  989. case WM8994_GPIO_11:
  990. case WM8994_PULL_CONTROL_1:
  991. case WM8994_PULL_CONTROL_2:
  992. case WM8994_INTERRUPT_STATUS_1:
  993. case WM8994_INTERRUPT_STATUS_2:
  994. case WM8994_INTERRUPT_RAW_STATUS_2:
  995. case WM8994_INTERRUPT_STATUS_1_MASK:
  996. case WM8994_INTERRUPT_STATUS_2_MASK:
  997. case WM8994_INTERRUPT_CONTROL:
  998. case WM8994_IRQ_DEBOUNCE:
  999. return true;
  1000. default:
  1001. return false;
  1002. }
  1003. }
  1004. static bool wm8994_readable_register(struct device *dev, unsigned int reg)
  1005. {
  1006. switch (reg) {
  1007. case WM8994_DC_SERVO_READBACK:
  1008. case WM8994_MICBIAS:
  1009. case WM8994_WRITE_SEQUENCER_CTRL_1:
  1010. case WM8994_WRITE_SEQUENCER_CTRL_2:
  1011. case WM8994_AIF1_ADC2_LEFT_VOLUME:
  1012. case WM8994_AIF1_ADC2_RIGHT_VOLUME:
  1013. case WM8994_AIF1_DAC2_LEFT_VOLUME:
  1014. case WM8994_AIF1_DAC2_RIGHT_VOLUME:
  1015. case WM8994_AIF1_ADC2_FILTERS:
  1016. case WM8994_AIF1_DAC2_FILTERS_1:
  1017. case WM8994_AIF1_DAC2_FILTERS_2:
  1018. case WM8958_AIF1_DAC2_NOISE_GATE:
  1019. case WM8994_AIF1_DRC2_1:
  1020. case WM8994_AIF1_DRC2_2:
  1021. case WM8994_AIF1_DRC2_3:
  1022. case WM8994_AIF1_DRC2_4:
  1023. case WM8994_AIF1_DRC2_5:
  1024. case WM8994_AIF1_DAC2_EQ_GAINS_1:
  1025. case WM8994_AIF1_DAC2_EQ_GAINS_2:
  1026. case WM8994_AIF1_DAC2_EQ_BAND_1_A:
  1027. case WM8994_AIF1_DAC2_EQ_BAND_1_B:
  1028. case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
  1029. case WM8994_AIF1_DAC2_EQ_BAND_2_A:
  1030. case WM8994_AIF1_DAC2_EQ_BAND_2_B:
  1031. case WM8994_AIF1_DAC2_EQ_BAND_2_C:
  1032. case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
  1033. case WM8994_AIF1_DAC2_EQ_BAND_3_A:
  1034. case WM8994_AIF1_DAC2_EQ_BAND_3_B:
  1035. case WM8994_AIF1_DAC2_EQ_BAND_3_C:
  1036. case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
  1037. case WM8994_AIF1_DAC2_EQ_BAND_4_A:
  1038. case WM8994_AIF1_DAC2_EQ_BAND_4_B:
  1039. case WM8994_AIF1_DAC2_EQ_BAND_4_C:
  1040. case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
  1041. case WM8994_AIF1_DAC2_EQ_BAND_5_A:
  1042. case WM8994_AIF1_DAC2_EQ_BAND_5_B:
  1043. case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
  1044. case WM8994_AIF1_DAC2_EQ_BAND_1_C:
  1045. case WM8994_DAC2_MIXER_VOLUMES:
  1046. case WM8994_DAC2_LEFT_MIXER_ROUTING:
  1047. case WM8994_DAC2_RIGHT_MIXER_ROUTING:
  1048. case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
  1049. case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
  1050. case WM8994_DAC2_LEFT_VOLUME:
  1051. case WM8994_DAC2_RIGHT_VOLUME:
  1052. return true;
  1053. default:
  1054. return wm1811_readable_register(dev, reg);
  1055. }
  1056. }
  1057. static bool wm8958_readable_register(struct device *dev, unsigned int reg)
  1058. {
  1059. switch (reg) {
  1060. case WM8958_DSP2_PROGRAM:
  1061. case WM8958_DSP2_CONFIG:
  1062. case WM8958_DSP2_MAGICNUM:
  1063. case WM8958_DSP2_RELEASEYEAR:
  1064. case WM8958_DSP2_RELEASEMONTHDAY:
  1065. case WM8958_DSP2_RELEASETIME:
  1066. case WM8958_DSP2_VERMAJMIN:
  1067. case WM8958_DSP2_VERBUILD:
  1068. case WM8958_DSP2_TESTREG:
  1069. case WM8958_DSP2_XORREG:
  1070. case WM8958_DSP2_SHIFTMAXX:
  1071. case WM8958_DSP2_SHIFTMAXY:
  1072. case WM8958_DSP2_SHIFTMAXZ:
  1073. case WM8958_DSP2_SHIFTMAXEXTLO:
  1074. case WM8958_DSP2_AESSELECT:
  1075. case WM8958_DSP2_EXECCONTROL:
  1076. case WM8958_DSP2_SAMPLEBREAK:
  1077. case WM8958_DSP2_COUNTBREAK:
  1078. case WM8958_DSP2_INTSTATUS:
  1079. case WM8958_DSP2_EVENTSTATUS:
  1080. case WM8958_DSP2_INTMASK:
  1081. case WM8958_DSP2_CONFIGDWIDTH:
  1082. case WM8958_DSP2_CONFIGINSTR:
  1083. case WM8958_DSP2_CONFIGDMEM:
  1084. case WM8958_DSP2_CONFIGDELAYS:
  1085. case WM8958_DSP2_CONFIGNUMIO:
  1086. case WM8958_DSP2_CONFIGEXTDEPTH:
  1087. case WM8958_DSP2_CONFIGMULTIPLIER:
  1088. case WM8958_DSP2_CONFIGCTRLDWIDTH:
  1089. case WM8958_DSP2_CONFIGPIPELINE:
  1090. case WM8958_DSP2_SHIFTMAXEXTHI:
  1091. case WM8958_DSP2_SWVERSIONREG:
  1092. case WM8958_DSP2_CONFIGXMEM:
  1093. case WM8958_DSP2_CONFIGYMEM:
  1094. case WM8958_DSP2_CONFIGZMEM:
  1095. case WM8958_FW_BUILD_1:
  1096. case WM8958_FW_BUILD_0:
  1097. case WM8958_FW_ID_1:
  1098. case WM8958_FW_ID_0:
  1099. case WM8958_FW_MAJOR_1:
  1100. case WM8958_FW_MAJOR_0:
  1101. case WM8958_FW_MINOR_1:
  1102. case WM8958_FW_MINOR_0:
  1103. case WM8958_FW_PATCH_1:
  1104. case WM8958_FW_PATCH_0:
  1105. case WM8958_MBC_BAND_1_K_1:
  1106. case WM8958_MBC_BAND_1_K_2:
  1107. case WM8958_MBC_BAND_1_N1_1:
  1108. case WM8958_MBC_BAND_1_N1_2:
  1109. case WM8958_MBC_BAND_1_N2_1:
  1110. case WM8958_MBC_BAND_1_N2_2:
  1111. case WM8958_MBC_BAND_1_N3_1:
  1112. case WM8958_MBC_BAND_1_N3_2:
  1113. case WM8958_MBC_BAND_1_N4_1:
  1114. case WM8958_MBC_BAND_1_N4_2:
  1115. case WM8958_MBC_BAND_1_N5_1:
  1116. case WM8958_MBC_BAND_1_N5_2:
  1117. case WM8958_MBC_BAND_1_X1_1:
  1118. case WM8958_MBC_BAND_1_X1_2:
  1119. case WM8958_MBC_BAND_1_X2_1:
  1120. case WM8958_MBC_BAND_1_X2_2:
  1121. case WM8958_MBC_BAND_1_X3_1:
  1122. case WM8958_MBC_BAND_1_X3_2:
  1123. case WM8958_MBC_BAND_1_ATTACK_1:
  1124. case WM8958_MBC_BAND_1_ATTACK_2:
  1125. case WM8958_MBC_BAND_1_DECAY_1:
  1126. case WM8958_MBC_BAND_1_DECAY_2:
  1127. case WM8958_MBC_BAND_2_K_1:
  1128. case WM8958_MBC_BAND_2_K_2:
  1129. case WM8958_MBC_BAND_2_N1_1:
  1130. case WM8958_MBC_BAND_2_N1_2:
  1131. case WM8958_MBC_BAND_2_N2_1:
  1132. case WM8958_MBC_BAND_2_N2_2:
  1133. case WM8958_MBC_BAND_2_N3_1:
  1134. case WM8958_MBC_BAND_2_N3_2:
  1135. case WM8958_MBC_BAND_2_N4_1:
  1136. case WM8958_MBC_BAND_2_N4_2:
  1137. case WM8958_MBC_BAND_2_N5_1:
  1138. case WM8958_MBC_BAND_2_N5_2:
  1139. case WM8958_MBC_BAND_2_X1_1:
  1140. case WM8958_MBC_BAND_2_X1_2:
  1141. case WM8958_MBC_BAND_2_X2_1:
  1142. case WM8958_MBC_BAND_2_X2_2:
  1143. case WM8958_MBC_BAND_2_X3_1:
  1144. case WM8958_MBC_BAND_2_X3_2:
  1145. case WM8958_MBC_BAND_2_ATTACK_1:
  1146. case WM8958_MBC_BAND_2_ATTACK_2:
  1147. case WM8958_MBC_BAND_2_DECAY_1:
  1148. case WM8958_MBC_BAND_2_DECAY_2:
  1149. case WM8958_MBC_B2_PG2_1:
  1150. case WM8958_MBC_B2_PG2_2:
  1151. case WM8958_MBC_B1_PG2_1:
  1152. case WM8958_MBC_B1_PG2_2:
  1153. case WM8958_MBC_CROSSOVER_1:
  1154. case WM8958_MBC_CROSSOVER_2:
  1155. case WM8958_MBC_HPF_1:
  1156. case WM8958_MBC_HPF_2:
  1157. case WM8958_MBC_LPF_1:
  1158. case WM8958_MBC_LPF_2:
  1159. case WM8958_MBC_RMS_LIMIT_1:
  1160. case WM8958_MBC_RMS_LIMIT_2:
  1161. return true;
  1162. default:
  1163. return wm8994_readable_register(dev, reg);
  1164. }
  1165. }
  1166. static bool wm8994_volatile_register(struct device *dev, unsigned int reg)
  1167. {
  1168. switch (reg) {
  1169. case WM8994_SOFTWARE_RESET:
  1170. case WM8994_DC_SERVO_1:
  1171. case WM8994_DC_SERVO_READBACK:
  1172. case WM8994_RATE_STATUS:
  1173. case WM8958_MIC_DETECT_3:
  1174. case WM8994_DC_SERVO_4E:
  1175. case WM8994_INTERRUPT_STATUS_1:
  1176. case WM8994_INTERRUPT_STATUS_2:
  1177. return true;
  1178. default:
  1179. return false;
  1180. }
  1181. }
  1182. static bool wm1811_volatile_register(struct device *dev, unsigned int reg)
  1183. {
  1184. struct wm8994 *wm8994 = dev_get_drvdata(dev);
  1185. switch (reg) {
  1186. case WM8994_GPIO_6:
  1187. if (wm8994->cust_id > 1 || wm8994->revision > 1)
  1188. return true;
  1189. else
  1190. return false;
  1191. default:
  1192. return wm8994_volatile_register(dev, reg);
  1193. }
  1194. }
  1195. static bool wm8958_volatile_register(struct device *dev, unsigned int reg)
  1196. {
  1197. switch (reg) {
  1198. case WM8958_DSP2_MAGICNUM:
  1199. case WM8958_DSP2_RELEASEYEAR:
  1200. case WM8958_DSP2_RELEASEMONTHDAY:
  1201. case WM8958_DSP2_RELEASETIME:
  1202. case WM8958_DSP2_VERMAJMIN:
  1203. case WM8958_DSP2_VERBUILD:
  1204. case WM8958_DSP2_EXECCONTROL:
  1205. case WM8958_DSP2_SWVERSIONREG:
  1206. case WM8958_DSP2_CONFIGXMEM:
  1207. case WM8958_DSP2_CONFIGYMEM:
  1208. case WM8958_DSP2_CONFIGZMEM:
  1209. case WM8958_FW_BUILD_1:
  1210. case WM8958_FW_BUILD_0:
  1211. case WM8958_FW_ID_1:
  1212. case WM8958_FW_ID_0:
  1213. case WM8958_FW_MAJOR_1:
  1214. case WM8958_FW_MAJOR_0:
  1215. case WM8958_FW_MINOR_1:
  1216. case WM8958_FW_MINOR_0:
  1217. case WM8958_FW_PATCH_1:
  1218. case WM8958_FW_PATCH_0:
  1219. return true;
  1220. default:
  1221. return wm8994_volatile_register(dev, reg);
  1222. }
  1223. }
  1224. struct regmap_config wm1811_regmap_config = {
  1225. .reg_bits = 16,
  1226. .val_bits = 16,
  1227. .cache_type = REGCACHE_RBTREE,
  1228. .reg_defaults = wm1811_defaults,
  1229. .num_reg_defaults = ARRAY_SIZE(wm1811_defaults),
  1230. .max_register = WM8994_MAX_REGISTER,
  1231. .volatile_reg = wm1811_volatile_register,
  1232. .readable_reg = wm1811_readable_register,
  1233. };
  1234. EXPORT_SYMBOL(wm1811_regmap_config);
  1235. struct regmap_config wm8994_regmap_config = {
  1236. .reg_bits = 16,
  1237. .val_bits = 16,
  1238. .cache_type = REGCACHE_RBTREE,
  1239. .reg_defaults = wm8994_defaults,
  1240. .num_reg_defaults = ARRAY_SIZE(wm8994_defaults),
  1241. .max_register = WM8994_MAX_REGISTER,
  1242. .volatile_reg = wm8994_volatile_register,
  1243. .readable_reg = wm8994_readable_register,
  1244. };
  1245. EXPORT_SYMBOL(wm8994_regmap_config);
  1246. struct regmap_config wm8958_regmap_config = {
  1247. .reg_bits = 16,
  1248. .val_bits = 16,
  1249. .cache_type = REGCACHE_RBTREE,
  1250. .reg_defaults = wm8958_defaults,
  1251. .num_reg_defaults = ARRAY_SIZE(wm8958_defaults),
  1252. .max_register = WM8994_MAX_REGISTER,
  1253. .volatile_reg = wm8958_volatile_register,
  1254. .readable_reg = wm8958_readable_register,
  1255. };
  1256. EXPORT_SYMBOL(wm8958_regmap_config);
  1257. struct regmap_config wm8994_base_regmap_config = {
  1258. .reg_bits = 16,
  1259. .val_bits = 16,
  1260. };
  1261. EXPORT_SYMBOL(wm8994_base_regmap_config);