wm8350-irq.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8350-irq.c -- IRQ support for Wolfson WM8350
  4. *
  5. * Copyright 2007, 2008, 2009 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Liam Girdwood, Mark Brown
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/bug.h>
  12. #include <linux/device.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/mfd/wm8350/core.h>
  16. #include <linux/mfd/wm8350/audio.h>
  17. #include <linux/mfd/wm8350/comparator.h>
  18. #include <linux/mfd/wm8350/gpio.h>
  19. #include <linux/mfd/wm8350/pmic.h>
  20. #include <linux/mfd/wm8350/rtc.h>
  21. #include <linux/mfd/wm8350/supply.h>
  22. #include <linux/mfd/wm8350/wdt.h>
  23. #define WM8350_INT_OFFSET_1 0
  24. #define WM8350_INT_OFFSET_2 1
  25. #define WM8350_POWER_UP_INT_OFFSET 2
  26. #define WM8350_UNDER_VOLTAGE_INT_OFFSET 3
  27. #define WM8350_OVER_CURRENT_INT_OFFSET 4
  28. #define WM8350_GPIO_INT_OFFSET 5
  29. #define WM8350_COMPARATOR_INT_OFFSET 6
  30. struct wm8350_irq_data {
  31. int primary;
  32. int reg;
  33. int mask;
  34. int primary_only;
  35. };
  36. static struct wm8350_irq_data wm8350_irqs[] = {
  37. [WM8350_IRQ_OC_LS] = {
  38. .primary = WM8350_OC_INT,
  39. .reg = WM8350_OVER_CURRENT_INT_OFFSET,
  40. .mask = WM8350_OC_LS_EINT,
  41. .primary_only = 1,
  42. },
  43. [WM8350_IRQ_UV_DC1] = {
  44. .primary = WM8350_UV_INT,
  45. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  46. .mask = WM8350_UV_DC1_EINT,
  47. },
  48. [WM8350_IRQ_UV_DC2] = {
  49. .primary = WM8350_UV_INT,
  50. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  51. .mask = WM8350_UV_DC2_EINT,
  52. },
  53. [WM8350_IRQ_UV_DC3] = {
  54. .primary = WM8350_UV_INT,
  55. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  56. .mask = WM8350_UV_DC3_EINT,
  57. },
  58. [WM8350_IRQ_UV_DC4] = {
  59. .primary = WM8350_UV_INT,
  60. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  61. .mask = WM8350_UV_DC4_EINT,
  62. },
  63. [WM8350_IRQ_UV_DC5] = {
  64. .primary = WM8350_UV_INT,
  65. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  66. .mask = WM8350_UV_DC5_EINT,
  67. },
  68. [WM8350_IRQ_UV_DC6] = {
  69. .primary = WM8350_UV_INT,
  70. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  71. .mask = WM8350_UV_DC6_EINT,
  72. },
  73. [WM8350_IRQ_UV_LDO1] = {
  74. .primary = WM8350_UV_INT,
  75. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  76. .mask = WM8350_UV_LDO1_EINT,
  77. },
  78. [WM8350_IRQ_UV_LDO2] = {
  79. .primary = WM8350_UV_INT,
  80. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  81. .mask = WM8350_UV_LDO2_EINT,
  82. },
  83. [WM8350_IRQ_UV_LDO3] = {
  84. .primary = WM8350_UV_INT,
  85. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  86. .mask = WM8350_UV_LDO3_EINT,
  87. },
  88. [WM8350_IRQ_UV_LDO4] = {
  89. .primary = WM8350_UV_INT,
  90. .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
  91. .mask = WM8350_UV_LDO4_EINT,
  92. },
  93. [WM8350_IRQ_CHG_BAT_HOT] = {
  94. .primary = WM8350_CHG_INT,
  95. .reg = WM8350_INT_OFFSET_1,
  96. .mask = WM8350_CHG_BAT_HOT_EINT,
  97. },
  98. [WM8350_IRQ_CHG_BAT_COLD] = {
  99. .primary = WM8350_CHG_INT,
  100. .reg = WM8350_INT_OFFSET_1,
  101. .mask = WM8350_CHG_BAT_COLD_EINT,
  102. },
  103. [WM8350_IRQ_CHG_BAT_FAIL] = {
  104. .primary = WM8350_CHG_INT,
  105. .reg = WM8350_INT_OFFSET_1,
  106. .mask = WM8350_CHG_BAT_FAIL_EINT,
  107. },
  108. [WM8350_IRQ_CHG_TO] = {
  109. .primary = WM8350_CHG_INT,
  110. .reg = WM8350_INT_OFFSET_1,
  111. .mask = WM8350_CHG_TO_EINT,
  112. },
  113. [WM8350_IRQ_CHG_END] = {
  114. .primary = WM8350_CHG_INT,
  115. .reg = WM8350_INT_OFFSET_1,
  116. .mask = WM8350_CHG_END_EINT,
  117. },
  118. [WM8350_IRQ_CHG_START] = {
  119. .primary = WM8350_CHG_INT,
  120. .reg = WM8350_INT_OFFSET_1,
  121. .mask = WM8350_CHG_START_EINT,
  122. },
  123. [WM8350_IRQ_CHG_FAST_RDY] = {
  124. .primary = WM8350_CHG_INT,
  125. .reg = WM8350_INT_OFFSET_1,
  126. .mask = WM8350_CHG_FAST_RDY_EINT,
  127. },
  128. [WM8350_IRQ_CHG_VBATT_LT_3P9] = {
  129. .primary = WM8350_CHG_INT,
  130. .reg = WM8350_INT_OFFSET_1,
  131. .mask = WM8350_CHG_VBATT_LT_3P9_EINT,
  132. },
  133. [WM8350_IRQ_CHG_VBATT_LT_3P1] = {
  134. .primary = WM8350_CHG_INT,
  135. .reg = WM8350_INT_OFFSET_1,
  136. .mask = WM8350_CHG_VBATT_LT_3P1_EINT,
  137. },
  138. [WM8350_IRQ_CHG_VBATT_LT_2P85] = {
  139. .primary = WM8350_CHG_INT,
  140. .reg = WM8350_INT_OFFSET_1,
  141. .mask = WM8350_CHG_VBATT_LT_2P85_EINT,
  142. },
  143. [WM8350_IRQ_RTC_ALM] = {
  144. .primary = WM8350_RTC_INT,
  145. .reg = WM8350_INT_OFFSET_1,
  146. .mask = WM8350_RTC_ALM_EINT,
  147. },
  148. [WM8350_IRQ_RTC_SEC] = {
  149. .primary = WM8350_RTC_INT,
  150. .reg = WM8350_INT_OFFSET_1,
  151. .mask = WM8350_RTC_SEC_EINT,
  152. },
  153. [WM8350_IRQ_RTC_PER] = {
  154. .primary = WM8350_RTC_INT,
  155. .reg = WM8350_INT_OFFSET_1,
  156. .mask = WM8350_RTC_PER_EINT,
  157. },
  158. [WM8350_IRQ_CS1] = {
  159. .primary = WM8350_CS_INT,
  160. .reg = WM8350_INT_OFFSET_2,
  161. .mask = WM8350_CS1_EINT,
  162. },
  163. [WM8350_IRQ_CS2] = {
  164. .primary = WM8350_CS_INT,
  165. .reg = WM8350_INT_OFFSET_2,
  166. .mask = WM8350_CS2_EINT,
  167. },
  168. [WM8350_IRQ_SYS_HYST_COMP_FAIL] = {
  169. .primary = WM8350_SYS_INT,
  170. .reg = WM8350_INT_OFFSET_2,
  171. .mask = WM8350_SYS_HYST_COMP_FAIL_EINT,
  172. },
  173. [WM8350_IRQ_SYS_CHIP_GT115] = {
  174. .primary = WM8350_SYS_INT,
  175. .reg = WM8350_INT_OFFSET_2,
  176. .mask = WM8350_SYS_CHIP_GT115_EINT,
  177. },
  178. [WM8350_IRQ_SYS_CHIP_GT140] = {
  179. .primary = WM8350_SYS_INT,
  180. .reg = WM8350_INT_OFFSET_2,
  181. .mask = WM8350_SYS_CHIP_GT140_EINT,
  182. },
  183. [WM8350_IRQ_SYS_WDOG_TO] = {
  184. .primary = WM8350_SYS_INT,
  185. .reg = WM8350_INT_OFFSET_2,
  186. .mask = WM8350_SYS_WDOG_TO_EINT,
  187. },
  188. [WM8350_IRQ_AUXADC_DATARDY] = {
  189. .primary = WM8350_AUXADC_INT,
  190. .reg = WM8350_INT_OFFSET_2,
  191. .mask = WM8350_AUXADC_DATARDY_EINT,
  192. },
  193. [WM8350_IRQ_AUXADC_DCOMP4] = {
  194. .primary = WM8350_AUXADC_INT,
  195. .reg = WM8350_INT_OFFSET_2,
  196. .mask = WM8350_AUXADC_DCOMP4_EINT,
  197. },
  198. [WM8350_IRQ_AUXADC_DCOMP3] = {
  199. .primary = WM8350_AUXADC_INT,
  200. .reg = WM8350_INT_OFFSET_2,
  201. .mask = WM8350_AUXADC_DCOMP3_EINT,
  202. },
  203. [WM8350_IRQ_AUXADC_DCOMP2] = {
  204. .primary = WM8350_AUXADC_INT,
  205. .reg = WM8350_INT_OFFSET_2,
  206. .mask = WM8350_AUXADC_DCOMP2_EINT,
  207. },
  208. [WM8350_IRQ_AUXADC_DCOMP1] = {
  209. .primary = WM8350_AUXADC_INT,
  210. .reg = WM8350_INT_OFFSET_2,
  211. .mask = WM8350_AUXADC_DCOMP1_EINT,
  212. },
  213. [WM8350_IRQ_USB_LIMIT] = {
  214. .primary = WM8350_USB_INT,
  215. .reg = WM8350_INT_OFFSET_2,
  216. .mask = WM8350_USB_LIMIT_EINT,
  217. .primary_only = 1,
  218. },
  219. [WM8350_IRQ_WKUP_OFF_STATE] = {
  220. .primary = WM8350_WKUP_INT,
  221. .reg = WM8350_COMPARATOR_INT_OFFSET,
  222. .mask = WM8350_WKUP_OFF_STATE_EINT,
  223. },
  224. [WM8350_IRQ_WKUP_HIB_STATE] = {
  225. .primary = WM8350_WKUP_INT,
  226. .reg = WM8350_COMPARATOR_INT_OFFSET,
  227. .mask = WM8350_WKUP_HIB_STATE_EINT,
  228. },
  229. [WM8350_IRQ_WKUP_CONV_FAULT] = {
  230. .primary = WM8350_WKUP_INT,
  231. .reg = WM8350_COMPARATOR_INT_OFFSET,
  232. .mask = WM8350_WKUP_CONV_FAULT_EINT,
  233. },
  234. [WM8350_IRQ_WKUP_WDOG_RST] = {
  235. .primary = WM8350_WKUP_INT,
  236. .reg = WM8350_COMPARATOR_INT_OFFSET,
  237. .mask = WM8350_WKUP_WDOG_RST_EINT,
  238. },
  239. [WM8350_IRQ_WKUP_GP_PWR_ON] = {
  240. .primary = WM8350_WKUP_INT,
  241. .reg = WM8350_COMPARATOR_INT_OFFSET,
  242. .mask = WM8350_WKUP_GP_PWR_ON_EINT,
  243. },
  244. [WM8350_IRQ_WKUP_ONKEY] = {
  245. .primary = WM8350_WKUP_INT,
  246. .reg = WM8350_COMPARATOR_INT_OFFSET,
  247. .mask = WM8350_WKUP_ONKEY_EINT,
  248. },
  249. [WM8350_IRQ_WKUP_GP_WAKEUP] = {
  250. .primary = WM8350_WKUP_INT,
  251. .reg = WM8350_COMPARATOR_INT_OFFSET,
  252. .mask = WM8350_WKUP_GP_WAKEUP_EINT,
  253. },
  254. [WM8350_IRQ_CODEC_JCK_DET_L] = {
  255. .primary = WM8350_CODEC_INT,
  256. .reg = WM8350_COMPARATOR_INT_OFFSET,
  257. .mask = WM8350_CODEC_JCK_DET_L_EINT,
  258. },
  259. [WM8350_IRQ_CODEC_JCK_DET_R] = {
  260. .primary = WM8350_CODEC_INT,
  261. .reg = WM8350_COMPARATOR_INT_OFFSET,
  262. .mask = WM8350_CODEC_JCK_DET_R_EINT,
  263. },
  264. [WM8350_IRQ_CODEC_MICSCD] = {
  265. .primary = WM8350_CODEC_INT,
  266. .reg = WM8350_COMPARATOR_INT_OFFSET,
  267. .mask = WM8350_CODEC_MICSCD_EINT,
  268. },
  269. [WM8350_IRQ_CODEC_MICD] = {
  270. .primary = WM8350_CODEC_INT,
  271. .reg = WM8350_COMPARATOR_INT_OFFSET,
  272. .mask = WM8350_CODEC_MICD_EINT,
  273. },
  274. [WM8350_IRQ_EXT_USB_FB] = {
  275. .primary = WM8350_EXT_INT,
  276. .reg = WM8350_COMPARATOR_INT_OFFSET,
  277. .mask = WM8350_EXT_USB_FB_EINT,
  278. },
  279. [WM8350_IRQ_EXT_WALL_FB] = {
  280. .primary = WM8350_EXT_INT,
  281. .reg = WM8350_COMPARATOR_INT_OFFSET,
  282. .mask = WM8350_EXT_WALL_FB_EINT,
  283. },
  284. [WM8350_IRQ_EXT_BAT_FB] = {
  285. .primary = WM8350_EXT_INT,
  286. .reg = WM8350_COMPARATOR_INT_OFFSET,
  287. .mask = WM8350_EXT_BAT_FB_EINT,
  288. },
  289. [WM8350_IRQ_GPIO(0)] = {
  290. .primary = WM8350_GP_INT,
  291. .reg = WM8350_GPIO_INT_OFFSET,
  292. .mask = WM8350_GP0_EINT,
  293. },
  294. [WM8350_IRQ_GPIO(1)] = {
  295. .primary = WM8350_GP_INT,
  296. .reg = WM8350_GPIO_INT_OFFSET,
  297. .mask = WM8350_GP1_EINT,
  298. },
  299. [WM8350_IRQ_GPIO(2)] = {
  300. .primary = WM8350_GP_INT,
  301. .reg = WM8350_GPIO_INT_OFFSET,
  302. .mask = WM8350_GP2_EINT,
  303. },
  304. [WM8350_IRQ_GPIO(3)] = {
  305. .primary = WM8350_GP_INT,
  306. .reg = WM8350_GPIO_INT_OFFSET,
  307. .mask = WM8350_GP3_EINT,
  308. },
  309. [WM8350_IRQ_GPIO(4)] = {
  310. .primary = WM8350_GP_INT,
  311. .reg = WM8350_GPIO_INT_OFFSET,
  312. .mask = WM8350_GP4_EINT,
  313. },
  314. [WM8350_IRQ_GPIO(5)] = {
  315. .primary = WM8350_GP_INT,
  316. .reg = WM8350_GPIO_INT_OFFSET,
  317. .mask = WM8350_GP5_EINT,
  318. },
  319. [WM8350_IRQ_GPIO(6)] = {
  320. .primary = WM8350_GP_INT,
  321. .reg = WM8350_GPIO_INT_OFFSET,
  322. .mask = WM8350_GP6_EINT,
  323. },
  324. [WM8350_IRQ_GPIO(7)] = {
  325. .primary = WM8350_GP_INT,
  326. .reg = WM8350_GPIO_INT_OFFSET,
  327. .mask = WM8350_GP7_EINT,
  328. },
  329. [WM8350_IRQ_GPIO(8)] = {
  330. .primary = WM8350_GP_INT,
  331. .reg = WM8350_GPIO_INT_OFFSET,
  332. .mask = WM8350_GP8_EINT,
  333. },
  334. [WM8350_IRQ_GPIO(9)] = {
  335. .primary = WM8350_GP_INT,
  336. .reg = WM8350_GPIO_INT_OFFSET,
  337. .mask = WM8350_GP9_EINT,
  338. },
  339. [WM8350_IRQ_GPIO(10)] = {
  340. .primary = WM8350_GP_INT,
  341. .reg = WM8350_GPIO_INT_OFFSET,
  342. .mask = WM8350_GP10_EINT,
  343. },
  344. [WM8350_IRQ_GPIO(11)] = {
  345. .primary = WM8350_GP_INT,
  346. .reg = WM8350_GPIO_INT_OFFSET,
  347. .mask = WM8350_GP11_EINT,
  348. },
  349. [WM8350_IRQ_GPIO(12)] = {
  350. .primary = WM8350_GP_INT,
  351. .reg = WM8350_GPIO_INT_OFFSET,
  352. .mask = WM8350_GP12_EINT,
  353. },
  354. };
  355. static inline struct wm8350_irq_data *irq_to_wm8350_irq(struct wm8350 *wm8350,
  356. int irq)
  357. {
  358. return &wm8350_irqs[irq - wm8350->irq_base];
  359. }
  360. /*
  361. * This is a threaded IRQ handler so can access I2C/SPI. Since all
  362. * interrupts are clear on read the IRQ line will be reasserted and
  363. * the physical IRQ will be handled again if another interrupt is
  364. * asserted while we run - in the normal course of events this is a
  365. * rare occurrence so we save I2C/SPI reads. We're also assuming that
  366. * it's rare to get lots of interrupts firing simultaneously so try to
  367. * minimise I/O.
  368. */
  369. static irqreturn_t wm8350_irq(int irq, void *irq_data)
  370. {
  371. struct wm8350 *wm8350 = irq_data;
  372. u16 level_one;
  373. u16 sub_reg[WM8350_NUM_IRQ_REGS];
  374. int read_done[WM8350_NUM_IRQ_REGS];
  375. struct wm8350_irq_data *data;
  376. int i;
  377. level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
  378. & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
  379. if (!level_one)
  380. return IRQ_NONE;
  381. memset(&read_done, 0, sizeof(read_done));
  382. for (i = 0; i < ARRAY_SIZE(wm8350_irqs); i++) {
  383. data = &wm8350_irqs[i];
  384. if (!(level_one & data->primary))
  385. continue;
  386. if (!read_done[data->reg]) {
  387. sub_reg[data->reg] =
  388. wm8350_reg_read(wm8350, WM8350_INT_STATUS_1 +
  389. data->reg);
  390. sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg];
  391. read_done[data->reg] = 1;
  392. }
  393. if (sub_reg[data->reg] & data->mask)
  394. handle_nested_irq(wm8350->irq_base + i);
  395. }
  396. return IRQ_HANDLED;
  397. }
  398. static void wm8350_irq_lock(struct irq_data *data)
  399. {
  400. struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
  401. mutex_lock(&wm8350->irq_lock);
  402. }
  403. static void wm8350_irq_sync_unlock(struct irq_data *data)
  404. {
  405. struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
  406. int i;
  407. for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
  408. /* If there's been a change in the mask write it back
  409. * to the hardware. */
  410. WARN_ON(regmap_update_bits(wm8350->regmap,
  411. WM8350_INT_STATUS_1_MASK + i,
  412. 0xffff, wm8350->irq_masks[i]));
  413. }
  414. mutex_unlock(&wm8350->irq_lock);
  415. }
  416. static void wm8350_irq_enable(struct irq_data *data)
  417. {
  418. struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
  419. struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
  420. data->irq);
  421. wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask;
  422. }
  423. static void wm8350_irq_disable(struct irq_data *data)
  424. {
  425. struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
  426. struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
  427. data->irq);
  428. wm8350->irq_masks[irq_data->reg] |= irq_data->mask;
  429. }
  430. static struct irq_chip wm8350_irq_chip = {
  431. .name = "wm8350",
  432. .irq_bus_lock = wm8350_irq_lock,
  433. .irq_bus_sync_unlock = wm8350_irq_sync_unlock,
  434. .irq_disable = wm8350_irq_disable,
  435. .irq_enable = wm8350_irq_enable,
  436. };
  437. int wm8350_irq_init(struct wm8350 *wm8350, int irq,
  438. struct wm8350_platform_data *pdata)
  439. {
  440. int ret, cur_irq, i;
  441. int flags = IRQF_ONESHOT;
  442. int irq_base = -1;
  443. if (!irq) {
  444. dev_warn(wm8350->dev, "No interrupt support, no core IRQ\n");
  445. return 0;
  446. }
  447. /* Mask top level interrupts */
  448. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
  449. /* Mask all individual interrupts by default and cache the
  450. * masks. We read the masks back since there are unwritable
  451. * bits in the mask registers. */
  452. for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
  453. wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK + i,
  454. 0xFFFF);
  455. wm8350->irq_masks[i] =
  456. wm8350_reg_read(wm8350,
  457. WM8350_INT_STATUS_1_MASK + i);
  458. }
  459. mutex_init(&wm8350->irq_lock);
  460. wm8350->chip_irq = irq;
  461. if (pdata && pdata->irq_base > 0)
  462. irq_base = pdata->irq_base;
  463. wm8350->irq_base =
  464. irq_alloc_descs(irq_base, 0, ARRAY_SIZE(wm8350_irqs), 0);
  465. if (wm8350->irq_base < 0) {
  466. dev_warn(wm8350->dev, "Allocating irqs failed with %d\n",
  467. wm8350->irq_base);
  468. return 0;
  469. }
  470. if (pdata && pdata->irq_high) {
  471. flags |= IRQF_TRIGGER_HIGH;
  472. wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
  473. WM8350_IRQ_POL);
  474. } else {
  475. flags |= IRQF_TRIGGER_LOW;
  476. wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
  477. WM8350_IRQ_POL);
  478. }
  479. /* Register with genirq */
  480. for (cur_irq = wm8350->irq_base;
  481. cur_irq < ARRAY_SIZE(wm8350_irqs) + wm8350->irq_base;
  482. cur_irq++) {
  483. irq_set_chip_data(cur_irq, wm8350);
  484. irq_set_chip_and_handler(cur_irq, &wm8350_irq_chip,
  485. handle_edge_irq);
  486. irq_set_nested_thread(cur_irq, 1);
  487. irq_clear_status_flags(cur_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  488. }
  489. ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
  490. "wm8350", wm8350);
  491. if (ret != 0)
  492. dev_err(wm8350->dev, "Failed to request IRQ: %d\n", ret);
  493. /* Allow interrupts to fire */
  494. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0);
  495. return ret;
  496. }
  497. int wm8350_irq_exit(struct wm8350 *wm8350)
  498. {
  499. free_irq(wm8350->chip_irq, wm8350);
  500. return 0;
  501. }