wm831x-irq.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
  4. *
  5. * Copyright 2009 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/i2c.h>
  12. #include <linux/irq.h>
  13. #include <linux/mfd/core.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/mfd/wm831x/core.h>
  17. #include <linux/mfd/wm831x/pdata.h>
  18. #include <linux/mfd/wm831x/gpio.h>
  19. #include <linux/mfd/wm831x/irq.h>
  20. #include <linux/delay.h>
  21. struct wm831x_irq_data {
  22. int primary;
  23. int reg;
  24. int mask;
  25. };
  26. static struct wm831x_irq_data wm831x_irqs[] = {
  27. [WM831X_IRQ_TEMP_THW] = {
  28. .primary = WM831X_TEMP_INT,
  29. .reg = 1,
  30. .mask = WM831X_TEMP_THW_EINT,
  31. },
  32. [WM831X_IRQ_GPIO_1] = {
  33. .primary = WM831X_GP_INT,
  34. .reg = 5,
  35. .mask = WM831X_GP1_EINT,
  36. },
  37. [WM831X_IRQ_GPIO_2] = {
  38. .primary = WM831X_GP_INT,
  39. .reg = 5,
  40. .mask = WM831X_GP2_EINT,
  41. },
  42. [WM831X_IRQ_GPIO_3] = {
  43. .primary = WM831X_GP_INT,
  44. .reg = 5,
  45. .mask = WM831X_GP3_EINT,
  46. },
  47. [WM831X_IRQ_GPIO_4] = {
  48. .primary = WM831X_GP_INT,
  49. .reg = 5,
  50. .mask = WM831X_GP4_EINT,
  51. },
  52. [WM831X_IRQ_GPIO_5] = {
  53. .primary = WM831X_GP_INT,
  54. .reg = 5,
  55. .mask = WM831X_GP5_EINT,
  56. },
  57. [WM831X_IRQ_GPIO_6] = {
  58. .primary = WM831X_GP_INT,
  59. .reg = 5,
  60. .mask = WM831X_GP6_EINT,
  61. },
  62. [WM831X_IRQ_GPIO_7] = {
  63. .primary = WM831X_GP_INT,
  64. .reg = 5,
  65. .mask = WM831X_GP7_EINT,
  66. },
  67. [WM831X_IRQ_GPIO_8] = {
  68. .primary = WM831X_GP_INT,
  69. .reg = 5,
  70. .mask = WM831X_GP8_EINT,
  71. },
  72. [WM831X_IRQ_GPIO_9] = {
  73. .primary = WM831X_GP_INT,
  74. .reg = 5,
  75. .mask = WM831X_GP9_EINT,
  76. },
  77. [WM831X_IRQ_GPIO_10] = {
  78. .primary = WM831X_GP_INT,
  79. .reg = 5,
  80. .mask = WM831X_GP10_EINT,
  81. },
  82. [WM831X_IRQ_GPIO_11] = {
  83. .primary = WM831X_GP_INT,
  84. .reg = 5,
  85. .mask = WM831X_GP11_EINT,
  86. },
  87. [WM831X_IRQ_GPIO_12] = {
  88. .primary = WM831X_GP_INT,
  89. .reg = 5,
  90. .mask = WM831X_GP12_EINT,
  91. },
  92. [WM831X_IRQ_GPIO_13] = {
  93. .primary = WM831X_GP_INT,
  94. .reg = 5,
  95. .mask = WM831X_GP13_EINT,
  96. },
  97. [WM831X_IRQ_GPIO_14] = {
  98. .primary = WM831X_GP_INT,
  99. .reg = 5,
  100. .mask = WM831X_GP14_EINT,
  101. },
  102. [WM831X_IRQ_GPIO_15] = {
  103. .primary = WM831X_GP_INT,
  104. .reg = 5,
  105. .mask = WM831X_GP15_EINT,
  106. },
  107. [WM831X_IRQ_GPIO_16] = {
  108. .primary = WM831X_GP_INT,
  109. .reg = 5,
  110. .mask = WM831X_GP16_EINT,
  111. },
  112. [WM831X_IRQ_ON] = {
  113. .primary = WM831X_ON_PIN_INT,
  114. .reg = 1,
  115. .mask = WM831X_ON_PIN_EINT,
  116. },
  117. [WM831X_IRQ_PPM_SYSLO] = {
  118. .primary = WM831X_PPM_INT,
  119. .reg = 1,
  120. .mask = WM831X_PPM_SYSLO_EINT,
  121. },
  122. [WM831X_IRQ_PPM_PWR_SRC] = {
  123. .primary = WM831X_PPM_INT,
  124. .reg = 1,
  125. .mask = WM831X_PPM_PWR_SRC_EINT,
  126. },
  127. [WM831X_IRQ_PPM_USB_CURR] = {
  128. .primary = WM831X_PPM_INT,
  129. .reg = 1,
  130. .mask = WM831X_PPM_USB_CURR_EINT,
  131. },
  132. [WM831X_IRQ_WDOG_TO] = {
  133. .primary = WM831X_WDOG_INT,
  134. .reg = 1,
  135. .mask = WM831X_WDOG_TO_EINT,
  136. },
  137. [WM831X_IRQ_RTC_PER] = {
  138. .primary = WM831X_RTC_INT,
  139. .reg = 1,
  140. .mask = WM831X_RTC_PER_EINT,
  141. },
  142. [WM831X_IRQ_RTC_ALM] = {
  143. .primary = WM831X_RTC_INT,
  144. .reg = 1,
  145. .mask = WM831X_RTC_ALM_EINT,
  146. },
  147. [WM831X_IRQ_CHG_BATT_HOT] = {
  148. .primary = WM831X_CHG_INT,
  149. .reg = 2,
  150. .mask = WM831X_CHG_BATT_HOT_EINT,
  151. },
  152. [WM831X_IRQ_CHG_BATT_COLD] = {
  153. .primary = WM831X_CHG_INT,
  154. .reg = 2,
  155. .mask = WM831X_CHG_BATT_COLD_EINT,
  156. },
  157. [WM831X_IRQ_CHG_BATT_FAIL] = {
  158. .primary = WM831X_CHG_INT,
  159. .reg = 2,
  160. .mask = WM831X_CHG_BATT_FAIL_EINT,
  161. },
  162. [WM831X_IRQ_CHG_OV] = {
  163. .primary = WM831X_CHG_INT,
  164. .reg = 2,
  165. .mask = WM831X_CHG_OV_EINT,
  166. },
  167. [WM831X_IRQ_CHG_END] = {
  168. .primary = WM831X_CHG_INT,
  169. .reg = 2,
  170. .mask = WM831X_CHG_END_EINT,
  171. },
  172. [WM831X_IRQ_CHG_TO] = {
  173. .primary = WM831X_CHG_INT,
  174. .reg = 2,
  175. .mask = WM831X_CHG_TO_EINT,
  176. },
  177. [WM831X_IRQ_CHG_MODE] = {
  178. .primary = WM831X_CHG_INT,
  179. .reg = 2,
  180. .mask = WM831X_CHG_MODE_EINT,
  181. },
  182. [WM831X_IRQ_CHG_START] = {
  183. .primary = WM831X_CHG_INT,
  184. .reg = 2,
  185. .mask = WM831X_CHG_START_EINT,
  186. },
  187. [WM831X_IRQ_TCHDATA] = {
  188. .primary = WM831X_TCHDATA_INT,
  189. .reg = 1,
  190. .mask = WM831X_TCHDATA_EINT,
  191. },
  192. [WM831X_IRQ_TCHPD] = {
  193. .primary = WM831X_TCHPD_INT,
  194. .reg = 1,
  195. .mask = WM831X_TCHPD_EINT,
  196. },
  197. [WM831X_IRQ_AUXADC_DATA] = {
  198. .primary = WM831X_AUXADC_INT,
  199. .reg = 1,
  200. .mask = WM831X_AUXADC_DATA_EINT,
  201. },
  202. [WM831X_IRQ_AUXADC_DCOMP1] = {
  203. .primary = WM831X_AUXADC_INT,
  204. .reg = 1,
  205. .mask = WM831X_AUXADC_DCOMP1_EINT,
  206. },
  207. [WM831X_IRQ_AUXADC_DCOMP2] = {
  208. .primary = WM831X_AUXADC_INT,
  209. .reg = 1,
  210. .mask = WM831X_AUXADC_DCOMP2_EINT,
  211. },
  212. [WM831X_IRQ_AUXADC_DCOMP3] = {
  213. .primary = WM831X_AUXADC_INT,
  214. .reg = 1,
  215. .mask = WM831X_AUXADC_DCOMP3_EINT,
  216. },
  217. [WM831X_IRQ_AUXADC_DCOMP4] = {
  218. .primary = WM831X_AUXADC_INT,
  219. .reg = 1,
  220. .mask = WM831X_AUXADC_DCOMP4_EINT,
  221. },
  222. [WM831X_IRQ_CS1] = {
  223. .primary = WM831X_CS_INT,
  224. .reg = 2,
  225. .mask = WM831X_CS1_EINT,
  226. },
  227. [WM831X_IRQ_CS2] = {
  228. .primary = WM831X_CS_INT,
  229. .reg = 2,
  230. .mask = WM831X_CS2_EINT,
  231. },
  232. [WM831X_IRQ_HC_DC1] = {
  233. .primary = WM831X_HC_INT,
  234. .reg = 4,
  235. .mask = WM831X_HC_DC1_EINT,
  236. },
  237. [WM831X_IRQ_HC_DC2] = {
  238. .primary = WM831X_HC_INT,
  239. .reg = 4,
  240. .mask = WM831X_HC_DC2_EINT,
  241. },
  242. [WM831X_IRQ_UV_LDO1] = {
  243. .primary = WM831X_UV_INT,
  244. .reg = 3,
  245. .mask = WM831X_UV_LDO1_EINT,
  246. },
  247. [WM831X_IRQ_UV_LDO2] = {
  248. .primary = WM831X_UV_INT,
  249. .reg = 3,
  250. .mask = WM831X_UV_LDO2_EINT,
  251. },
  252. [WM831X_IRQ_UV_LDO3] = {
  253. .primary = WM831X_UV_INT,
  254. .reg = 3,
  255. .mask = WM831X_UV_LDO3_EINT,
  256. },
  257. [WM831X_IRQ_UV_LDO4] = {
  258. .primary = WM831X_UV_INT,
  259. .reg = 3,
  260. .mask = WM831X_UV_LDO4_EINT,
  261. },
  262. [WM831X_IRQ_UV_LDO5] = {
  263. .primary = WM831X_UV_INT,
  264. .reg = 3,
  265. .mask = WM831X_UV_LDO5_EINT,
  266. },
  267. [WM831X_IRQ_UV_LDO6] = {
  268. .primary = WM831X_UV_INT,
  269. .reg = 3,
  270. .mask = WM831X_UV_LDO6_EINT,
  271. },
  272. [WM831X_IRQ_UV_LDO7] = {
  273. .primary = WM831X_UV_INT,
  274. .reg = 3,
  275. .mask = WM831X_UV_LDO7_EINT,
  276. },
  277. [WM831X_IRQ_UV_LDO8] = {
  278. .primary = WM831X_UV_INT,
  279. .reg = 3,
  280. .mask = WM831X_UV_LDO8_EINT,
  281. },
  282. [WM831X_IRQ_UV_LDO9] = {
  283. .primary = WM831X_UV_INT,
  284. .reg = 3,
  285. .mask = WM831X_UV_LDO9_EINT,
  286. },
  287. [WM831X_IRQ_UV_LDO10] = {
  288. .primary = WM831X_UV_INT,
  289. .reg = 3,
  290. .mask = WM831X_UV_LDO10_EINT,
  291. },
  292. [WM831X_IRQ_UV_DC1] = {
  293. .primary = WM831X_UV_INT,
  294. .reg = 4,
  295. .mask = WM831X_UV_DC1_EINT,
  296. },
  297. [WM831X_IRQ_UV_DC2] = {
  298. .primary = WM831X_UV_INT,
  299. .reg = 4,
  300. .mask = WM831X_UV_DC2_EINT,
  301. },
  302. [WM831X_IRQ_UV_DC3] = {
  303. .primary = WM831X_UV_INT,
  304. .reg = 4,
  305. .mask = WM831X_UV_DC3_EINT,
  306. },
  307. [WM831X_IRQ_UV_DC4] = {
  308. .primary = WM831X_UV_INT,
  309. .reg = 4,
  310. .mask = WM831X_UV_DC4_EINT,
  311. },
  312. };
  313. static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
  314. {
  315. return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
  316. }
  317. static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
  318. int irq)
  319. {
  320. return &wm831x_irqs[irq];
  321. }
  322. static void wm831x_irq_lock(struct irq_data *data)
  323. {
  324. struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
  325. mutex_lock(&wm831x->irq_lock);
  326. }
  327. static void wm831x_irq_sync_unlock(struct irq_data *data)
  328. {
  329. struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
  330. int i;
  331. for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
  332. if (wm831x->gpio_update[i]) {
  333. wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
  334. WM831X_GPN_INT_MODE | WM831X_GPN_POL,
  335. wm831x->gpio_update[i]);
  336. wm831x->gpio_update[i] = 0;
  337. }
  338. }
  339. for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
  340. /* If there's been a change in the mask write it back
  341. * to the hardware. */
  342. if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
  343. dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
  344. WM831X_INTERRUPT_STATUS_1_MASK + i,
  345. wm831x->irq_masks_cur[i]);
  346. wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
  347. wm831x_reg_write(wm831x,
  348. WM831X_INTERRUPT_STATUS_1_MASK + i,
  349. wm831x->irq_masks_cur[i]);
  350. }
  351. }
  352. mutex_unlock(&wm831x->irq_lock);
  353. }
  354. static void wm831x_irq_enable(struct irq_data *data)
  355. {
  356. struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
  357. struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
  358. data->hwirq);
  359. wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
  360. }
  361. static void wm831x_irq_disable(struct irq_data *data)
  362. {
  363. struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
  364. struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
  365. data->hwirq);
  366. wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
  367. }
  368. static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
  369. {
  370. struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
  371. int irq;
  372. irq = data->hwirq;
  373. if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
  374. /* Ignore internal-only IRQs */
  375. if (irq >= 0 && irq < WM831X_NUM_IRQS)
  376. return 0;
  377. else
  378. return -EINVAL;
  379. }
  380. /* Rebase the IRQ into the GPIO range so we've got a sensible array
  381. * index.
  382. */
  383. irq -= WM831X_IRQ_GPIO_1;
  384. /* We set the high bit to flag that we need an update; don't
  385. * do the update here as we can be called with the bus lock
  386. * held.
  387. */
  388. wm831x->gpio_level_low[irq] = false;
  389. wm831x->gpio_level_high[irq] = false;
  390. switch (type) {
  391. case IRQ_TYPE_EDGE_BOTH:
  392. wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
  393. break;
  394. case IRQ_TYPE_EDGE_RISING:
  395. wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
  396. break;
  397. case IRQ_TYPE_EDGE_FALLING:
  398. wm831x->gpio_update[irq] = 0x10000;
  399. break;
  400. case IRQ_TYPE_LEVEL_HIGH:
  401. wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
  402. wm831x->gpio_level_high[irq] = true;
  403. break;
  404. case IRQ_TYPE_LEVEL_LOW:
  405. wm831x->gpio_update[irq] = 0x10000;
  406. wm831x->gpio_level_low[irq] = true;
  407. break;
  408. default:
  409. return -EINVAL;
  410. }
  411. return 0;
  412. }
  413. static struct irq_chip wm831x_irq_chip = {
  414. .name = "wm831x",
  415. .irq_bus_lock = wm831x_irq_lock,
  416. .irq_bus_sync_unlock = wm831x_irq_sync_unlock,
  417. .irq_disable = wm831x_irq_disable,
  418. .irq_enable = wm831x_irq_enable,
  419. .irq_set_type = wm831x_irq_set_type,
  420. };
  421. /* The processing of the primary interrupt occurs in a thread so that
  422. * we can interact with the device over I2C or SPI. */
  423. static irqreturn_t wm831x_irq_thread(int irq, void *data)
  424. {
  425. struct wm831x *wm831x = data;
  426. unsigned int i;
  427. int primary, status_addr, ret;
  428. int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
  429. int read[WM831X_NUM_IRQ_REGS] = { 0 };
  430. int *status;
  431. primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
  432. if (primary < 0) {
  433. dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
  434. primary);
  435. goto out;
  436. }
  437. /* The touch interrupts are visible in the primary register as
  438. * an optimisation; open code this to avoid complicating the
  439. * main handling loop and so we can also skip iterating the
  440. * descriptors.
  441. */
  442. if (primary & WM831X_TCHPD_INT)
  443. handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
  444. WM831X_IRQ_TCHPD));
  445. if (primary & WM831X_TCHDATA_INT)
  446. handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
  447. WM831X_IRQ_TCHDATA));
  448. primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
  449. for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
  450. int offset = wm831x_irqs[i].reg - 1;
  451. if (!(primary & wm831x_irqs[i].primary))
  452. continue;
  453. status = &status_regs[offset];
  454. /* Hopefully there should only be one register to read
  455. * each time otherwise we ought to do a block read. */
  456. if (!read[offset]) {
  457. status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
  458. *status = wm831x_reg_read(wm831x, status_addr);
  459. if (*status < 0) {
  460. dev_err(wm831x->dev,
  461. "Failed to read IRQ status: %d\n",
  462. *status);
  463. goto out;
  464. }
  465. read[offset] = 1;
  466. /* Ignore any bits that we don't think are masked */
  467. *status &= ~wm831x->irq_masks_cur[offset];
  468. /* Acknowledge now so we don't miss
  469. * notifications while we handle.
  470. */
  471. wm831x_reg_write(wm831x, status_addr, *status);
  472. }
  473. if (*status & wm831x_irqs[i].mask)
  474. handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
  475. i));
  476. /* Simulate an edge triggered IRQ by polling the input
  477. * status. This is sucky but improves interoperability.
  478. */
  479. if (primary == WM831X_GP_INT &&
  480. wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
  481. ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
  482. while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
  483. handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
  484. i));
  485. ret = wm831x_reg_read(wm831x,
  486. WM831X_GPIO_LEVEL);
  487. }
  488. }
  489. if (primary == WM831X_GP_INT &&
  490. wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
  491. ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
  492. while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
  493. handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
  494. i));
  495. ret = wm831x_reg_read(wm831x,
  496. WM831X_GPIO_LEVEL);
  497. }
  498. }
  499. }
  500. out:
  501. return IRQ_HANDLED;
  502. }
  503. static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
  504. irq_hw_number_t hw)
  505. {
  506. irq_set_chip_data(virq, h->host_data);
  507. irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
  508. irq_set_nested_thread(virq, 1);
  509. irq_set_noprobe(virq);
  510. return 0;
  511. }
  512. static const struct irq_domain_ops wm831x_irq_domain_ops = {
  513. .map = wm831x_irq_map,
  514. .xlate = irq_domain_xlate_twocell,
  515. };
  516. int wm831x_irq_init(struct wm831x *wm831x, int irq)
  517. {
  518. struct wm831x_pdata *pdata = &wm831x->pdata;
  519. struct irq_domain *domain;
  520. int i, ret, irq_base;
  521. mutex_init(&wm831x->irq_lock);
  522. /* Mask the individual interrupt sources */
  523. for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
  524. wm831x->irq_masks_cur[i] = 0xffff;
  525. wm831x->irq_masks_cache[i] = 0xffff;
  526. wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
  527. 0xffff);
  528. }
  529. /* Try to dynamically allocate IRQs if no base is specified */
  530. if (pdata->irq_base) {
  531. irq_base = irq_alloc_descs(pdata->irq_base, 0,
  532. WM831X_NUM_IRQS, 0);
  533. if (irq_base < 0) {
  534. dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
  535. irq_base);
  536. irq_base = 0;
  537. }
  538. } else {
  539. irq_base = 0;
  540. }
  541. if (irq_base)
  542. domain = irq_domain_add_legacy(wm831x->dev->of_node,
  543. ARRAY_SIZE(wm831x_irqs),
  544. irq_base, 0,
  545. &wm831x_irq_domain_ops,
  546. wm831x);
  547. else
  548. domain = irq_domain_add_linear(wm831x->dev->of_node,
  549. ARRAY_SIZE(wm831x_irqs),
  550. &wm831x_irq_domain_ops,
  551. wm831x);
  552. if (!domain) {
  553. dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
  554. return -EINVAL;
  555. }
  556. if (pdata->irq_cmos)
  557. i = 0;
  558. else
  559. i = WM831X_IRQ_OD;
  560. wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
  561. WM831X_IRQ_OD, i);
  562. wm831x->irq = irq;
  563. wm831x->irq_domain = domain;
  564. if (irq) {
  565. /* Try to flag /IRQ as a wake source; there are a number of
  566. * unconditional wake sources in the PMIC so this isn't
  567. * conditional but we don't actually care *too* much if it
  568. * fails.
  569. */
  570. ret = enable_irq_wake(irq);
  571. if (ret != 0) {
  572. dev_warn(wm831x->dev,
  573. "Can't enable IRQ as wake source: %d\n",
  574. ret);
  575. }
  576. ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
  577. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  578. "wm831x", wm831x);
  579. if (ret != 0) {
  580. dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
  581. irq, ret);
  582. return ret;
  583. }
  584. } else {
  585. dev_warn(wm831x->dev,
  586. "No interrupt specified - functionality limited\n");
  587. }
  588. /* Enable top level interrupts, we mask at secondary level */
  589. wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
  590. return 0;
  591. }
  592. void wm831x_irq_exit(struct wm831x *wm831x)
  593. {
  594. if (wm831x->irq)
  595. free_irq(wm831x->irq, wm831x);
  596. }