twl4030-power.c 26 KB

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  1. /*
  2. *
  3. * Handle TWL4030 Power initialization
  4. *
  5. * Copyright (C) 2008 Nokia Corporation
  6. * Copyright (C) 2006 Texas Instruments, Inc
  7. *
  8. * Written by Kalle Jokiniemi
  9. * Peter De Schrijver <peter.de-schrijver@nokia.com>
  10. * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
  11. *
  12. * This file is subject to the terms and conditions of the GNU General
  13. * Public License. See the file "COPYING" in the main directory of this
  14. * archive for more details.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/pm.h>
  27. #include <linux/mfd/twl.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/of.h>
  30. #include <linux/of_device.h>
  31. #include <asm/mach-types.h>
  32. static u8 twl4030_start_script_address = 0x2b;
  33. /* Register bits for P1, P2 and P3_SW_EVENTS */
  34. #define PWR_STOPON_PRWON BIT(6)
  35. #define PWR_STOPON_SYSEN BIT(5)
  36. #define PWR_ENABLE_WARMRESET BIT(4)
  37. #define PWR_LVL_WAKEUP BIT(3)
  38. #define PWR_DEVACT BIT(2)
  39. #define PWR_DEVSLP BIT(1)
  40. #define PWR_DEVOFF BIT(0)
  41. /* Register bits for CFG_P1_TRANSITION (also for P2 and P3) */
  42. #define STARTON_SWBUG BIT(7) /* Start on watchdog */
  43. #define STARTON_VBUS BIT(5) /* Start on VBUS */
  44. #define STARTON_VBAT BIT(4) /* Start on battery insert */
  45. #define STARTON_RTC BIT(3) /* Start on RTC */
  46. #define STARTON_USB BIT(2) /* Start on USB host */
  47. #define STARTON_CHG BIT(1) /* Start on charger */
  48. #define STARTON_PWON BIT(0) /* Start on PWRON button */
  49. #define SEQ_OFFSYNC (1 << 0)
  50. #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
  51. #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
  52. /* resource - hfclk */
  53. #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
  54. /* PM events */
  55. #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
  56. #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
  57. #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
  58. #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
  59. #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
  60. #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
  61. #define END_OF_SCRIPT 0x3f
  62. #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
  63. #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
  64. #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
  65. #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
  66. #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
  67. #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
  68. /* resource configuration registers
  69. <RESOURCE>_DEV_GRP at address 'n+0'
  70. <RESOURCE>_TYPE at address 'n+1'
  71. <RESOURCE>_REMAP at address 'n+2'
  72. <RESOURCE>_DEDICATED at address 'n+3'
  73. */
  74. #define DEV_GRP_OFFSET 0
  75. #define TYPE_OFFSET 1
  76. #define REMAP_OFFSET 2
  77. #define DEDICATED_OFFSET 3
  78. /* Bit positions in the registers */
  79. /* <RESOURCE>_DEV_GRP */
  80. #define DEV_GRP_SHIFT 5
  81. #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
  82. /* <RESOURCE>_TYPE */
  83. #define TYPE_SHIFT 0
  84. #define TYPE_MASK (7 << TYPE_SHIFT)
  85. #define TYPE2_SHIFT 3
  86. #define TYPE2_MASK (3 << TYPE2_SHIFT)
  87. /* <RESOURCE>_REMAP */
  88. #define SLEEP_STATE_SHIFT 0
  89. #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
  90. #define OFF_STATE_SHIFT 4
  91. #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
  92. static u8 res_config_addrs[] = {
  93. [RES_VAUX1] = 0x17,
  94. [RES_VAUX2] = 0x1b,
  95. [RES_VAUX3] = 0x1f,
  96. [RES_VAUX4] = 0x23,
  97. [RES_VMMC1] = 0x27,
  98. [RES_VMMC2] = 0x2b,
  99. [RES_VPLL1] = 0x2f,
  100. [RES_VPLL2] = 0x33,
  101. [RES_VSIM] = 0x37,
  102. [RES_VDAC] = 0x3b,
  103. [RES_VINTANA1] = 0x3f,
  104. [RES_VINTANA2] = 0x43,
  105. [RES_VINTDIG] = 0x47,
  106. [RES_VIO] = 0x4b,
  107. [RES_VDD1] = 0x55,
  108. [RES_VDD2] = 0x63,
  109. [RES_VUSB_1V5] = 0x71,
  110. [RES_VUSB_1V8] = 0x74,
  111. [RES_VUSB_3V1] = 0x77,
  112. [RES_VUSBCP] = 0x7a,
  113. [RES_REGEN] = 0x7f,
  114. [RES_NRES_PWRON] = 0x82,
  115. [RES_CLKEN] = 0x85,
  116. [RES_SYSEN] = 0x88,
  117. [RES_HFCLKOUT] = 0x8b,
  118. [RES_32KCLKOUT] = 0x8e,
  119. [RES_RESET] = 0x91,
  120. [RES_MAIN_REF] = 0x94,
  121. };
  122. /*
  123. * Usable values for .remap_sleep and .remap_off
  124. * Based on table "5.3.3 Resource Operating modes"
  125. */
  126. enum {
  127. TWL_REMAP_OFF = 0,
  128. TWL_REMAP_SLEEP = 8,
  129. TWL_REMAP_ACTIVE = 9,
  130. };
  131. /*
  132. * Macros to configure the PM register states for various resources.
  133. * Note that we can make MSG_SINGULAR etc private to this driver once
  134. * omap3 has been made DT only.
  135. */
  136. #define TWL_DFLT_DELAY 2 /* typically 2 32 KiHz cycles */
  137. #define TWL_DEV_GRP_P123 (DEV_GRP_P1 | DEV_GRP_P2 | DEV_GRP_P3)
  138. #define TWL_RESOURCE_SET(res, state) \
  139. { MSG_SINGULAR(DEV_GRP_NULL, (res), (state)), TWL_DFLT_DELAY }
  140. #define TWL_RESOURCE_ON(res) TWL_RESOURCE_SET(res, RES_STATE_ACTIVE)
  141. #define TWL_RESOURCE_OFF(res) TWL_RESOURCE_SET(res, RES_STATE_OFF)
  142. #define TWL_RESOURCE_RESET(res) TWL_RESOURCE_SET(res, RES_STATE_WRST)
  143. /*
  144. * It seems that type1 and type2 is just the resource init order
  145. * number for the type1 and type2 group.
  146. */
  147. #define TWL_RESOURCE_SET_ACTIVE(res, state) \
  148. { MSG_SINGULAR(DEV_GRP_NULL, (res), RES_STATE_ACTIVE), (state) }
  149. #define TWL_RESOURCE_GROUP_RESET(group, type1, type2) \
  150. { MSG_BROADCAST(DEV_GRP_NULL, (group), (type1), (type2), \
  151. RES_STATE_WRST), TWL_DFLT_DELAY }
  152. #define TWL_RESOURCE_GROUP_SLEEP(group, type, type2) \
  153. { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
  154. RES_STATE_SLEEP), TWL_DFLT_DELAY }
  155. #define TWL_RESOURCE_GROUP_ACTIVE(group, type, type2) \
  156. { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
  157. RES_STATE_ACTIVE), TWL_DFLT_DELAY }
  158. #define TWL_REMAP_SLEEP(res, devgrp, typ, typ2) \
  159. { .resource = (res), .devgroup = (devgrp), \
  160. .type = (typ), .type2 = (typ2), \
  161. .remap_off = TWL_REMAP_OFF, \
  162. .remap_sleep = TWL_REMAP_SLEEP, }
  163. #define TWL_REMAP_OFF(res, devgrp, typ, typ2) \
  164. { .resource = (res), .devgroup = (devgrp), \
  165. .type = (typ), .type2 = (typ2), \
  166. .remap_off = TWL_REMAP_OFF, .remap_sleep = TWL_REMAP_OFF, }
  167. static int twl4030_write_script_byte(u8 address, u8 byte)
  168. {
  169. int err;
  170. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
  171. if (err)
  172. goto out;
  173. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
  174. out:
  175. return err;
  176. }
  177. static int twl4030_write_script_ins(u8 address, u16 pmb_message,
  178. u8 delay, u8 next)
  179. {
  180. int err;
  181. address *= 4;
  182. err = twl4030_write_script_byte(address++, pmb_message >> 8);
  183. if (err)
  184. goto out;
  185. err = twl4030_write_script_byte(address++, pmb_message & 0xff);
  186. if (err)
  187. goto out;
  188. err = twl4030_write_script_byte(address++, delay);
  189. if (err)
  190. goto out;
  191. err = twl4030_write_script_byte(address++, next);
  192. out:
  193. return err;
  194. }
  195. static int twl4030_write_script(u8 address, struct twl4030_ins *script,
  196. int len)
  197. {
  198. int err = -EINVAL;
  199. for (; len; len--, address++, script++) {
  200. if (len == 1) {
  201. err = twl4030_write_script_ins(address,
  202. script->pmb_message,
  203. script->delay,
  204. END_OF_SCRIPT);
  205. if (err)
  206. break;
  207. } else {
  208. err = twl4030_write_script_ins(address,
  209. script->pmb_message,
  210. script->delay,
  211. address + 1);
  212. if (err)
  213. break;
  214. }
  215. }
  216. return err;
  217. }
  218. static int twl4030_config_wakeup3_sequence(u8 address)
  219. {
  220. int err;
  221. u8 data;
  222. /* Set SLEEP to ACTIVE SEQ address for P3 */
  223. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
  224. if (err)
  225. goto out;
  226. /* P3 LVL_WAKEUP should be on LEVEL */
  227. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
  228. if (err)
  229. goto out;
  230. data |= PWR_LVL_WAKEUP;
  231. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
  232. out:
  233. if (err)
  234. pr_err("TWL4030 wakeup sequence for P3 config error\n");
  235. return err;
  236. }
  237. static int
  238. twl4030_config_wakeup12_sequence(const struct twl4030_power_data *pdata,
  239. u8 address)
  240. {
  241. int err = 0;
  242. u8 data;
  243. /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
  244. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
  245. if (err)
  246. goto out;
  247. /* P1/P2 LVL_WAKEUP should be on LEVEL */
  248. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
  249. if (err)
  250. goto out;
  251. data |= PWR_LVL_WAKEUP;
  252. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
  253. if (err)
  254. goto out;
  255. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
  256. if (err)
  257. goto out;
  258. data |= PWR_LVL_WAKEUP;
  259. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
  260. if (err)
  261. goto out;
  262. if (pdata->ac_charger_quirk || machine_is_omap_3430sdp() ||
  263. machine_is_omap_ldp()) {
  264. /* Disabling AC charger effect on sleep-active transitions */
  265. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
  266. R_CFG_P1_TRANSITION);
  267. if (err)
  268. goto out;
  269. data &= ~STARTON_CHG;
  270. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
  271. R_CFG_P1_TRANSITION);
  272. if (err)
  273. goto out;
  274. }
  275. out:
  276. if (err)
  277. pr_err("TWL4030 wakeup sequence for P1 and P2" \
  278. "config error\n");
  279. return err;
  280. }
  281. static int twl4030_config_sleep_sequence(u8 address)
  282. {
  283. int err;
  284. /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
  285. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
  286. if (err)
  287. pr_err("TWL4030 sleep sequence config error\n");
  288. return err;
  289. }
  290. static int twl4030_config_warmreset_sequence(u8 address)
  291. {
  292. int err;
  293. u8 rd_data;
  294. /* Set WARM RESET SEQ address for P1 */
  295. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
  296. if (err)
  297. goto out;
  298. /* P1/P2/P3 enable WARMRESET */
  299. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
  300. if (err)
  301. goto out;
  302. rd_data |= PWR_ENABLE_WARMRESET;
  303. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
  304. if (err)
  305. goto out;
  306. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
  307. if (err)
  308. goto out;
  309. rd_data |= PWR_ENABLE_WARMRESET;
  310. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
  311. if (err)
  312. goto out;
  313. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
  314. if (err)
  315. goto out;
  316. rd_data |= PWR_ENABLE_WARMRESET;
  317. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
  318. out:
  319. if (err)
  320. pr_err("TWL4030 warmreset seq config error\n");
  321. return err;
  322. }
  323. static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
  324. {
  325. int rconfig_addr;
  326. int err;
  327. u8 type;
  328. u8 grp;
  329. u8 remap;
  330. if (rconfig->resource > TOTAL_RESOURCES) {
  331. pr_err("TWL4030 Resource %d does not exist\n",
  332. rconfig->resource);
  333. return -EINVAL;
  334. }
  335. rconfig_addr = res_config_addrs[rconfig->resource];
  336. /* Set resource group */
  337. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
  338. rconfig_addr + DEV_GRP_OFFSET);
  339. if (err) {
  340. pr_err("TWL4030 Resource %d group could not be read\n",
  341. rconfig->resource);
  342. return err;
  343. }
  344. if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
  345. grp &= ~DEV_GRP_MASK;
  346. grp |= rconfig->devgroup << DEV_GRP_SHIFT;
  347. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  348. grp, rconfig_addr + DEV_GRP_OFFSET);
  349. if (err < 0) {
  350. pr_err("TWL4030 failed to program devgroup\n");
  351. return err;
  352. }
  353. }
  354. /* Set resource types */
  355. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
  356. rconfig_addr + TYPE_OFFSET);
  357. if (err < 0) {
  358. pr_err("TWL4030 Resource %d type could not be read\n",
  359. rconfig->resource);
  360. return err;
  361. }
  362. if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
  363. type &= ~TYPE_MASK;
  364. type |= rconfig->type << TYPE_SHIFT;
  365. }
  366. if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
  367. type &= ~TYPE2_MASK;
  368. type |= rconfig->type2 << TYPE2_SHIFT;
  369. }
  370. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  371. type, rconfig_addr + TYPE_OFFSET);
  372. if (err < 0) {
  373. pr_err("TWL4030 failed to program resource type\n");
  374. return err;
  375. }
  376. /* Set remap states */
  377. err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
  378. rconfig_addr + REMAP_OFFSET);
  379. if (err < 0) {
  380. pr_err("TWL4030 Resource %d remap could not be read\n",
  381. rconfig->resource);
  382. return err;
  383. }
  384. if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
  385. remap &= ~OFF_STATE_MASK;
  386. remap |= rconfig->remap_off << OFF_STATE_SHIFT;
  387. }
  388. if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
  389. remap &= ~SLEEP_STATE_MASK;
  390. remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
  391. }
  392. err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
  393. remap,
  394. rconfig_addr + REMAP_OFFSET);
  395. if (err < 0) {
  396. pr_err("TWL4030 failed to program remap\n");
  397. return err;
  398. }
  399. return 0;
  400. }
  401. static int load_twl4030_script(const struct twl4030_power_data *pdata,
  402. struct twl4030_script *tscript,
  403. u8 address)
  404. {
  405. int err;
  406. static int order;
  407. /* Make sure the script isn't going beyond last valid address (0x3f) */
  408. if ((address + tscript->size) > END_OF_SCRIPT) {
  409. pr_err("TWL4030 scripts too big error\n");
  410. return -EINVAL;
  411. }
  412. err = twl4030_write_script(address, tscript->script, tscript->size);
  413. if (err)
  414. goto out;
  415. if (tscript->flags & TWL4030_WRST_SCRIPT) {
  416. err = twl4030_config_warmreset_sequence(address);
  417. if (err)
  418. goto out;
  419. }
  420. if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
  421. /* Reset any existing sleep script to avoid hangs on reboot */
  422. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  423. R_SEQ_ADD_A2S);
  424. if (err)
  425. goto out;
  426. err = twl4030_config_wakeup12_sequence(pdata, address);
  427. if (err)
  428. goto out;
  429. order = 1;
  430. }
  431. if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
  432. err = twl4030_config_wakeup3_sequence(address);
  433. if (err)
  434. goto out;
  435. }
  436. if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
  437. if (!order)
  438. pr_warn("TWL4030: Bad order of scripts (sleep script before wakeup) Leads to boot failure on some boards\n");
  439. err = twl4030_config_sleep_sequence(address);
  440. }
  441. out:
  442. return err;
  443. }
  444. int twl4030_remove_script(u8 flags)
  445. {
  446. int err = 0;
  447. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  448. TWL4030_PM_MASTER_PROTECT_KEY);
  449. if (err) {
  450. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  451. return err;
  452. }
  453. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
  454. TWL4030_PM_MASTER_PROTECT_KEY);
  455. if (err) {
  456. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  457. return err;
  458. }
  459. if (flags & TWL4030_WRST_SCRIPT) {
  460. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  461. R_SEQ_ADD_WARM);
  462. if (err)
  463. return err;
  464. }
  465. if (flags & TWL4030_WAKEUP12_SCRIPT) {
  466. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  467. R_SEQ_ADD_S2A12);
  468. if (err)
  469. return err;
  470. }
  471. if (flags & TWL4030_WAKEUP3_SCRIPT) {
  472. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  473. R_SEQ_ADD_S2A3);
  474. if (err)
  475. return err;
  476. }
  477. if (flags & TWL4030_SLEEP_SCRIPT) {
  478. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
  479. R_SEQ_ADD_A2S);
  480. if (err)
  481. return err;
  482. }
  483. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  484. TWL4030_PM_MASTER_PROTECT_KEY);
  485. if (err)
  486. pr_err("TWL4030 Unable to relock registers\n");
  487. return err;
  488. }
  489. static int
  490. twl4030_power_configure_scripts(const struct twl4030_power_data *pdata)
  491. {
  492. int err;
  493. int i;
  494. u8 address = twl4030_start_script_address;
  495. for (i = 0; i < pdata->num; i++) {
  496. err = load_twl4030_script(pdata, pdata->scripts[i], address);
  497. if (err)
  498. return err;
  499. address += pdata->scripts[i]->size;
  500. }
  501. return 0;
  502. }
  503. static void twl4030_patch_rconfig(struct twl4030_resconfig *common,
  504. struct twl4030_resconfig *board)
  505. {
  506. while (common->resource) {
  507. struct twl4030_resconfig *b = board;
  508. while (b->resource) {
  509. if (b->resource == common->resource) {
  510. *common = *b;
  511. break;
  512. }
  513. b++;
  514. }
  515. common++;
  516. }
  517. }
  518. static int
  519. twl4030_power_configure_resources(const struct twl4030_power_data *pdata)
  520. {
  521. struct twl4030_resconfig *resconfig = pdata->resource_config;
  522. struct twl4030_resconfig *boardconf = pdata->board_config;
  523. int err;
  524. if (resconfig) {
  525. if (boardconf)
  526. twl4030_patch_rconfig(resconfig, boardconf);
  527. while (resconfig->resource) {
  528. err = twl4030_configure_resource(resconfig);
  529. if (err)
  530. return err;
  531. resconfig++;
  532. }
  533. }
  534. return 0;
  535. }
  536. static int twl4030_starton_mask_and_set(u8 bitmask, u8 bitvalues)
  537. {
  538. u8 regs[3] = { TWL4030_PM_MASTER_CFG_P1_TRANSITION,
  539. TWL4030_PM_MASTER_CFG_P2_TRANSITION,
  540. TWL4030_PM_MASTER_CFG_P3_TRANSITION, };
  541. u8 val;
  542. int i, err;
  543. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  544. TWL4030_PM_MASTER_PROTECT_KEY);
  545. if (err)
  546. goto relock;
  547. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
  548. TWL4030_PM_MASTER_KEY_CFG2,
  549. TWL4030_PM_MASTER_PROTECT_KEY);
  550. if (err)
  551. goto relock;
  552. for (i = 0; i < sizeof(regs); i++) {
  553. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER,
  554. &val, regs[i]);
  555. if (err)
  556. break;
  557. val = (~bitmask & val) | (bitmask & bitvalues);
  558. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
  559. val, regs[i]);
  560. if (err)
  561. break;
  562. }
  563. if (err)
  564. pr_err("TWL4030 Register access failed: %i\n", err);
  565. relock:
  566. return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  567. TWL4030_PM_MASTER_PROTECT_KEY);
  568. }
  569. /*
  570. * In master mode, start the power off sequence.
  571. * After a successful execution, TWL shuts down the power to the SoC
  572. * and all peripherals connected to it.
  573. */
  574. void twl4030_power_off(void)
  575. {
  576. int err;
  577. /* Disable start on charger or VBUS as it can break poweroff */
  578. err = twl4030_starton_mask_and_set(STARTON_VBUS | STARTON_CHG, 0);
  579. if (err)
  580. pr_err("TWL4030 Unable to configure start-up\n");
  581. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
  582. TWL4030_PM_MASTER_P1_SW_EVENTS);
  583. if (err)
  584. pr_err("TWL4030 Unable to power off\n");
  585. }
  586. static bool twl4030_power_use_poweroff(const struct twl4030_power_data *pdata,
  587. struct device_node *node)
  588. {
  589. if (pdata && pdata->use_poweroff)
  590. return true;
  591. if (of_property_read_bool(node, "ti,system-power-controller"))
  592. return true;
  593. if (of_property_read_bool(node, "ti,use_poweroff"))
  594. return true;
  595. return false;
  596. }
  597. #ifdef CONFIG_OF
  598. /* Generic warm reset configuration for omap3 */
  599. static struct twl4030_ins omap3_wrst_seq[] = {
  600. TWL_RESOURCE_OFF(RES_NRES_PWRON),
  601. TWL_RESOURCE_OFF(RES_RESET),
  602. TWL_RESOURCE_RESET(RES_MAIN_REF),
  603. TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2),
  604. TWL_RESOURCE_RESET(RES_VUSB_3V1),
  605. TWL_RESOURCE_RESET(RES_VMMC1),
  606. TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1),
  607. TWL_RESOURCE_GROUP_RESET(RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0),
  608. TWL_RESOURCE_ON(RES_RESET),
  609. TWL_RESOURCE_ON(RES_NRES_PWRON),
  610. };
  611. static struct twl4030_script omap3_wrst_script = {
  612. .script = omap3_wrst_seq,
  613. .size = ARRAY_SIZE(omap3_wrst_seq),
  614. .flags = TWL4030_WRST_SCRIPT,
  615. };
  616. static struct twl4030_script *omap3_reset_scripts[] = {
  617. &omap3_wrst_script,
  618. };
  619. static struct twl4030_resconfig omap3_rconfig[] = {
  620. TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, -1, -1),
  621. TWL_REMAP_SLEEP(RES_VDD1, DEV_GRP_P1, -1, -1),
  622. TWL_REMAP_SLEEP(RES_VDD2, DEV_GRP_P1, -1, -1),
  623. { 0, 0 },
  624. };
  625. static struct twl4030_power_data omap3_reset = {
  626. .scripts = omap3_reset_scripts,
  627. .num = ARRAY_SIZE(omap3_reset_scripts),
  628. .resource_config = omap3_rconfig,
  629. };
  630. /* Recommended generic default idle configuration for off-idle */
  631. /* Broadcast message to put res to sleep */
  632. static struct twl4030_ins omap3_idle_sleep_on_seq[] = {
  633. TWL_RESOURCE_GROUP_SLEEP(RES_GRP_ALL, RES_TYPE_ALL, 0),
  634. };
  635. static struct twl4030_script omap3_idle_sleep_on_script = {
  636. .script = omap3_idle_sleep_on_seq,
  637. .size = ARRAY_SIZE(omap3_idle_sleep_on_seq),
  638. .flags = TWL4030_SLEEP_SCRIPT,
  639. };
  640. /* Broadcast message to put res to active */
  641. static struct twl4030_ins omap3_idle_wakeup_p12_seq[] = {
  642. TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
  643. };
  644. static struct twl4030_script omap3_idle_wakeup_p12_script = {
  645. .script = omap3_idle_wakeup_p12_seq,
  646. .size = ARRAY_SIZE(omap3_idle_wakeup_p12_seq),
  647. .flags = TWL4030_WAKEUP12_SCRIPT,
  648. };
  649. /* Broadcast message to put res to active */
  650. static struct twl4030_ins omap3_idle_wakeup_p3_seq[] = {
  651. TWL_RESOURCE_SET_ACTIVE(RES_CLKEN, 0x37),
  652. TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
  653. };
  654. static struct twl4030_script omap3_idle_wakeup_p3_script = {
  655. .script = omap3_idle_wakeup_p3_seq,
  656. .size = ARRAY_SIZE(omap3_idle_wakeup_p3_seq),
  657. .flags = TWL4030_WAKEUP3_SCRIPT,
  658. };
  659. static struct twl4030_script *omap3_idle_scripts[] = {
  660. &omap3_idle_wakeup_p12_script,
  661. &omap3_idle_wakeup_p3_script,
  662. &omap3_wrst_script,
  663. &omap3_idle_sleep_on_script,
  664. };
  665. /*
  666. * Recommended configuration based on "Recommended Sleep
  667. * Sequences for the Zoom Platform":
  668. * http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
  669. * Note that the type1 and type2 seem to be just the init order number
  670. * for type1 and type2 groups as specified in the document mentioned
  671. * above.
  672. */
  673. static struct twl4030_resconfig omap3_idle_rconfig[] = {
  674. TWL_REMAP_SLEEP(RES_VAUX1, TWL4030_RESCONFIG_UNDEF, 0, 0),
  675. TWL_REMAP_SLEEP(RES_VAUX2, TWL4030_RESCONFIG_UNDEF, 0, 0),
  676. TWL_REMAP_SLEEP(RES_VAUX3, TWL4030_RESCONFIG_UNDEF, 0, 0),
  677. TWL_REMAP_SLEEP(RES_VAUX4, TWL4030_RESCONFIG_UNDEF, 0, 0),
  678. TWL_REMAP_SLEEP(RES_VMMC1, TWL4030_RESCONFIG_UNDEF, 0, 0),
  679. TWL_REMAP_SLEEP(RES_VMMC2, TWL4030_RESCONFIG_UNDEF, 0, 0),
  680. TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1),
  681. TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0),
  682. TWL_REMAP_SLEEP(RES_VSIM, TWL4030_RESCONFIG_UNDEF, 0, 0),
  683. TWL_REMAP_SLEEP(RES_VDAC, TWL4030_RESCONFIG_UNDEF, 0, 0),
  684. TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2),
  685. TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2),
  686. TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2),
  687. TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2),
  688. TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1),
  689. TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1),
  690. TWL_REMAP_SLEEP(RES_VUSB_1V5, TWL4030_RESCONFIG_UNDEF, 0, 0),
  691. TWL_REMAP_SLEEP(RES_VUSB_1V8, TWL4030_RESCONFIG_UNDEF, 0, 0),
  692. TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0),
  693. /* Resource #20 USB charge pump skipped */
  694. TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1),
  695. TWL_REMAP_SLEEP(RES_NRES_PWRON, TWL_DEV_GRP_P123, 0, 1),
  696. TWL_REMAP_SLEEP(RES_CLKEN, TWL_DEV_GRP_P123, 3, 2),
  697. TWL_REMAP_SLEEP(RES_SYSEN, TWL_DEV_GRP_P123, 6, 1),
  698. TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, 0, 2),
  699. TWL_REMAP_SLEEP(RES_32KCLKOUT, TWL_DEV_GRP_P123, 0, 0),
  700. TWL_REMAP_SLEEP(RES_RESET, TWL_DEV_GRP_P123, 6, 0),
  701. TWL_REMAP_SLEEP(RES_MAIN_REF, TWL_DEV_GRP_P123, 0, 0),
  702. { /* Terminator */ },
  703. };
  704. static struct twl4030_power_data omap3_idle = {
  705. .scripts = omap3_idle_scripts,
  706. .num = ARRAY_SIZE(omap3_idle_scripts),
  707. .resource_config = omap3_idle_rconfig,
  708. };
  709. /* Disable 32 KiHz oscillator during idle */
  710. static struct twl4030_resconfig osc_off_rconfig[] = {
  711. TWL_REMAP_OFF(RES_CLKEN, DEV_GRP_P1 | DEV_GRP_P3, 3, 2),
  712. { /* Terminator */ },
  713. };
  714. static struct twl4030_power_data osc_off_idle = {
  715. .scripts = omap3_idle_scripts,
  716. .num = ARRAY_SIZE(omap3_idle_scripts),
  717. .resource_config = omap3_idle_rconfig,
  718. .board_config = osc_off_rconfig,
  719. };
  720. static struct twl4030_power_data omap3_idle_ac_quirk = {
  721. .scripts = omap3_idle_scripts,
  722. .num = ARRAY_SIZE(omap3_idle_scripts),
  723. .resource_config = omap3_idle_rconfig,
  724. .ac_charger_quirk = true,
  725. };
  726. static struct twl4030_power_data omap3_idle_ac_quirk_osc_off = {
  727. .scripts = omap3_idle_scripts,
  728. .num = ARRAY_SIZE(omap3_idle_scripts),
  729. .resource_config = omap3_idle_rconfig,
  730. .board_config = osc_off_rconfig,
  731. .ac_charger_quirk = true,
  732. };
  733. static const struct of_device_id twl4030_power_of_match[] = {
  734. {
  735. .compatible = "ti,twl4030-power",
  736. },
  737. {
  738. .compatible = "ti,twl4030-power-reset",
  739. .data = &omap3_reset,
  740. },
  741. {
  742. .compatible = "ti,twl4030-power-idle",
  743. .data = &omap3_idle,
  744. },
  745. {
  746. .compatible = "ti,twl4030-power-idle-osc-off",
  747. .data = &osc_off_idle,
  748. },
  749. {
  750. .compatible = "ti,twl4030-power-omap3-sdp",
  751. .data = &omap3_idle_ac_quirk,
  752. },
  753. {
  754. .compatible = "ti,twl4030-power-omap3-ldp",
  755. .data = &omap3_idle_ac_quirk_osc_off,
  756. },
  757. {
  758. .compatible = "ti,twl4030-power-omap3-evm",
  759. .data = &omap3_idle_ac_quirk,
  760. },
  761. { },
  762. };
  763. MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
  764. #endif /* CONFIG_OF */
  765. static int twl4030_power_probe(struct platform_device *pdev)
  766. {
  767. const struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev);
  768. struct device_node *node = pdev->dev.of_node;
  769. const struct of_device_id *match;
  770. int err = 0;
  771. int err2 = 0;
  772. u8 val;
  773. if (!pdata && !node) {
  774. dev_err(&pdev->dev, "Platform data is missing\n");
  775. return -EINVAL;
  776. }
  777. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  778. TWL4030_PM_MASTER_PROTECT_KEY);
  779. err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
  780. TWL4030_PM_MASTER_KEY_CFG2,
  781. TWL4030_PM_MASTER_PROTECT_KEY);
  782. if (err) {
  783. pr_err("TWL4030 Unable to unlock registers\n");
  784. return err;
  785. }
  786. match = of_match_device(of_match_ptr(twl4030_power_of_match),
  787. &pdev->dev);
  788. if (match && match->data)
  789. pdata = match->data;
  790. if (pdata) {
  791. err = twl4030_power_configure_scripts(pdata);
  792. if (err) {
  793. pr_err("TWL4030 failed to load scripts\n");
  794. goto relock;
  795. }
  796. err = twl4030_power_configure_resources(pdata);
  797. if (err) {
  798. pr_err("TWL4030 failed to configure resource\n");
  799. goto relock;
  800. }
  801. }
  802. /* Board has to be wired properly to use this feature */
  803. if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
  804. /* Default for SEQ_OFFSYNC is set, lets ensure this */
  805. err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
  806. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  807. if (err) {
  808. pr_warn("TWL4030 Unable to read registers\n");
  809. } else if (!(val & SEQ_OFFSYNC)) {
  810. val |= SEQ_OFFSYNC;
  811. err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
  812. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  813. if (err) {
  814. pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
  815. goto relock;
  816. }
  817. }
  818. pm_power_off = twl4030_power_off;
  819. }
  820. relock:
  821. err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  822. TWL4030_PM_MASTER_PROTECT_KEY);
  823. if (err2) {
  824. pr_err("TWL4030 Unable to relock registers\n");
  825. return err2;
  826. }
  827. return err;
  828. }
  829. static int twl4030_power_remove(struct platform_device *pdev)
  830. {
  831. return 0;
  832. }
  833. static struct platform_driver twl4030_power_driver = {
  834. .driver = {
  835. .name = "twl4030_power",
  836. .of_match_table = of_match_ptr(twl4030_power_of_match),
  837. },
  838. .probe = twl4030_power_probe,
  839. .remove = twl4030_power_remove,
  840. };
  841. module_platform_driver(twl4030_power_driver);
  842. MODULE_AUTHOR("Nokia Corporation");
  843. MODULE_AUTHOR("Texas Instruments, Inc.");
  844. MODULE_DESCRIPTION("Power management for TWL4030");
  845. MODULE_LICENSE("GPL");
  846. MODULE_ALIAS("platform:twl4030_power");