tps80031.c 15 KB

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  1. /*
  2. * tps80031.c -- TI TPS80031/TPS80032 mfd core driver.
  3. *
  4. * MFD core driver for TI TPS80031/TPS80032 Fully Integrated
  5. * Power Management with Power Path and Battery Charger
  6. *
  7. * Copyright (c) 2012, NVIDIA Corporation.
  8. *
  9. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation version 2.
  14. *
  15. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  16. * whether express or implied; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  23. * 02111-1307, USA
  24. */
  25. #include <linux/err.h>
  26. #include <linux/i2c.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/irq.h>
  30. #include <linux/mfd/core.h>
  31. #include <linux/mfd/tps80031.h>
  32. #include <linux/pm.h>
  33. #include <linux/regmap.h>
  34. #include <linux/slab.h>
  35. static struct resource tps80031_rtc_resources[] = {
  36. {
  37. .start = TPS80031_INT_RTC_ALARM,
  38. .end = TPS80031_INT_RTC_ALARM,
  39. .flags = IORESOURCE_IRQ,
  40. },
  41. };
  42. /* TPS80031 sub mfd devices */
  43. static const struct mfd_cell tps80031_cell[] = {
  44. {
  45. .name = "tps80031-pmic",
  46. },
  47. {
  48. .name = "tps80031-clock",
  49. },
  50. {
  51. .name = "tps80031-rtc",
  52. .num_resources = ARRAY_SIZE(tps80031_rtc_resources),
  53. .resources = tps80031_rtc_resources,
  54. },
  55. {
  56. .name = "tps80031-gpadc",
  57. },
  58. {
  59. .name = "tps80031-fuel-gauge",
  60. },
  61. {
  62. .name = "tps80031-charger",
  63. },
  64. };
  65. static int tps80031_slave_address[TPS80031_NUM_SLAVES] = {
  66. TPS80031_I2C_ID0_ADDR,
  67. TPS80031_I2C_ID1_ADDR,
  68. TPS80031_I2C_ID2_ADDR,
  69. TPS80031_I2C_ID3_ADDR,
  70. };
  71. struct tps80031_pupd_data {
  72. u8 reg;
  73. u8 pullup_bit;
  74. u8 pulldown_bit;
  75. };
  76. #define TPS80031_IRQ(_reg, _mask) \
  77. { \
  78. .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
  79. TPS80031_INT_MSK_LINE_A, \
  80. .mask = BIT(_mask), \
  81. }
  82. static const struct regmap_irq tps80031_main_irqs[] = {
  83. [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0),
  84. [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1),
  85. [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2),
  86. [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3),
  87. [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4),
  88. [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5),
  89. [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6),
  90. [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7),
  91. [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
  92. [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
  93. [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
  94. [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
  95. [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
  96. [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
  97. [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
  98. [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
  99. [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0),
  100. [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1),
  101. [TPS80031_INT_ID] = TPS80031_IRQ(C, 2),
  102. [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3),
  103. [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4),
  104. [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5),
  105. [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6),
  106. [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7),
  107. };
  108. static struct regmap_irq_chip tps80031_irq_chip = {
  109. .name = "tps80031",
  110. .irqs = tps80031_main_irqs,
  111. .num_irqs = ARRAY_SIZE(tps80031_main_irqs),
  112. .num_regs = 3,
  113. .status_base = TPS80031_INT_STS_A,
  114. .mask_base = TPS80031_INT_MSK_LINE_A,
  115. };
  116. #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \
  117. { \
  118. .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
  119. .pulldown_bit = _pulldown_bit, \
  120. .pullup_bit = _pullup_bit, \
  121. }
  122. static const struct tps80031_pupd_data tps80031_pupds[] = {
  123. [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)),
  124. [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)),
  125. [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)),
  126. [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)),
  127. [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)),
  128. [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)),
  129. [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0),
  130. [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)),
  131. [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)),
  132. [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)),
  133. [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0),
  134. [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)),
  135. [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)),
  136. [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)),
  137. [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)),
  138. };
  139. static struct tps80031 *tps80031_power_off_dev;
  140. int tps80031_ext_power_req_config(struct device *dev,
  141. unsigned long ext_ctrl_flag, int preq_bit,
  142. int state_reg_add, int trans_reg_add)
  143. {
  144. u8 res_ass_reg = 0;
  145. int preq_mask_bit = 0;
  146. int ret;
  147. if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ))
  148. return 0;
  149. if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) {
  150. res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
  151. preq_mask_bit = 5;
  152. } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) {
  153. res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
  154. preq_mask_bit = 6;
  155. } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) {
  156. res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
  157. preq_mask_bit = 7;
  158. }
  159. /* Configure REQ_ASS registers */
  160. ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg,
  161. BIT(preq_bit & 0x7));
  162. if (ret < 0) {
  163. dev_err(dev, "reg 0x%02x setbit failed, err = %d\n",
  164. res_ass_reg, ret);
  165. return ret;
  166. }
  167. /* Unmask the PREQ */
  168. ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1,
  169. TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
  170. if (ret < 0) {
  171. dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n",
  172. TPS80031_PHOENIX_MSK_TRANSITION, ret);
  173. return ret;
  174. }
  175. /* Switch regulator control to resource now */
  176. if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 |
  177. TPS80031_PWR_REQ_INPUT_PREQ3)) {
  178. ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add,
  179. 0x0, TPS80031_STATE_MASK);
  180. if (ret < 0)
  181. dev_err(dev, "reg 0x%02x update failed, err = %d\n",
  182. state_reg_add, ret);
  183. } else {
  184. ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add,
  185. TPS80031_TRANS_SLEEP_OFF,
  186. TPS80031_TRANS_SLEEP_MASK);
  187. if (ret < 0)
  188. dev_err(dev, "reg 0x%02x update failed, err = %d\n",
  189. trans_reg_add, ret);
  190. }
  191. return ret;
  192. }
  193. EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
  194. static void tps80031_power_off(void)
  195. {
  196. dev_info(tps80031_power_off_dev->dev, "switching off PMU\n");
  197. tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1,
  198. TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF);
  199. }
  200. static void tps80031_pupd_init(struct tps80031 *tps80031,
  201. struct tps80031_platform_data *pdata)
  202. {
  203. struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
  204. int data_size = pdata->pupd_init_data_size;
  205. int i;
  206. for (i = 0; i < data_size; ++i) {
  207. struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
  208. const struct tps80031_pupd_data *pupd =
  209. &tps80031_pupds[pupd_init->input_pin];
  210. u8 update_value = 0;
  211. u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
  212. if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
  213. update_value = pupd->pulldown_bit;
  214. else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
  215. update_value = pupd->pullup_bit;
  216. tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg,
  217. update_value, update_mask);
  218. }
  219. }
  220. static int tps80031_init_ext_control(struct tps80031 *tps80031,
  221. struct tps80031_platform_data *pdata)
  222. {
  223. struct device *dev = tps80031->dev;
  224. int ret;
  225. int i;
  226. /* Clear all external control for this rail */
  227. for (i = 0; i < 9; ++i) {
  228. ret = tps80031_write(dev, TPS80031_SLAVE_ID1,
  229. TPS80031_PREQ1_RES_ASS_A + i, 0);
  230. if (ret < 0) {
  231. dev_err(dev, "reg 0x%02x write failed, err = %d\n",
  232. TPS80031_PREQ1_RES_ASS_A + i, ret);
  233. return ret;
  234. }
  235. }
  236. /* Mask the PREQ */
  237. ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1,
  238. TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
  239. if (ret < 0) {
  240. dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n",
  241. TPS80031_PHOENIX_MSK_TRANSITION, ret);
  242. return ret;
  243. }
  244. return ret;
  245. }
  246. static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base)
  247. {
  248. struct device *dev = tps80031->dev;
  249. int i, ret;
  250. /*
  251. * The MASK register used for updating status register when
  252. * interrupt occurs and LINE register used to pass the status
  253. * to actual interrupt line. As per datasheet:
  254. * When INT_MSK_LINE [i] is set to 1, the associated interrupt
  255. * number i is INT line masked, which means that no interrupt is
  256. * generated on the INT line.
  257. * When INT_MSK_LINE [i] is set to 0, the associated interrupt
  258. * number i is line enabled: An interrupt is generated on the
  259. * INT line.
  260. * In any case, the INT_STS [i] status bit may or may not be updated,
  261. * only linked to the INT_MSK_STS [i] configuration register bit.
  262. *
  263. * When INT_MSK_STS [i] is set to 1, the associated interrupt number
  264. * i is status masked, which means that no interrupt is stored in
  265. * the INT_STS[i] status bit. Note that no interrupt number i is
  266. * generated on the INT line, even if the INT_MSK_LINE [i] register
  267. * bit is set to 0.
  268. * When INT_MSK_STS [i] is set to 0, the associated interrupt number i
  269. * is status enabled: An interrupt status is updated in the INT_STS [i]
  270. * register. The interrupt may or may not be generated on the INT line,
  271. * depending on the INT_MSK_LINE [i] configuration register bit.
  272. */
  273. for (i = 0; i < 3; i++)
  274. tps80031_write(dev, TPS80031_SLAVE_ID2,
  275. TPS80031_INT_MSK_STS_A + i, 0x00);
  276. ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq,
  277. IRQF_ONESHOT, irq_base,
  278. &tps80031_irq_chip, &tps80031->irq_data);
  279. if (ret < 0) {
  280. dev_err(dev, "add irq failed, err = %d\n", ret);
  281. return ret;
  282. }
  283. return ret;
  284. }
  285. static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
  286. {
  287. switch (reg) {
  288. case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE:
  289. return true;
  290. default:
  291. return false;
  292. }
  293. }
  294. static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
  295. {
  296. switch (reg) {
  297. case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG:
  298. case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7:
  299. case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG:
  300. case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
  301. case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST:
  302. case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
  303. case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
  304. case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
  305. case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
  306. case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
  307. case TPS80031_BACKUP_REG:
  308. return true;
  309. default:
  310. return false;
  311. }
  312. }
  313. static bool is_volatile_reg_id1(struct device *dev, unsigned int reg)
  314. {
  315. switch (reg) {
  316. case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
  317. case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
  318. case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
  319. case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
  320. case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
  321. case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
  322. return true;
  323. default:
  324. return false;
  325. }
  326. }
  327. static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
  328. {
  329. switch (reg) {
  330. case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION:
  331. case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1:
  332. case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB:
  333. case TPS80031_TOGGLE1 ... TPS80031_VIBMODE:
  334. case TPS80031_PWM1ON ... TPS80031_PWM2OFF:
  335. case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11:
  336. case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C:
  337. case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2:
  338. return true;
  339. default:
  340. return false;
  341. }
  342. }
  343. static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
  344. {
  345. switch (reg) {
  346. case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18:
  347. return true;
  348. default:
  349. return false;
  350. }
  351. }
  352. static const struct regmap_config tps80031_regmap_configs[] = {
  353. {
  354. .reg_bits = 8,
  355. .val_bits = 8,
  356. .writeable_reg = rd_wr_reg_id0,
  357. .readable_reg = rd_wr_reg_id0,
  358. .max_register = TPS80031_MAX_REGISTER,
  359. },
  360. {
  361. .reg_bits = 8,
  362. .val_bits = 8,
  363. .writeable_reg = rd_wr_reg_id1,
  364. .readable_reg = rd_wr_reg_id1,
  365. .volatile_reg = is_volatile_reg_id1,
  366. .max_register = TPS80031_MAX_REGISTER,
  367. },
  368. {
  369. .reg_bits = 8,
  370. .val_bits = 8,
  371. .writeable_reg = rd_wr_reg_id2,
  372. .readable_reg = rd_wr_reg_id2,
  373. .max_register = TPS80031_MAX_REGISTER,
  374. },
  375. {
  376. .reg_bits = 8,
  377. .val_bits = 8,
  378. .writeable_reg = rd_wr_reg_id3,
  379. .readable_reg = rd_wr_reg_id3,
  380. .max_register = TPS80031_MAX_REGISTER,
  381. },
  382. };
  383. static int tps80031_probe(struct i2c_client *client,
  384. const struct i2c_device_id *id)
  385. {
  386. struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev);
  387. struct tps80031 *tps80031;
  388. int ret;
  389. uint8_t es_version;
  390. uint8_t ep_ver;
  391. int i;
  392. if (!pdata) {
  393. dev_err(&client->dev, "tps80031 requires platform data\n");
  394. return -EINVAL;
  395. }
  396. tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
  397. if (!tps80031)
  398. return -ENOMEM;
  399. for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
  400. if (tps80031_slave_address[i] == client->addr)
  401. tps80031->clients[i] = client;
  402. else
  403. tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev,
  404. client->adapter, tps80031_slave_address[i]);
  405. if (IS_ERR(tps80031->clients[i])) {
  406. dev_err(&client->dev, "can't attach client %d\n", i);
  407. return PTR_ERR(tps80031->clients[i]);
  408. }
  409. i2c_set_clientdata(tps80031->clients[i], tps80031);
  410. tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i],
  411. &tps80031_regmap_configs[i]);
  412. if (IS_ERR(tps80031->regmap[i])) {
  413. ret = PTR_ERR(tps80031->regmap[i]);
  414. dev_err(&client->dev,
  415. "regmap %d init failed, err %d\n", i, ret);
  416. return ret;
  417. }
  418. }
  419. ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
  420. TPS80031_JTAGVERNUM, &es_version);
  421. if (ret < 0) {
  422. dev_err(&client->dev,
  423. "Silicon version number read failed: %d\n", ret);
  424. return ret;
  425. }
  426. ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
  427. TPS80031_EPROM_REV, &ep_ver);
  428. if (ret < 0) {
  429. dev_err(&client->dev,
  430. "Silicon eeprom version read failed: %d\n", ret);
  431. return ret;
  432. }
  433. dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
  434. es_version, ep_ver);
  435. tps80031->es_version = es_version;
  436. tps80031->dev = &client->dev;
  437. i2c_set_clientdata(client, tps80031);
  438. tps80031->chip_info = id->driver_data;
  439. ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
  440. if (ret) {
  441. dev_err(&client->dev, "IRQ init failed: %d\n", ret);
  442. return ret;
  443. }
  444. tps80031_pupd_init(tps80031, pdata);
  445. tps80031_init_ext_control(tps80031, pdata);
  446. ret = mfd_add_devices(tps80031->dev, -1,
  447. tps80031_cell, ARRAY_SIZE(tps80031_cell),
  448. NULL, 0,
  449. regmap_irq_get_domain(tps80031->irq_data));
  450. if (ret < 0) {
  451. dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
  452. goto fail_mfd_add;
  453. }
  454. if (pdata->use_power_off && !pm_power_off) {
  455. tps80031_power_off_dev = tps80031;
  456. pm_power_off = tps80031_power_off;
  457. }
  458. return 0;
  459. fail_mfd_add:
  460. regmap_del_irq_chip(client->irq, tps80031->irq_data);
  461. return ret;
  462. }
  463. static const struct i2c_device_id tps80031_id_table[] = {
  464. { "tps80031", TPS80031 },
  465. { "tps80032", TPS80032 },
  466. { }
  467. };
  468. static struct i2c_driver tps80031_driver = {
  469. .driver = {
  470. .name = "tps80031",
  471. .suppress_bind_attrs = true,
  472. },
  473. .probe = tps80031_probe,
  474. .id_table = tps80031_id_table,
  475. };
  476. static int __init tps80031_init(void)
  477. {
  478. return i2c_add_driver(&tps80031_driver);
  479. }
  480. subsys_initcall(tps80031_init);