tc6393xb.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Toshiba TC6393XB SoC support
  4. *
  5. * Copyright(c) 2005-2006 Chris Humbert
  6. * Copyright(c) 2005 Dirk Opfer
  7. * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
  8. * Copyright(c) 2007 Dmitry Baryshkov
  9. *
  10. * Based on code written by Sharp/Lineo for 2.4 kernels
  11. * Based on locomo.c
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/mfd/core.h>
  21. #include <linux/mfd/tmio.h>
  22. #include <linux/mfd/tc6393xb.h>
  23. #include <linux/gpio/driver.h>
  24. #include <linux/slab.h>
  25. #define SCR_REVID 0x08 /* b Revision ID */
  26. #define SCR_ISR 0x50 /* b Interrupt Status */
  27. #define SCR_IMR 0x52 /* b Interrupt Mask */
  28. #define SCR_IRR 0x54 /* b Interrupt Routing */
  29. #define SCR_GPER 0x60 /* w GP Enable */
  30. #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
  31. #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
  32. #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
  33. #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
  34. #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
  35. #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
  36. #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
  37. #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
  38. #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
  39. #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
  40. #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
  41. #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
  42. #define SCR_CCR 0x98 /* w Clock Control */
  43. #define SCR_PLL2CR 0x9a /* w PLL2 Control */
  44. #define SCR_PLL1CR 0x9c /* l PLL1 Control */
  45. #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
  46. #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
  47. #define SCR_FER 0xe0 /* b Function Enable */
  48. #define SCR_MCR 0xe4 /* w Mode Control */
  49. #define SCR_CONFIG 0xfc /* b Configuration Control */
  50. #define SCR_DEBUG 0xff /* b Debug */
  51. #define SCR_CCR_CK32K BIT(0)
  52. #define SCR_CCR_USBCK BIT(1)
  53. #define SCR_CCR_UNK1 BIT(4)
  54. #define SCR_CCR_MCLK_MASK (7 << 8)
  55. #define SCR_CCR_MCLK_OFF (0 << 8)
  56. #define SCR_CCR_MCLK_12 (1 << 8)
  57. #define SCR_CCR_MCLK_24 (2 << 8)
  58. #define SCR_CCR_MCLK_48 (3 << 8)
  59. #define SCR_CCR_HCLK_MASK (3 << 12)
  60. #define SCR_CCR_HCLK_24 (0 << 12)
  61. #define SCR_CCR_HCLK_48 (1 << 12)
  62. #define SCR_FER_USBEN BIT(0) /* USB host enable */
  63. #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
  64. #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
  65. #define SCR_MCR_RDY_MASK (3 << 0)
  66. #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
  67. #define SCR_MCR_RDY_TRISTATE (1 << 0)
  68. #define SCR_MCR_RDY_PUSHPULL (2 << 0)
  69. #define SCR_MCR_RDY_UNK BIT(2)
  70. #define SCR_MCR_RDY_EN BIT(3)
  71. #define SCR_MCR_INT_MASK (3 << 4)
  72. #define SCR_MCR_INT_OPENDRAIN (0 << 4)
  73. #define SCR_MCR_INT_TRISTATE (1 << 4)
  74. #define SCR_MCR_INT_PUSHPULL (2 << 4)
  75. #define SCR_MCR_INT_UNK BIT(6)
  76. #define SCR_MCR_INT_EN BIT(7)
  77. /* bits 8 - 16 are unknown */
  78. #define TC_GPIO_BIT(i) (1 << (i & 0x7))
  79. /*--------------------------------------------------------------------------*/
  80. struct tc6393xb {
  81. void __iomem *scr;
  82. struct gpio_chip gpio;
  83. struct clk *clk; /* 3,6 Mhz */
  84. raw_spinlock_t lock; /* protects RMW cycles */
  85. struct {
  86. u8 fer;
  87. u16 ccr;
  88. u8 gpi_bcr[3];
  89. u8 gpo_dsr[3];
  90. u8 gpo_doecr[3];
  91. } suspend_state;
  92. struct resource rscr;
  93. struct resource *iomem;
  94. int irq;
  95. int irq_base;
  96. };
  97. enum {
  98. TC6393XB_CELL_NAND,
  99. TC6393XB_CELL_MMC,
  100. TC6393XB_CELL_OHCI,
  101. TC6393XB_CELL_FB,
  102. };
  103. /*--------------------------------------------------------------------------*/
  104. static int tc6393xb_nand_enable(struct platform_device *nand)
  105. {
  106. struct tc6393xb *tc6393xb = dev_get_drvdata(nand->dev.parent);
  107. unsigned long flags;
  108. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  109. /* SMD buffer on */
  110. dev_dbg(nand->dev.parent, "SMD buffer on\n");
  111. tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
  112. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  113. return 0;
  114. }
  115. static struct resource tc6393xb_nand_resources[] = {
  116. {
  117. .start = 0x1000,
  118. .end = 0x1007,
  119. .flags = IORESOURCE_MEM,
  120. },
  121. {
  122. .start = 0x0100,
  123. .end = 0x01ff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. {
  127. .start = IRQ_TC6393_NAND,
  128. .end = IRQ_TC6393_NAND,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. static struct resource tc6393xb_mmc_resources[] = {
  133. {
  134. .start = 0x800,
  135. .end = 0x9ff,
  136. .flags = IORESOURCE_MEM,
  137. },
  138. {
  139. .start = IRQ_TC6393_MMC,
  140. .end = IRQ_TC6393_MMC,
  141. .flags = IORESOURCE_IRQ,
  142. },
  143. };
  144. static const struct resource tc6393xb_ohci_resources[] = {
  145. {
  146. .start = 0x3000,
  147. .end = 0x31ff,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. {
  151. .start = 0x0300,
  152. .end = 0x03ff,
  153. .flags = IORESOURCE_MEM,
  154. },
  155. {
  156. .start = 0x010000,
  157. .end = 0x017fff,
  158. .flags = IORESOURCE_MEM,
  159. },
  160. {
  161. .start = 0x018000,
  162. .end = 0x01ffff,
  163. .flags = IORESOURCE_MEM,
  164. },
  165. {
  166. .start = IRQ_TC6393_OHCI,
  167. .end = IRQ_TC6393_OHCI,
  168. .flags = IORESOURCE_IRQ,
  169. },
  170. };
  171. static struct resource tc6393xb_fb_resources[] = {
  172. {
  173. .start = 0x5000,
  174. .end = 0x51ff,
  175. .flags = IORESOURCE_MEM,
  176. },
  177. {
  178. .start = 0x0500,
  179. .end = 0x05ff,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. {
  183. .start = 0x100000,
  184. .end = 0x1fffff,
  185. .flags = IORESOURCE_MEM,
  186. },
  187. {
  188. .start = IRQ_TC6393_FB,
  189. .end = IRQ_TC6393_FB,
  190. .flags = IORESOURCE_IRQ,
  191. },
  192. };
  193. static int tc6393xb_ohci_enable(struct platform_device *dev)
  194. {
  195. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  196. unsigned long flags;
  197. u16 ccr;
  198. u8 fer;
  199. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  200. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  201. ccr |= SCR_CCR_USBCK;
  202. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  203. fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
  204. fer |= SCR_FER_USBEN;
  205. tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
  206. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  207. return 0;
  208. }
  209. static int tc6393xb_ohci_disable(struct platform_device *dev)
  210. {
  211. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  212. unsigned long flags;
  213. u16 ccr;
  214. u8 fer;
  215. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  216. fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
  217. fer &= ~SCR_FER_USBEN;
  218. tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
  219. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  220. ccr &= ~SCR_CCR_USBCK;
  221. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  222. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  223. return 0;
  224. }
  225. static int tc6393xb_ohci_suspend(struct platform_device *dev)
  226. {
  227. struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent);
  228. /* We can't properly store/restore OHCI state, so fail here */
  229. if (tcpd->resume_restore)
  230. return -EBUSY;
  231. return tc6393xb_ohci_disable(dev);
  232. }
  233. static int tc6393xb_fb_enable(struct platform_device *dev)
  234. {
  235. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  236. unsigned long flags;
  237. u16 ccr;
  238. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  239. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  240. ccr &= ~SCR_CCR_MCLK_MASK;
  241. ccr |= SCR_CCR_MCLK_48;
  242. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  243. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  244. return 0;
  245. }
  246. static int tc6393xb_fb_disable(struct platform_device *dev)
  247. {
  248. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  249. unsigned long flags;
  250. u16 ccr;
  251. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  252. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  253. ccr &= ~SCR_CCR_MCLK_MASK;
  254. ccr |= SCR_CCR_MCLK_OFF;
  255. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  256. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  257. return 0;
  258. }
  259. int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
  260. {
  261. struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
  262. u8 fer;
  263. unsigned long flags;
  264. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  265. fer = ioread8(tc6393xb->scr + SCR_FER);
  266. if (on)
  267. fer |= SCR_FER_SLCDEN;
  268. else
  269. fer &= ~SCR_FER_SLCDEN;
  270. iowrite8(fer, tc6393xb->scr + SCR_FER);
  271. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  272. return 0;
  273. }
  274. EXPORT_SYMBOL(tc6393xb_lcd_set_power);
  275. int tc6393xb_lcd_mode(struct platform_device *fb,
  276. const struct fb_videomode *mode) {
  277. struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
  278. unsigned long flags;
  279. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  280. iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
  281. iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
  282. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  283. return 0;
  284. }
  285. EXPORT_SYMBOL(tc6393xb_lcd_mode);
  286. static int tc6393xb_mmc_enable(struct platform_device *mmc)
  287. {
  288. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  289. tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
  290. tc6393xb_mmc_resources[0].start & 0xfffe);
  291. return 0;
  292. }
  293. static int tc6393xb_mmc_resume(struct platform_device *mmc)
  294. {
  295. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  296. tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
  297. tc6393xb_mmc_resources[0].start & 0xfffe);
  298. return 0;
  299. }
  300. static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
  301. {
  302. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  303. tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
  304. }
  305. static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
  306. {
  307. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  308. tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
  309. }
  310. static struct tmio_mmc_data tc6393xb_mmc_data = {
  311. .hclk = 24000000,
  312. .set_pwr = tc6393xb_mmc_pwr,
  313. .set_clk_div = tc6393xb_mmc_clk_div,
  314. };
  315. static struct mfd_cell tc6393xb_cells[] = {
  316. [TC6393XB_CELL_NAND] = {
  317. .name = "tmio-nand",
  318. .enable = tc6393xb_nand_enable,
  319. .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
  320. .resources = tc6393xb_nand_resources,
  321. },
  322. [TC6393XB_CELL_MMC] = {
  323. .name = "tmio-mmc",
  324. .enable = tc6393xb_mmc_enable,
  325. .resume = tc6393xb_mmc_resume,
  326. .platform_data = &tc6393xb_mmc_data,
  327. .pdata_size = sizeof(tc6393xb_mmc_data),
  328. .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
  329. .resources = tc6393xb_mmc_resources,
  330. },
  331. [TC6393XB_CELL_OHCI] = {
  332. .name = "tmio-ohci",
  333. .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
  334. .resources = tc6393xb_ohci_resources,
  335. .enable = tc6393xb_ohci_enable,
  336. .suspend = tc6393xb_ohci_suspend,
  337. .resume = tc6393xb_ohci_enable,
  338. .disable = tc6393xb_ohci_disable,
  339. },
  340. [TC6393XB_CELL_FB] = {
  341. .name = "tmio-fb",
  342. .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
  343. .resources = tc6393xb_fb_resources,
  344. .enable = tc6393xb_fb_enable,
  345. .suspend = tc6393xb_fb_disable,
  346. .resume = tc6393xb_fb_enable,
  347. .disable = tc6393xb_fb_disable,
  348. },
  349. };
  350. /*--------------------------------------------------------------------------*/
  351. static int tc6393xb_gpio_get(struct gpio_chip *chip,
  352. unsigned offset)
  353. {
  354. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  355. /* XXX: does dsr also represent inputs? */
  356. return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
  357. & TC_GPIO_BIT(offset));
  358. }
  359. static void __tc6393xb_gpio_set(struct gpio_chip *chip,
  360. unsigned offset, int value)
  361. {
  362. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  363. u8 dsr;
  364. dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
  365. if (value)
  366. dsr |= TC_GPIO_BIT(offset);
  367. else
  368. dsr &= ~TC_GPIO_BIT(offset);
  369. tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
  370. }
  371. static void tc6393xb_gpio_set(struct gpio_chip *chip,
  372. unsigned offset, int value)
  373. {
  374. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  375. unsigned long flags;
  376. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  377. __tc6393xb_gpio_set(chip, offset, value);
  378. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  379. }
  380. static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
  381. unsigned offset)
  382. {
  383. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  384. unsigned long flags;
  385. u8 doecr;
  386. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  387. doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  388. doecr &= ~TC_GPIO_BIT(offset);
  389. tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  390. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  391. return 0;
  392. }
  393. static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
  394. unsigned offset, int value)
  395. {
  396. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  397. unsigned long flags;
  398. u8 doecr;
  399. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  400. __tc6393xb_gpio_set(chip, offset, value);
  401. doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  402. doecr |= TC_GPIO_BIT(offset);
  403. tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  404. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  405. return 0;
  406. }
  407. static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
  408. {
  409. tc6393xb->gpio.label = "tc6393xb";
  410. tc6393xb->gpio.base = gpio_base;
  411. tc6393xb->gpio.ngpio = 16;
  412. tc6393xb->gpio.set = tc6393xb_gpio_set;
  413. tc6393xb->gpio.get = tc6393xb_gpio_get;
  414. tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
  415. tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
  416. return gpiochip_add_data(&tc6393xb->gpio, tc6393xb);
  417. }
  418. /*--------------------------------------------------------------------------*/
  419. static void tc6393xb_irq(struct irq_desc *desc)
  420. {
  421. struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
  422. unsigned int isr;
  423. unsigned int i, irq_base;
  424. irq_base = tc6393xb->irq_base;
  425. while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
  426. ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
  427. for (i = 0; i < TC6393XB_NR_IRQS; i++) {
  428. if (isr & (1 << i))
  429. generic_handle_irq(irq_base + i);
  430. }
  431. }
  432. static void tc6393xb_irq_ack(struct irq_data *data)
  433. {
  434. }
  435. static void tc6393xb_irq_mask(struct irq_data *data)
  436. {
  437. struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
  438. unsigned long flags;
  439. u8 imr;
  440. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  441. imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
  442. imr |= 1 << (data->irq - tc6393xb->irq_base);
  443. tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
  444. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  445. }
  446. static void tc6393xb_irq_unmask(struct irq_data *data)
  447. {
  448. struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
  449. unsigned long flags;
  450. u8 imr;
  451. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  452. imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
  453. imr &= ~(1 << (data->irq - tc6393xb->irq_base));
  454. tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
  455. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  456. }
  457. static struct irq_chip tc6393xb_chip = {
  458. .name = "tc6393xb",
  459. .irq_ack = tc6393xb_irq_ack,
  460. .irq_mask = tc6393xb_irq_mask,
  461. .irq_unmask = tc6393xb_irq_unmask,
  462. };
  463. static void tc6393xb_attach_irq(struct platform_device *dev)
  464. {
  465. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  466. unsigned int irq, irq_base;
  467. irq_base = tc6393xb->irq_base;
  468. for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
  469. irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
  470. irq_set_chip_data(irq, tc6393xb);
  471. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  472. }
  473. irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
  474. irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq,
  475. tc6393xb);
  476. }
  477. static void tc6393xb_detach_irq(struct platform_device *dev)
  478. {
  479. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  480. unsigned int irq, irq_base;
  481. irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL);
  482. irq_base = tc6393xb->irq_base;
  483. for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
  484. irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  485. irq_set_chip(irq, NULL);
  486. irq_set_chip_data(irq, NULL);
  487. }
  488. }
  489. /*--------------------------------------------------------------------------*/
  490. static int tc6393xb_probe(struct platform_device *dev)
  491. {
  492. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  493. struct tc6393xb *tc6393xb;
  494. struct resource *iomem, *rscr;
  495. int ret;
  496. iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
  497. if (!iomem)
  498. return -EINVAL;
  499. tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
  500. if (!tc6393xb) {
  501. ret = -ENOMEM;
  502. goto err_kzalloc;
  503. }
  504. raw_spin_lock_init(&tc6393xb->lock);
  505. platform_set_drvdata(dev, tc6393xb);
  506. ret = platform_get_irq(dev, 0);
  507. if (ret >= 0)
  508. tc6393xb->irq = ret;
  509. else
  510. goto err_noirq;
  511. tc6393xb->iomem = iomem;
  512. tc6393xb->irq_base = tcpd->irq_base;
  513. tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
  514. if (IS_ERR(tc6393xb->clk)) {
  515. ret = PTR_ERR(tc6393xb->clk);
  516. goto err_clk_get;
  517. }
  518. rscr = &tc6393xb->rscr;
  519. rscr->name = "tc6393xb-core";
  520. rscr->start = iomem->start;
  521. rscr->end = iomem->start + 0xff;
  522. rscr->flags = IORESOURCE_MEM;
  523. ret = request_resource(iomem, rscr);
  524. if (ret)
  525. goto err_request_scr;
  526. tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
  527. if (!tc6393xb->scr) {
  528. ret = -ENOMEM;
  529. goto err_ioremap;
  530. }
  531. ret = clk_prepare_enable(tc6393xb->clk);
  532. if (ret)
  533. goto err_clk_enable;
  534. ret = tcpd->enable(dev);
  535. if (ret)
  536. goto err_enable;
  537. iowrite8(0, tc6393xb->scr + SCR_FER);
  538. iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
  539. iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
  540. tc6393xb->scr + SCR_CCR);
  541. iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
  542. SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
  543. BIT(15), tc6393xb->scr + SCR_MCR);
  544. iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
  545. iowrite8(0, tc6393xb->scr + SCR_IRR);
  546. iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
  547. printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
  548. tmio_ioread8(tc6393xb->scr + SCR_REVID),
  549. (unsigned long) iomem->start, tc6393xb->irq);
  550. tc6393xb->gpio.base = -1;
  551. if (tcpd->gpio_base >= 0) {
  552. ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
  553. if (ret)
  554. goto err_gpio_add;
  555. }
  556. tc6393xb_attach_irq(dev);
  557. if (tcpd->setup) {
  558. ret = tcpd->setup(dev);
  559. if (ret)
  560. goto err_setup;
  561. }
  562. tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
  563. tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
  564. sizeof(*tcpd->nand_data);
  565. tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
  566. tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
  567. ret = mfd_add_devices(&dev->dev, dev->id,
  568. tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
  569. iomem, tcpd->irq_base, NULL);
  570. if (!ret)
  571. return 0;
  572. if (tcpd->teardown)
  573. tcpd->teardown(dev);
  574. err_setup:
  575. tc6393xb_detach_irq(dev);
  576. err_gpio_add:
  577. if (tc6393xb->gpio.base != -1)
  578. gpiochip_remove(&tc6393xb->gpio);
  579. tcpd->disable(dev);
  580. err_enable:
  581. clk_disable_unprepare(tc6393xb->clk);
  582. err_clk_enable:
  583. iounmap(tc6393xb->scr);
  584. err_ioremap:
  585. release_resource(&tc6393xb->rscr);
  586. err_request_scr:
  587. clk_put(tc6393xb->clk);
  588. err_noirq:
  589. err_clk_get:
  590. kfree(tc6393xb);
  591. err_kzalloc:
  592. return ret;
  593. }
  594. static int tc6393xb_remove(struct platform_device *dev)
  595. {
  596. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  597. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  598. int ret;
  599. mfd_remove_devices(&dev->dev);
  600. if (tcpd->teardown)
  601. tcpd->teardown(dev);
  602. tc6393xb_detach_irq(dev);
  603. if (tc6393xb->gpio.base != -1)
  604. gpiochip_remove(&tc6393xb->gpio);
  605. ret = tcpd->disable(dev);
  606. clk_disable_unprepare(tc6393xb->clk);
  607. iounmap(tc6393xb->scr);
  608. release_resource(&tc6393xb->rscr);
  609. clk_put(tc6393xb->clk);
  610. kfree(tc6393xb);
  611. return ret;
  612. }
  613. #ifdef CONFIG_PM
  614. static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
  615. {
  616. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  617. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  618. int i, ret;
  619. tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
  620. tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
  621. for (i = 0; i < 3; i++) {
  622. tc6393xb->suspend_state.gpo_dsr[i] =
  623. ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
  624. tc6393xb->suspend_state.gpo_doecr[i] =
  625. ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
  626. tc6393xb->suspend_state.gpi_bcr[i] =
  627. ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
  628. }
  629. ret = tcpd->suspend(dev);
  630. clk_disable_unprepare(tc6393xb->clk);
  631. return ret;
  632. }
  633. static int tc6393xb_resume(struct platform_device *dev)
  634. {
  635. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  636. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  637. int ret;
  638. int i;
  639. ret = clk_prepare_enable(tc6393xb->clk);
  640. if (ret)
  641. return ret;
  642. ret = tcpd->resume(dev);
  643. if (ret)
  644. return ret;
  645. if (!tcpd->resume_restore)
  646. return 0;
  647. iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
  648. iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
  649. iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
  650. iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
  651. SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
  652. BIT(15), tc6393xb->scr + SCR_MCR);
  653. iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
  654. iowrite8(0, tc6393xb->scr + SCR_IRR);
  655. iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
  656. for (i = 0; i < 3; i++) {
  657. iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
  658. tc6393xb->scr + SCR_GPO_DSR(i));
  659. iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
  660. tc6393xb->scr + SCR_GPO_DOECR(i));
  661. iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
  662. tc6393xb->scr + SCR_GPI_BCR(i));
  663. }
  664. return 0;
  665. }
  666. #else
  667. #define tc6393xb_suspend NULL
  668. #define tc6393xb_resume NULL
  669. #endif
  670. static struct platform_driver tc6393xb_driver = {
  671. .probe = tc6393xb_probe,
  672. .remove = tc6393xb_remove,
  673. .suspend = tc6393xb_suspend,
  674. .resume = tc6393xb_resume,
  675. .driver = {
  676. .name = "tc6393xb",
  677. },
  678. };
  679. static int __init tc6393xb_init(void)
  680. {
  681. return platform_driver_register(&tc6393xb_driver);
  682. }
  683. static void __exit tc6393xb_exit(void)
  684. {
  685. platform_driver_unregister(&tc6393xb_driver);
  686. }
  687. subsys_initcall(tc6393xb_init);
  688. module_exit(tc6393xb_exit);
  689. MODULE_LICENSE("GPL v2");
  690. MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
  691. MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
  692. MODULE_ALIAS("platform:tc6393xb");