stmpe.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6. */
  7. #ifndef __STMPE_H
  8. #define __STMPE_H
  9. #include <linux/device.h>
  10. #include <linux/mfd/core.h>
  11. #include <linux/mfd/stmpe.h>
  12. #include <linux/printk.h>
  13. #include <linux/types.h>
  14. extern const struct dev_pm_ops stmpe_dev_pm_ops;
  15. #ifdef STMPE_DUMP_BYTES
  16. static inline void stmpe_dump_bytes(const char *str, const void *buf,
  17. size_t len)
  18. {
  19. print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
  20. }
  21. #else
  22. static inline void stmpe_dump_bytes(const char *str, const void *buf,
  23. size_t len)
  24. {
  25. }
  26. #endif
  27. /**
  28. * struct stmpe_variant_block - information about block
  29. * @cell: base mfd cell
  30. * @irq: interrupt number to be added to each IORESOURCE_IRQ
  31. * in the cell
  32. * @block: block id; used for identification with platform data and for
  33. * enable and altfunc callbacks
  34. */
  35. struct stmpe_variant_block {
  36. const struct mfd_cell *cell;
  37. int irq;
  38. enum stmpe_block block;
  39. };
  40. /**
  41. * struct stmpe_variant_info - variant-specific information
  42. * @name: part name
  43. * @id_val: content of CHIPID register
  44. * @id_mask: bits valid in CHIPID register for comparison with id_val
  45. * @num_gpios: number of GPIOS
  46. * @af_bits: number of bits used to specify the alternate function
  47. * @regs: variant specific registers.
  48. * @blocks: list of blocks present on this device
  49. * @num_blocks: number of blocks present on this device
  50. * @num_irqs: number of internal IRQs available on this device
  51. * @enable: callback to enable the specified blocks.
  52. * Called with the I/O lock held.
  53. * @get_altfunc: callback to get the alternate function number for the
  54. * specific block
  55. * @enable_autosleep: callback to configure autosleep with specified timeout
  56. */
  57. struct stmpe_variant_info {
  58. const char *name;
  59. u16 id_val;
  60. u16 id_mask;
  61. int num_gpios;
  62. int af_bits;
  63. const u8 *regs;
  64. struct stmpe_variant_block *blocks;
  65. int num_blocks;
  66. int num_irqs;
  67. int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
  68. int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
  69. int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
  70. };
  71. /**
  72. * struct stmpe_client_info - i2c or spi specific routines/info
  73. * @data: client specific data
  74. * @read_byte: read single byte
  75. * @write_byte: write single byte
  76. * @read_block: read block or multiple bytes
  77. * @write_block: write block or multiple bytes
  78. * @init: client init routine, called during probe
  79. */
  80. struct stmpe_client_info {
  81. void *data;
  82. int irq;
  83. void *client;
  84. struct device *dev;
  85. int (*read_byte)(struct stmpe *stmpe, u8 reg);
  86. int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
  87. int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
  88. int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
  89. const u8 *values);
  90. void (*init)(struct stmpe *stmpe);
  91. };
  92. int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
  93. int stmpe_remove(struct stmpe *stmpe);
  94. #define STMPE_ICR_LSB_HIGH (1 << 2)
  95. #define STMPE_ICR_LSB_EDGE (1 << 1)
  96. #define STMPE_ICR_LSB_GIM (1 << 0)
  97. #define STMPE_SYS_CTRL_RESET (1 << 7)
  98. #define STMPE_SYS_CTRL_INT_EN (1 << 2)
  99. #define STMPE_SYS_CTRL_INT_HI (1 << 0)
  100. /*
  101. * STMPE801
  102. */
  103. #define STMPE801_ID 0x0108
  104. #define STMPE801_NR_INTERNAL_IRQS 1
  105. #define STMPE801_REG_CHIP_ID 0x00
  106. #define STMPE801_REG_VERSION_ID 0x02
  107. #define STMPE801_REG_SYS_CTRL 0x04
  108. #define STMPE801_REG_GPIO_INT_EN 0x08
  109. #define STMPE801_REG_GPIO_INT_STA 0x09
  110. #define STMPE801_REG_GPIO_MP_STA 0x10
  111. #define STMPE801_REG_GPIO_SET_PIN 0x11
  112. #define STMPE801_REG_GPIO_DIR 0x12
  113. /*
  114. * STMPE811
  115. */
  116. #define STMPE811_ID 0x0811
  117. #define STMPE811_IRQ_TOUCH_DET 0
  118. #define STMPE811_IRQ_FIFO_TH 1
  119. #define STMPE811_IRQ_FIFO_OFLOW 2
  120. #define STMPE811_IRQ_FIFO_FULL 3
  121. #define STMPE811_IRQ_FIFO_EMPTY 4
  122. #define STMPE811_IRQ_TEMP_SENS 5
  123. #define STMPE811_IRQ_ADC 6
  124. #define STMPE811_IRQ_GPIOC 7
  125. #define STMPE811_NR_INTERNAL_IRQS 8
  126. #define STMPE811_REG_CHIP_ID 0x00
  127. #define STMPE811_REG_SYS_CTRL 0x03
  128. #define STMPE811_REG_SYS_CTRL2 0x04
  129. #define STMPE811_REG_SPI_CFG 0x08
  130. #define STMPE811_REG_INT_CTRL 0x09
  131. #define STMPE811_REG_INT_EN 0x0A
  132. #define STMPE811_REG_INT_STA 0x0B
  133. #define STMPE811_REG_GPIO_INT_EN 0x0C
  134. #define STMPE811_REG_GPIO_INT_STA 0x0D
  135. #define STMPE811_REG_GPIO_SET_PIN 0x10
  136. #define STMPE811_REG_GPIO_CLR_PIN 0x11
  137. #define STMPE811_REG_GPIO_MP_STA 0x12
  138. #define STMPE811_REG_GPIO_DIR 0x13
  139. #define STMPE811_REG_GPIO_ED 0x14
  140. #define STMPE811_REG_GPIO_RE 0x15
  141. #define STMPE811_REG_GPIO_FE 0x16
  142. #define STMPE811_REG_GPIO_AF 0x17
  143. #define STMPE811_SYS_CTRL_RESET (1 << 1)
  144. #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
  145. #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
  146. #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
  147. #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
  148. /*
  149. * STMPE1600
  150. */
  151. #define STMPE1600_ID 0x0016
  152. #define STMPE1600_NR_INTERNAL_IRQS 16
  153. #define STMPE1600_REG_CHIP_ID 0x00
  154. #define STMPE1600_REG_SYS_CTRL 0x03
  155. #define STMPE1600_REG_IEGPIOR_LSB 0x08
  156. #define STMPE1600_REG_IEGPIOR_MSB 0x09
  157. #define STMPE1600_REG_ISGPIOR_LSB 0x0A
  158. #define STMPE1600_REG_ISGPIOR_MSB 0x0B
  159. #define STMPE1600_REG_GPMR_LSB 0x10
  160. #define STMPE1600_REG_GPMR_MSB 0x11
  161. #define STMPE1600_REG_GPSR_LSB 0x12
  162. #define STMPE1600_REG_GPSR_MSB 0x13
  163. #define STMPE1600_REG_GPDR_LSB 0x14
  164. #define STMPE1600_REG_GPDR_MSB 0x15
  165. #define STMPE1600_REG_GPPIR_LSB 0x16
  166. #define STMPE1600_REG_GPPIR_MSB 0x17
  167. /*
  168. * STMPE1601
  169. */
  170. #define STMPE1601_IRQ_GPIOC 8
  171. #define STMPE1601_IRQ_PWM3 7
  172. #define STMPE1601_IRQ_PWM2 6
  173. #define STMPE1601_IRQ_PWM1 5
  174. #define STMPE1601_IRQ_PWM0 4
  175. #define STMPE1601_IRQ_KEYPAD_OVER 2
  176. #define STMPE1601_IRQ_KEYPAD 1
  177. #define STMPE1601_IRQ_WAKEUP 0
  178. #define STMPE1601_NR_INTERNAL_IRQS 9
  179. #define STMPE1601_REG_SYS_CTRL 0x02
  180. #define STMPE1601_REG_SYS_CTRL2 0x03
  181. #define STMPE1601_REG_ICR_MSB 0x10
  182. #define STMPE1601_REG_ICR_LSB 0x11
  183. #define STMPE1601_REG_IER_MSB 0x12
  184. #define STMPE1601_REG_IER_LSB 0x13
  185. #define STMPE1601_REG_ISR_MSB 0x14
  186. #define STMPE1601_REG_ISR_LSB 0x15
  187. #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
  188. #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
  189. #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
  190. #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
  191. #define STMPE1601_REG_CHIP_ID 0x80
  192. #define STMPE1601_REG_GPIO_SET_MSB 0x82
  193. #define STMPE1601_REG_GPIO_SET_LSB 0x83
  194. #define STMPE1601_REG_GPIO_CLR_MSB 0x84
  195. #define STMPE1601_REG_GPIO_CLR_LSB 0x85
  196. #define STMPE1601_REG_GPIO_MP_MSB 0x86
  197. #define STMPE1601_REG_GPIO_MP_LSB 0x87
  198. #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
  199. #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
  200. #define STMPE1601_REG_GPIO_ED_MSB 0x8A
  201. #define STMPE1601_REG_GPIO_ED_LSB 0x8B
  202. #define STMPE1601_REG_GPIO_RE_MSB 0x8C
  203. #define STMPE1601_REG_GPIO_RE_LSB 0x8D
  204. #define STMPE1601_REG_GPIO_FE_MSB 0x8E
  205. #define STMPE1601_REG_GPIO_FE_LSB 0x8F
  206. #define STMPE1601_REG_GPIO_PU_MSB 0x90
  207. #define STMPE1601_REG_GPIO_PU_LSB 0x91
  208. #define STMPE1601_REG_GPIO_AF_U_MSB 0x92
  209. #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
  210. #define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
  211. #define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
  212. /* The 1601/2403 share the same masks */
  213. #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
  214. #define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
  215. /*
  216. * STMPE1801
  217. */
  218. #define STMPE1801_ID 0xc110
  219. #define STMPE1801_NR_INTERNAL_IRQS 5
  220. #define STMPE1801_IRQ_KEYPAD_COMBI 4
  221. #define STMPE1801_IRQ_GPIOC 3
  222. #define STMPE1801_IRQ_KEYPAD_OVER 2
  223. #define STMPE1801_IRQ_KEYPAD 1
  224. #define STMPE1801_IRQ_WAKEUP 0
  225. #define STMPE1801_REG_CHIP_ID 0x00
  226. #define STMPE1801_REG_SYS_CTRL 0x02
  227. #define STMPE1801_REG_INT_CTRL_LOW 0x04
  228. #define STMPE1801_REG_INT_EN_MASK_LOW 0x06
  229. #define STMPE1801_REG_INT_STA_LOW 0x08
  230. #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
  231. #define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
  232. #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
  233. #define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
  234. #define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
  235. #define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
  236. #define STMPE1801_REG_GPIO_SET_LOW 0x10
  237. #define STMPE1801_REG_GPIO_SET_MID 0x11
  238. #define STMPE1801_REG_GPIO_SET_HIGH 0x12
  239. #define STMPE1801_REG_GPIO_CLR_LOW 0x13
  240. #define STMPE1801_REG_GPIO_CLR_MID 0x14
  241. #define STMPE1801_REG_GPIO_CLR_HIGH 0x15
  242. #define STMPE1801_REG_GPIO_MP_LOW 0x16
  243. #define STMPE1801_REG_GPIO_MP_MID 0x17
  244. #define STMPE1801_REG_GPIO_MP_HIGH 0x18
  245. #define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
  246. #define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
  247. #define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
  248. #define STMPE1801_REG_GPIO_RE_LOW 0x1C
  249. #define STMPE1801_REG_GPIO_RE_MID 0x1D
  250. #define STMPE1801_REG_GPIO_RE_HIGH 0x1E
  251. #define STMPE1801_REG_GPIO_FE_LOW 0x1F
  252. #define STMPE1801_REG_GPIO_FE_MID 0x20
  253. #define STMPE1801_REG_GPIO_FE_HIGH 0x21
  254. #define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
  255. #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
  256. #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
  257. #define STMPE1801_MSK_INT_EN_KPC (1 << 1)
  258. #define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
  259. /*
  260. * STMPE24xx
  261. */
  262. #define STMPE24XX_IRQ_GPIOC 8
  263. #define STMPE24XX_IRQ_PWM2 7
  264. #define STMPE24XX_IRQ_PWM1 6
  265. #define STMPE24XX_IRQ_PWM0 5
  266. #define STMPE24XX_IRQ_ROT_OVER 4
  267. #define STMPE24XX_IRQ_ROT 3
  268. #define STMPE24XX_IRQ_KEYPAD_OVER 2
  269. #define STMPE24XX_IRQ_KEYPAD 1
  270. #define STMPE24XX_IRQ_WAKEUP 0
  271. #define STMPE24XX_NR_INTERNAL_IRQS 9
  272. #define STMPE24XX_REG_SYS_CTRL 0x02
  273. #define STMPE24XX_REG_SYS_CTRL2 0x03
  274. #define STMPE24XX_REG_ICR_MSB 0x10
  275. #define STMPE24XX_REG_ICR_LSB 0x11
  276. #define STMPE24XX_REG_IER_MSB 0x12
  277. #define STMPE24XX_REG_IER_LSB 0x13
  278. #define STMPE24XX_REG_ISR_MSB 0x14
  279. #define STMPE24XX_REG_ISR_LSB 0x15
  280. #define STMPE24XX_REG_IEGPIOR_MSB 0x16
  281. #define STMPE24XX_REG_IEGPIOR_CSB 0x17
  282. #define STMPE24XX_REG_IEGPIOR_LSB 0x18
  283. #define STMPE24XX_REG_ISGPIOR_MSB 0x19
  284. #define STMPE24XX_REG_ISGPIOR_CSB 0x1A
  285. #define STMPE24XX_REG_ISGPIOR_LSB 0x1B
  286. #define STMPE24XX_REG_CHIP_ID 0x80
  287. #define STMPE24XX_REG_GPSR_MSB 0x83
  288. #define STMPE24XX_REG_GPSR_CSB 0x84
  289. #define STMPE24XX_REG_GPSR_LSB 0x85
  290. #define STMPE24XX_REG_GPCR_MSB 0x86
  291. #define STMPE24XX_REG_GPCR_CSB 0x87
  292. #define STMPE24XX_REG_GPCR_LSB 0x88
  293. #define STMPE24XX_REG_GPDR_MSB 0x89
  294. #define STMPE24XX_REG_GPDR_CSB 0x8A
  295. #define STMPE24XX_REG_GPDR_LSB 0x8B
  296. #define STMPE24XX_REG_GPEDR_MSB 0x8C
  297. #define STMPE24XX_REG_GPEDR_CSB 0x8D
  298. #define STMPE24XX_REG_GPEDR_LSB 0x8E
  299. #define STMPE24XX_REG_GPRER_MSB 0x8F
  300. #define STMPE24XX_REG_GPRER_CSB 0x90
  301. #define STMPE24XX_REG_GPRER_LSB 0x91
  302. #define STMPE24XX_REG_GPFER_MSB 0x92
  303. #define STMPE24XX_REG_GPFER_CSB 0x93
  304. #define STMPE24XX_REG_GPFER_LSB 0x94
  305. #define STMPE24XX_REG_GPPUR_MSB 0x95
  306. #define STMPE24XX_REG_GPPUR_CSB 0x96
  307. #define STMPE24XX_REG_GPPUR_LSB 0x97
  308. #define STMPE24XX_REG_GPPDR_MSB 0x98
  309. #define STMPE24XX_REG_GPPDR_CSB 0x99
  310. #define STMPE24XX_REG_GPPDR_LSB 0x9A
  311. #define STMPE24XX_REG_GPAFR_U_MSB 0x9B
  312. #define STMPE24XX_REG_GPMR_MSB 0xA2
  313. #define STMPE24XX_REG_GPMR_CSB 0xA3
  314. #define STMPE24XX_REG_GPMR_LSB 0xA4
  315. #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
  316. #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
  317. #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
  318. #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
  319. #endif