stmpe.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST Microelectronics MFD: stmpe's driver
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  8. */
  9. #include <linux/err.h>
  10. #include <linux/gpio.h>
  11. #include <linux/export.h>
  12. #include <linux/kernel.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/pm.h>
  19. #include <linux/slab.h>
  20. #include <linux/mfd/core.h>
  21. #include <linux/delay.h>
  22. #include <linux/regulator/consumer.h>
  23. #include "stmpe.h"
  24. /**
  25. * struct stmpe_platform_data - STMPE platform data
  26. * @id: device id to distinguish between multiple STMPEs on the same board
  27. * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
  28. * @irq_trigger: IRQ trigger to use for the interrupt to the host
  29. * @autosleep: bool to enable/disable stmpe autosleep
  30. * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
  31. * @irq_over_gpio: true if gpio is used to get irq
  32. * @irq_gpio: gpio number over which irq will be requested (significant only if
  33. * irq_over_gpio is true)
  34. */
  35. struct stmpe_platform_data {
  36. int id;
  37. unsigned int blocks;
  38. unsigned int irq_trigger;
  39. bool autosleep;
  40. bool irq_over_gpio;
  41. int irq_gpio;
  42. int autosleep_timeout;
  43. };
  44. static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
  45. {
  46. return stmpe->variant->enable(stmpe, blocks, true);
  47. }
  48. static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
  49. {
  50. return stmpe->variant->enable(stmpe, blocks, false);
  51. }
  52. static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
  53. {
  54. int ret;
  55. ret = stmpe->ci->read_byte(stmpe, reg);
  56. if (ret < 0)
  57. dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
  58. dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
  59. return ret;
  60. }
  61. static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
  62. {
  63. int ret;
  64. dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
  65. ret = stmpe->ci->write_byte(stmpe, reg, val);
  66. if (ret < 0)
  67. dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
  68. return ret;
  69. }
  70. static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
  71. {
  72. int ret;
  73. ret = __stmpe_reg_read(stmpe, reg);
  74. if (ret < 0)
  75. return ret;
  76. ret &= ~mask;
  77. ret |= val;
  78. return __stmpe_reg_write(stmpe, reg, ret);
  79. }
  80. static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
  81. u8 *values)
  82. {
  83. int ret;
  84. ret = stmpe->ci->read_block(stmpe, reg, length, values);
  85. if (ret < 0)
  86. dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
  87. dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
  88. stmpe_dump_bytes("stmpe rd: ", values, length);
  89. return ret;
  90. }
  91. static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
  92. const u8 *values)
  93. {
  94. int ret;
  95. dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
  96. stmpe_dump_bytes("stmpe wr: ", values, length);
  97. ret = stmpe->ci->write_block(stmpe, reg, length, values);
  98. if (ret < 0)
  99. dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
  100. return ret;
  101. }
  102. /**
  103. * stmpe_enable - enable blocks on an STMPE device
  104. * @stmpe: Device to work on
  105. * @blocks: Mask of blocks (enum stmpe_block values) to enable
  106. */
  107. int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
  108. {
  109. int ret;
  110. mutex_lock(&stmpe->lock);
  111. ret = __stmpe_enable(stmpe, blocks);
  112. mutex_unlock(&stmpe->lock);
  113. return ret;
  114. }
  115. EXPORT_SYMBOL_GPL(stmpe_enable);
  116. /**
  117. * stmpe_disable - disable blocks on an STMPE device
  118. * @stmpe: Device to work on
  119. * @blocks: Mask of blocks (enum stmpe_block values) to enable
  120. */
  121. int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
  122. {
  123. int ret;
  124. mutex_lock(&stmpe->lock);
  125. ret = __stmpe_disable(stmpe, blocks);
  126. mutex_unlock(&stmpe->lock);
  127. return ret;
  128. }
  129. EXPORT_SYMBOL_GPL(stmpe_disable);
  130. /**
  131. * stmpe_reg_read() - read a single STMPE register
  132. * @stmpe: Device to read from
  133. * @reg: Register to read
  134. */
  135. int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
  136. {
  137. int ret;
  138. mutex_lock(&stmpe->lock);
  139. ret = __stmpe_reg_read(stmpe, reg);
  140. mutex_unlock(&stmpe->lock);
  141. return ret;
  142. }
  143. EXPORT_SYMBOL_GPL(stmpe_reg_read);
  144. /**
  145. * stmpe_reg_write() - write a single STMPE register
  146. * @stmpe: Device to write to
  147. * @reg: Register to write
  148. * @val: Value to write
  149. */
  150. int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
  151. {
  152. int ret;
  153. mutex_lock(&stmpe->lock);
  154. ret = __stmpe_reg_write(stmpe, reg, val);
  155. mutex_unlock(&stmpe->lock);
  156. return ret;
  157. }
  158. EXPORT_SYMBOL_GPL(stmpe_reg_write);
  159. /**
  160. * stmpe_set_bits() - set the value of a bitfield in a STMPE register
  161. * @stmpe: Device to write to
  162. * @reg: Register to write
  163. * @mask: Mask of bits to set
  164. * @val: Value to set
  165. */
  166. int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
  167. {
  168. int ret;
  169. mutex_lock(&stmpe->lock);
  170. ret = __stmpe_set_bits(stmpe, reg, mask, val);
  171. mutex_unlock(&stmpe->lock);
  172. return ret;
  173. }
  174. EXPORT_SYMBOL_GPL(stmpe_set_bits);
  175. /**
  176. * stmpe_block_read() - read multiple STMPE registers
  177. * @stmpe: Device to read from
  178. * @reg: First register
  179. * @length: Number of registers
  180. * @values: Buffer to write to
  181. */
  182. int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
  183. {
  184. int ret;
  185. mutex_lock(&stmpe->lock);
  186. ret = __stmpe_block_read(stmpe, reg, length, values);
  187. mutex_unlock(&stmpe->lock);
  188. return ret;
  189. }
  190. EXPORT_SYMBOL_GPL(stmpe_block_read);
  191. /**
  192. * stmpe_block_write() - write multiple STMPE registers
  193. * @stmpe: Device to write to
  194. * @reg: First register
  195. * @length: Number of registers
  196. * @values: Values to write
  197. */
  198. int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
  199. const u8 *values)
  200. {
  201. int ret;
  202. mutex_lock(&stmpe->lock);
  203. ret = __stmpe_block_write(stmpe, reg, length, values);
  204. mutex_unlock(&stmpe->lock);
  205. return ret;
  206. }
  207. EXPORT_SYMBOL_GPL(stmpe_block_write);
  208. /**
  209. * stmpe_set_altfunc()- set the alternate function for STMPE pins
  210. * @stmpe: Device to configure
  211. * @pins: Bitmask of pins to affect
  212. * @block: block to enable alternate functions for
  213. *
  214. * @pins is assumed to have a bit set for each of the bits whose alternate
  215. * function is to be changed, numbered according to the GPIOXY numbers.
  216. *
  217. * If the GPIO module is not enabled, this function automatically enables it in
  218. * order to perform the change.
  219. */
  220. int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
  221. {
  222. struct stmpe_variant_info *variant = stmpe->variant;
  223. u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
  224. int af_bits = variant->af_bits;
  225. int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
  226. int mask = (1 << af_bits) - 1;
  227. u8 regs[8];
  228. int af, afperreg, ret;
  229. if (!variant->get_altfunc)
  230. return 0;
  231. afperreg = 8 / af_bits;
  232. mutex_lock(&stmpe->lock);
  233. ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
  234. if (ret < 0)
  235. goto out;
  236. ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
  237. if (ret < 0)
  238. goto out;
  239. af = variant->get_altfunc(stmpe, block);
  240. while (pins) {
  241. int pin = __ffs(pins);
  242. int regoffset = numregs - (pin / afperreg) - 1;
  243. int pos = (pin % afperreg) * (8 / afperreg);
  244. regs[regoffset] &= ~(mask << pos);
  245. regs[regoffset] |= af << pos;
  246. pins &= ~(1 << pin);
  247. }
  248. ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
  249. out:
  250. mutex_unlock(&stmpe->lock);
  251. return ret;
  252. }
  253. EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
  254. /*
  255. * GPIO (all variants)
  256. */
  257. static struct resource stmpe_gpio_resources[] = {
  258. /* Start and end filled dynamically */
  259. {
  260. .flags = IORESOURCE_IRQ,
  261. },
  262. };
  263. static const struct mfd_cell stmpe_gpio_cell = {
  264. .name = "stmpe-gpio",
  265. .of_compatible = "st,stmpe-gpio",
  266. .resources = stmpe_gpio_resources,
  267. .num_resources = ARRAY_SIZE(stmpe_gpio_resources),
  268. };
  269. static const struct mfd_cell stmpe_gpio_cell_noirq = {
  270. .name = "stmpe-gpio",
  271. .of_compatible = "st,stmpe-gpio",
  272. /* gpio cell resources consist of an irq only so no resources here */
  273. };
  274. /*
  275. * Keypad (1601, 2401, 2403)
  276. */
  277. static struct resource stmpe_keypad_resources[] = {
  278. {
  279. .name = "KEYPAD",
  280. .flags = IORESOURCE_IRQ,
  281. },
  282. {
  283. .name = "KEYPAD_OVER",
  284. .flags = IORESOURCE_IRQ,
  285. },
  286. };
  287. static const struct mfd_cell stmpe_keypad_cell = {
  288. .name = "stmpe-keypad",
  289. .of_compatible = "st,stmpe-keypad",
  290. .resources = stmpe_keypad_resources,
  291. .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
  292. };
  293. /*
  294. * PWM (1601, 2401, 2403)
  295. */
  296. static struct resource stmpe_pwm_resources[] = {
  297. {
  298. .name = "PWM0",
  299. .flags = IORESOURCE_IRQ,
  300. },
  301. {
  302. .name = "PWM1",
  303. .flags = IORESOURCE_IRQ,
  304. },
  305. {
  306. .name = "PWM2",
  307. .flags = IORESOURCE_IRQ,
  308. },
  309. };
  310. static const struct mfd_cell stmpe_pwm_cell = {
  311. .name = "stmpe-pwm",
  312. .of_compatible = "st,stmpe-pwm",
  313. .resources = stmpe_pwm_resources,
  314. .num_resources = ARRAY_SIZE(stmpe_pwm_resources),
  315. };
  316. /*
  317. * STMPE801
  318. */
  319. static const u8 stmpe801_regs[] = {
  320. [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
  321. [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
  322. [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
  323. [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
  324. [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
  325. [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
  326. [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
  327. [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
  328. };
  329. static struct stmpe_variant_block stmpe801_blocks[] = {
  330. {
  331. .cell = &stmpe_gpio_cell,
  332. .irq = 0,
  333. .block = STMPE_BLOCK_GPIO,
  334. },
  335. };
  336. static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
  337. {
  338. .cell = &stmpe_gpio_cell_noirq,
  339. .block = STMPE_BLOCK_GPIO,
  340. },
  341. };
  342. static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
  343. bool enable)
  344. {
  345. if (blocks & STMPE_BLOCK_GPIO)
  346. return 0;
  347. else
  348. return -EINVAL;
  349. }
  350. static struct stmpe_variant_info stmpe801 = {
  351. .name = "stmpe801",
  352. .id_val = STMPE801_ID,
  353. .id_mask = 0xffff,
  354. .num_gpios = 8,
  355. .regs = stmpe801_regs,
  356. .blocks = stmpe801_blocks,
  357. .num_blocks = ARRAY_SIZE(stmpe801_blocks),
  358. .num_irqs = STMPE801_NR_INTERNAL_IRQS,
  359. .enable = stmpe801_enable,
  360. };
  361. static struct stmpe_variant_info stmpe801_noirq = {
  362. .name = "stmpe801",
  363. .id_val = STMPE801_ID,
  364. .id_mask = 0xffff,
  365. .num_gpios = 8,
  366. .regs = stmpe801_regs,
  367. .blocks = stmpe801_blocks_noirq,
  368. .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
  369. .enable = stmpe801_enable,
  370. };
  371. /*
  372. * Touchscreen (STMPE811 or STMPE610)
  373. */
  374. static struct resource stmpe_ts_resources[] = {
  375. {
  376. .name = "TOUCH_DET",
  377. .flags = IORESOURCE_IRQ,
  378. },
  379. {
  380. .name = "FIFO_TH",
  381. .flags = IORESOURCE_IRQ,
  382. },
  383. };
  384. static const struct mfd_cell stmpe_ts_cell = {
  385. .name = "stmpe-ts",
  386. .of_compatible = "st,stmpe-ts",
  387. .resources = stmpe_ts_resources,
  388. .num_resources = ARRAY_SIZE(stmpe_ts_resources),
  389. };
  390. /*
  391. * ADC (STMPE811)
  392. */
  393. static struct resource stmpe_adc_resources[] = {
  394. {
  395. .name = "STMPE_TEMP_SENS",
  396. .flags = IORESOURCE_IRQ,
  397. },
  398. {
  399. .name = "STMPE_ADC",
  400. .flags = IORESOURCE_IRQ,
  401. },
  402. };
  403. static const struct mfd_cell stmpe_adc_cell = {
  404. .name = "stmpe-adc",
  405. .of_compatible = "st,stmpe-adc",
  406. .resources = stmpe_adc_resources,
  407. .num_resources = ARRAY_SIZE(stmpe_adc_resources),
  408. };
  409. /*
  410. * STMPE811 or STMPE610
  411. */
  412. static const u8 stmpe811_regs[] = {
  413. [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
  414. [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
  415. [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
  416. [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
  417. [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
  418. [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
  419. [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
  420. [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
  421. [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
  422. [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
  423. [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
  424. [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
  425. [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
  426. [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
  427. [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
  428. [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
  429. };
  430. static struct stmpe_variant_block stmpe811_blocks[] = {
  431. {
  432. .cell = &stmpe_gpio_cell,
  433. .irq = STMPE811_IRQ_GPIOC,
  434. .block = STMPE_BLOCK_GPIO,
  435. },
  436. {
  437. .cell = &stmpe_ts_cell,
  438. .irq = STMPE811_IRQ_TOUCH_DET,
  439. .block = STMPE_BLOCK_TOUCHSCREEN,
  440. },
  441. {
  442. .cell = &stmpe_adc_cell,
  443. .irq = STMPE811_IRQ_TEMP_SENS,
  444. .block = STMPE_BLOCK_ADC,
  445. },
  446. };
  447. static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
  448. bool enable)
  449. {
  450. unsigned int mask = 0;
  451. if (blocks & STMPE_BLOCK_GPIO)
  452. mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
  453. if (blocks & STMPE_BLOCK_ADC)
  454. mask |= STMPE811_SYS_CTRL2_ADC_OFF;
  455. if (blocks & STMPE_BLOCK_TOUCHSCREEN)
  456. mask |= STMPE811_SYS_CTRL2_TSC_OFF;
  457. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
  458. enable ? 0 : mask);
  459. }
  460. int stmpe811_adc_common_init(struct stmpe *stmpe)
  461. {
  462. int ret;
  463. u8 adc_ctrl1, adc_ctrl1_mask;
  464. adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
  465. STMPE_MOD_12B(stmpe->mod_12b) |
  466. STMPE_REF_SEL(stmpe->ref_sel);
  467. adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
  468. STMPE_REF_SEL(0xff);
  469. ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
  470. adc_ctrl1_mask, adc_ctrl1);
  471. if (ret) {
  472. dev_err(stmpe->dev, "Could not setup ADC\n");
  473. return ret;
  474. }
  475. ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
  476. STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
  477. if (ret) {
  478. dev_err(stmpe->dev, "Could not setup ADC\n");
  479. return ret;
  480. }
  481. return 0;
  482. }
  483. EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
  484. static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  485. {
  486. /* 0 for touchscreen, 1 for GPIO */
  487. return block != STMPE_BLOCK_TOUCHSCREEN;
  488. }
  489. static struct stmpe_variant_info stmpe811 = {
  490. .name = "stmpe811",
  491. .id_val = 0x0811,
  492. .id_mask = 0xffff,
  493. .num_gpios = 8,
  494. .af_bits = 1,
  495. .regs = stmpe811_regs,
  496. .blocks = stmpe811_blocks,
  497. .num_blocks = ARRAY_SIZE(stmpe811_blocks),
  498. .num_irqs = STMPE811_NR_INTERNAL_IRQS,
  499. .enable = stmpe811_enable,
  500. .get_altfunc = stmpe811_get_altfunc,
  501. };
  502. /* Similar to 811, except number of gpios */
  503. static struct stmpe_variant_info stmpe610 = {
  504. .name = "stmpe610",
  505. .id_val = 0x0811,
  506. .id_mask = 0xffff,
  507. .num_gpios = 6,
  508. .af_bits = 1,
  509. .regs = stmpe811_regs,
  510. .blocks = stmpe811_blocks,
  511. .num_blocks = ARRAY_SIZE(stmpe811_blocks),
  512. .num_irqs = STMPE811_NR_INTERNAL_IRQS,
  513. .enable = stmpe811_enable,
  514. .get_altfunc = stmpe811_get_altfunc,
  515. };
  516. /*
  517. * STMPE1600
  518. * Compared to all others STMPE variant, LSB and MSB regs are located in this
  519. * order : LSB addr
  520. * MSB addr + 1
  521. * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
  522. */
  523. static const u8 stmpe1600_regs[] = {
  524. [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID,
  525. [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL,
  526. [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL,
  527. [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB,
  528. [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB,
  529. [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB,
  530. [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB,
  531. [STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB,
  532. [STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB,
  533. [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB,
  534. [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB,
  535. [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
  536. [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
  537. [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
  538. };
  539. static struct stmpe_variant_block stmpe1600_blocks[] = {
  540. {
  541. .cell = &stmpe_gpio_cell,
  542. .irq = 0,
  543. .block = STMPE_BLOCK_GPIO,
  544. },
  545. };
  546. static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
  547. bool enable)
  548. {
  549. if (blocks & STMPE_BLOCK_GPIO)
  550. return 0;
  551. else
  552. return -EINVAL;
  553. }
  554. static struct stmpe_variant_info stmpe1600 = {
  555. .name = "stmpe1600",
  556. .id_val = STMPE1600_ID,
  557. .id_mask = 0xffff,
  558. .num_gpios = 16,
  559. .af_bits = 0,
  560. .regs = stmpe1600_regs,
  561. .blocks = stmpe1600_blocks,
  562. .num_blocks = ARRAY_SIZE(stmpe1600_blocks),
  563. .num_irqs = STMPE1600_NR_INTERNAL_IRQS,
  564. .enable = stmpe1600_enable,
  565. };
  566. /*
  567. * STMPE1601
  568. */
  569. static const u8 stmpe1601_regs[] = {
  570. [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
  571. [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
  572. [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
  573. [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
  574. [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
  575. [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
  576. [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
  577. [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
  578. [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
  579. [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
  580. [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
  581. [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
  582. [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
  583. [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
  584. [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
  585. [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
  586. [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
  587. [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
  588. [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
  589. [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
  590. [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
  591. [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
  592. [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
  593. [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
  594. [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
  595. [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
  596. };
  597. static struct stmpe_variant_block stmpe1601_blocks[] = {
  598. {
  599. .cell = &stmpe_gpio_cell,
  600. .irq = STMPE1601_IRQ_GPIOC,
  601. .block = STMPE_BLOCK_GPIO,
  602. },
  603. {
  604. .cell = &stmpe_keypad_cell,
  605. .irq = STMPE1601_IRQ_KEYPAD,
  606. .block = STMPE_BLOCK_KEYPAD,
  607. },
  608. {
  609. .cell = &stmpe_pwm_cell,
  610. .irq = STMPE1601_IRQ_PWM0,
  611. .block = STMPE_BLOCK_PWM,
  612. },
  613. };
  614. /* supported autosleep timeout delay (in msecs) */
  615. static const int stmpe_autosleep_delay[] = {
  616. 4, 16, 32, 64, 128, 256, 512, 1024,
  617. };
  618. static int stmpe_round_timeout(int timeout)
  619. {
  620. int i;
  621. for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
  622. if (stmpe_autosleep_delay[i] >= timeout)
  623. return i;
  624. }
  625. /*
  626. * requests for delays longer than supported should not return the
  627. * longest supported delay
  628. */
  629. return -EINVAL;
  630. }
  631. static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
  632. {
  633. int ret;
  634. if (!stmpe->variant->enable_autosleep)
  635. return -ENOSYS;
  636. mutex_lock(&stmpe->lock);
  637. ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
  638. mutex_unlock(&stmpe->lock);
  639. return ret;
  640. }
  641. /*
  642. * Both stmpe 1601/2403 support same layout for autosleep
  643. */
  644. static int stmpe1601_autosleep(struct stmpe *stmpe,
  645. int autosleep_timeout)
  646. {
  647. int ret, timeout;
  648. /* choose the best available timeout */
  649. timeout = stmpe_round_timeout(autosleep_timeout);
  650. if (timeout < 0) {
  651. dev_err(stmpe->dev, "invalid timeout\n");
  652. return timeout;
  653. }
  654. ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
  655. STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
  656. timeout);
  657. if (ret < 0)
  658. return ret;
  659. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
  660. STPME1601_AUTOSLEEP_ENABLE,
  661. STPME1601_AUTOSLEEP_ENABLE);
  662. }
  663. static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
  664. bool enable)
  665. {
  666. unsigned int mask = 0;
  667. if (blocks & STMPE_BLOCK_GPIO)
  668. mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
  669. else
  670. mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
  671. if (blocks & STMPE_BLOCK_KEYPAD)
  672. mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
  673. else
  674. mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
  675. if (blocks & STMPE_BLOCK_PWM)
  676. mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
  677. else
  678. mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
  679. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
  680. enable ? mask : 0);
  681. }
  682. static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  683. {
  684. switch (block) {
  685. case STMPE_BLOCK_PWM:
  686. return 2;
  687. case STMPE_BLOCK_KEYPAD:
  688. return 1;
  689. case STMPE_BLOCK_GPIO:
  690. default:
  691. return 0;
  692. }
  693. }
  694. static struct stmpe_variant_info stmpe1601 = {
  695. .name = "stmpe1601",
  696. .id_val = 0x0210,
  697. .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
  698. .num_gpios = 16,
  699. .af_bits = 2,
  700. .regs = stmpe1601_regs,
  701. .blocks = stmpe1601_blocks,
  702. .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
  703. .num_irqs = STMPE1601_NR_INTERNAL_IRQS,
  704. .enable = stmpe1601_enable,
  705. .get_altfunc = stmpe1601_get_altfunc,
  706. .enable_autosleep = stmpe1601_autosleep,
  707. };
  708. /*
  709. * STMPE1801
  710. */
  711. static const u8 stmpe1801_regs[] = {
  712. [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
  713. [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
  714. [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
  715. [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
  716. [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
  717. [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
  718. [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
  719. [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
  720. [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
  721. [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
  722. [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
  723. [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
  724. [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
  725. [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
  726. [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
  727. [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
  728. [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
  729. [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
  730. [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
  731. [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
  732. [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
  733. [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
  734. [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
  735. [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
  736. [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
  737. [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
  738. [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
  739. [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
  740. };
  741. static struct stmpe_variant_block stmpe1801_blocks[] = {
  742. {
  743. .cell = &stmpe_gpio_cell,
  744. .irq = STMPE1801_IRQ_GPIOC,
  745. .block = STMPE_BLOCK_GPIO,
  746. },
  747. {
  748. .cell = &stmpe_keypad_cell,
  749. .irq = STMPE1801_IRQ_KEYPAD,
  750. .block = STMPE_BLOCK_KEYPAD,
  751. },
  752. };
  753. static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
  754. bool enable)
  755. {
  756. unsigned int mask = 0;
  757. if (blocks & STMPE_BLOCK_GPIO)
  758. mask |= STMPE1801_MSK_INT_EN_GPIO;
  759. if (blocks & STMPE_BLOCK_KEYPAD)
  760. mask |= STMPE1801_MSK_INT_EN_KPC;
  761. return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
  762. enable ? mask : 0);
  763. }
  764. static int stmpe_reset(struct stmpe *stmpe)
  765. {
  766. u16 id_val = stmpe->variant->id_val;
  767. unsigned long timeout;
  768. int ret = 0;
  769. u8 reset_bit;
  770. if (id_val == STMPE811_ID)
  771. /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
  772. reset_bit = STMPE811_SYS_CTRL_RESET;
  773. else
  774. /* all other STMPE variant use bit 7 of SYS_CTRL register */
  775. reset_bit = STMPE_SYS_CTRL_RESET;
  776. ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
  777. reset_bit, reset_bit);
  778. if (ret < 0)
  779. return ret;
  780. msleep(10);
  781. timeout = jiffies + msecs_to_jiffies(100);
  782. while (time_before(jiffies, timeout)) {
  783. ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
  784. if (ret < 0)
  785. return ret;
  786. if (!(ret & reset_bit))
  787. return 0;
  788. usleep_range(100, 200);
  789. }
  790. return -EIO;
  791. }
  792. static struct stmpe_variant_info stmpe1801 = {
  793. .name = "stmpe1801",
  794. .id_val = STMPE1801_ID,
  795. .id_mask = 0xfff0,
  796. .num_gpios = 18,
  797. .af_bits = 0,
  798. .regs = stmpe1801_regs,
  799. .blocks = stmpe1801_blocks,
  800. .num_blocks = ARRAY_SIZE(stmpe1801_blocks),
  801. .num_irqs = STMPE1801_NR_INTERNAL_IRQS,
  802. .enable = stmpe1801_enable,
  803. /* stmpe1801 do not have any gpio alternate function */
  804. .get_altfunc = NULL,
  805. };
  806. /*
  807. * STMPE24XX
  808. */
  809. static const u8 stmpe24xx_regs[] = {
  810. [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
  811. [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
  812. [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
  813. [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
  814. [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
  815. [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
  816. [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
  817. [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
  818. [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
  819. [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
  820. [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
  821. [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
  822. [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
  823. [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
  824. [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
  825. [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
  826. [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
  827. [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
  828. [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
  829. [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
  830. [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
  831. [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
  832. [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
  833. [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
  834. [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
  835. [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
  836. [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
  837. [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
  838. [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
  839. [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
  840. [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
  841. [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
  842. [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
  843. [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
  844. [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
  845. };
  846. static struct stmpe_variant_block stmpe24xx_blocks[] = {
  847. {
  848. .cell = &stmpe_gpio_cell,
  849. .irq = STMPE24XX_IRQ_GPIOC,
  850. .block = STMPE_BLOCK_GPIO,
  851. },
  852. {
  853. .cell = &stmpe_keypad_cell,
  854. .irq = STMPE24XX_IRQ_KEYPAD,
  855. .block = STMPE_BLOCK_KEYPAD,
  856. },
  857. {
  858. .cell = &stmpe_pwm_cell,
  859. .irq = STMPE24XX_IRQ_PWM0,
  860. .block = STMPE_BLOCK_PWM,
  861. },
  862. };
  863. static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
  864. bool enable)
  865. {
  866. unsigned int mask = 0;
  867. if (blocks & STMPE_BLOCK_GPIO)
  868. mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
  869. if (blocks & STMPE_BLOCK_KEYPAD)
  870. mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
  871. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
  872. enable ? mask : 0);
  873. }
  874. static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  875. {
  876. switch (block) {
  877. case STMPE_BLOCK_ROTATOR:
  878. return 2;
  879. case STMPE_BLOCK_KEYPAD:
  880. case STMPE_BLOCK_PWM:
  881. return 1;
  882. case STMPE_BLOCK_GPIO:
  883. default:
  884. return 0;
  885. }
  886. }
  887. static struct stmpe_variant_info stmpe2401 = {
  888. .name = "stmpe2401",
  889. .id_val = 0x0101,
  890. .id_mask = 0xffff,
  891. .num_gpios = 24,
  892. .af_bits = 2,
  893. .regs = stmpe24xx_regs,
  894. .blocks = stmpe24xx_blocks,
  895. .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
  896. .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
  897. .enable = stmpe24xx_enable,
  898. .get_altfunc = stmpe24xx_get_altfunc,
  899. };
  900. static struct stmpe_variant_info stmpe2403 = {
  901. .name = "stmpe2403",
  902. .id_val = 0x0120,
  903. .id_mask = 0xffff,
  904. .num_gpios = 24,
  905. .af_bits = 2,
  906. .regs = stmpe24xx_regs,
  907. .blocks = stmpe24xx_blocks,
  908. .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
  909. .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
  910. .enable = stmpe24xx_enable,
  911. .get_altfunc = stmpe24xx_get_altfunc,
  912. .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
  913. };
  914. static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
  915. [STMPE610] = &stmpe610,
  916. [STMPE801] = &stmpe801,
  917. [STMPE811] = &stmpe811,
  918. [STMPE1600] = &stmpe1600,
  919. [STMPE1601] = &stmpe1601,
  920. [STMPE1801] = &stmpe1801,
  921. [STMPE2401] = &stmpe2401,
  922. [STMPE2403] = &stmpe2403,
  923. };
  924. /*
  925. * These devices can be connected in a 'no-irq' configuration - the irq pin
  926. * is not used and the device cannot interrupt the CPU. Here we only list
  927. * devices which support this configuration - the driver will fail probing
  928. * for any devices not listed here which are configured in this way.
  929. */
  930. static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
  931. [STMPE801] = &stmpe801_noirq,
  932. };
  933. static irqreturn_t stmpe_irq(int irq, void *data)
  934. {
  935. struct stmpe *stmpe = data;
  936. struct stmpe_variant_info *variant = stmpe->variant;
  937. int num = DIV_ROUND_UP(variant->num_irqs, 8);
  938. u8 israddr;
  939. u8 isr[3];
  940. int ret;
  941. int i;
  942. if (variant->id_val == STMPE801_ID ||
  943. variant->id_val == STMPE1600_ID) {
  944. int base = irq_find_mapping(stmpe->domain, 0);
  945. handle_nested_irq(base);
  946. return IRQ_HANDLED;
  947. }
  948. if (variant->id_val == STMPE1801_ID)
  949. israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
  950. else
  951. israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
  952. ret = stmpe_block_read(stmpe, israddr, num, isr);
  953. if (ret < 0)
  954. return IRQ_NONE;
  955. for (i = 0; i < num; i++) {
  956. int bank = num - i - 1;
  957. u8 status = isr[i];
  958. u8 clear;
  959. status &= stmpe->ier[bank];
  960. if (!status)
  961. continue;
  962. clear = status;
  963. while (status) {
  964. int bit = __ffs(status);
  965. int line = bank * 8 + bit;
  966. int nestedirq = irq_find_mapping(stmpe->domain, line);
  967. handle_nested_irq(nestedirq);
  968. status &= ~(1 << bit);
  969. }
  970. stmpe_reg_write(stmpe, israddr + i, clear);
  971. }
  972. return IRQ_HANDLED;
  973. }
  974. static void stmpe_irq_lock(struct irq_data *data)
  975. {
  976. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  977. mutex_lock(&stmpe->irq_lock);
  978. }
  979. static void stmpe_irq_sync_unlock(struct irq_data *data)
  980. {
  981. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  982. struct stmpe_variant_info *variant = stmpe->variant;
  983. int num = DIV_ROUND_UP(variant->num_irqs, 8);
  984. int i;
  985. for (i = 0; i < num; i++) {
  986. u8 new = stmpe->ier[i];
  987. u8 old = stmpe->oldier[i];
  988. if (new == old)
  989. continue;
  990. stmpe->oldier[i] = new;
  991. stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
  992. }
  993. mutex_unlock(&stmpe->irq_lock);
  994. }
  995. static void stmpe_irq_mask(struct irq_data *data)
  996. {
  997. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  998. int offset = data->hwirq;
  999. int regoffset = offset / 8;
  1000. int mask = 1 << (offset % 8);
  1001. stmpe->ier[regoffset] &= ~mask;
  1002. }
  1003. static void stmpe_irq_unmask(struct irq_data *data)
  1004. {
  1005. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  1006. int offset = data->hwirq;
  1007. int regoffset = offset / 8;
  1008. int mask = 1 << (offset % 8);
  1009. stmpe->ier[regoffset] |= mask;
  1010. }
  1011. static struct irq_chip stmpe_irq_chip = {
  1012. .name = "stmpe",
  1013. .irq_bus_lock = stmpe_irq_lock,
  1014. .irq_bus_sync_unlock = stmpe_irq_sync_unlock,
  1015. .irq_mask = stmpe_irq_mask,
  1016. .irq_unmask = stmpe_irq_unmask,
  1017. };
  1018. static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
  1019. irq_hw_number_t hwirq)
  1020. {
  1021. struct stmpe *stmpe = d->host_data;
  1022. struct irq_chip *chip = NULL;
  1023. if (stmpe->variant->id_val != STMPE801_ID)
  1024. chip = &stmpe_irq_chip;
  1025. irq_set_chip_data(virq, stmpe);
  1026. irq_set_chip_and_handler(virq, chip, handle_edge_irq);
  1027. irq_set_nested_thread(virq, 1);
  1028. irq_set_noprobe(virq);
  1029. return 0;
  1030. }
  1031. static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
  1032. {
  1033. irq_set_chip_and_handler(virq, NULL, NULL);
  1034. irq_set_chip_data(virq, NULL);
  1035. }
  1036. static const struct irq_domain_ops stmpe_irq_ops = {
  1037. .map = stmpe_irq_map,
  1038. .unmap = stmpe_irq_unmap,
  1039. .xlate = irq_domain_xlate_twocell,
  1040. };
  1041. static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
  1042. {
  1043. int base = 0;
  1044. int num_irqs = stmpe->variant->num_irqs;
  1045. stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
  1046. &stmpe_irq_ops, stmpe);
  1047. if (!stmpe->domain) {
  1048. dev_err(stmpe->dev, "Failed to create irqdomain\n");
  1049. return -ENOSYS;
  1050. }
  1051. return 0;
  1052. }
  1053. static int stmpe_chip_init(struct stmpe *stmpe)
  1054. {
  1055. unsigned int irq_trigger = stmpe->pdata->irq_trigger;
  1056. int autosleep_timeout = stmpe->pdata->autosleep_timeout;
  1057. struct stmpe_variant_info *variant = stmpe->variant;
  1058. u8 icr = 0;
  1059. unsigned int id;
  1060. u8 data[2];
  1061. int ret;
  1062. ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
  1063. ARRAY_SIZE(data), data);
  1064. if (ret < 0)
  1065. return ret;
  1066. id = (data[0] << 8) | data[1];
  1067. if ((id & variant->id_mask) != variant->id_val) {
  1068. dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
  1069. return -EINVAL;
  1070. }
  1071. dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
  1072. /* Disable all modules -- subdrivers should enable what they need. */
  1073. ret = stmpe_disable(stmpe, ~0);
  1074. if (ret)
  1075. return ret;
  1076. ret = stmpe_reset(stmpe);
  1077. if (ret < 0)
  1078. return ret;
  1079. if (stmpe->irq >= 0) {
  1080. if (id == STMPE801_ID || id == STMPE1600_ID)
  1081. icr = STMPE_SYS_CTRL_INT_EN;
  1082. else
  1083. icr = STMPE_ICR_LSB_GIM;
  1084. /* STMPE801 and STMPE1600 don't support Edge interrupts */
  1085. if (id != STMPE801_ID && id != STMPE1600_ID) {
  1086. if (irq_trigger == IRQF_TRIGGER_FALLING ||
  1087. irq_trigger == IRQF_TRIGGER_RISING)
  1088. icr |= STMPE_ICR_LSB_EDGE;
  1089. }
  1090. if (irq_trigger == IRQF_TRIGGER_RISING ||
  1091. irq_trigger == IRQF_TRIGGER_HIGH) {
  1092. if (id == STMPE801_ID || id == STMPE1600_ID)
  1093. icr |= STMPE_SYS_CTRL_INT_HI;
  1094. else
  1095. icr |= STMPE_ICR_LSB_HIGH;
  1096. }
  1097. }
  1098. if (stmpe->pdata->autosleep) {
  1099. ret = stmpe_autosleep(stmpe, autosleep_timeout);
  1100. if (ret)
  1101. return ret;
  1102. }
  1103. return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
  1104. }
  1105. static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
  1106. {
  1107. return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
  1108. NULL, 0, stmpe->domain);
  1109. }
  1110. static int stmpe_devices_init(struct stmpe *stmpe)
  1111. {
  1112. struct stmpe_variant_info *variant = stmpe->variant;
  1113. unsigned int platform_blocks = stmpe->pdata->blocks;
  1114. int ret = -EINVAL;
  1115. int i, j;
  1116. for (i = 0; i < variant->num_blocks; i++) {
  1117. struct stmpe_variant_block *block = &variant->blocks[i];
  1118. if (!(platform_blocks & block->block))
  1119. continue;
  1120. for (j = 0; j < block->cell->num_resources; j++) {
  1121. struct resource *res =
  1122. (struct resource *) &block->cell->resources[j];
  1123. /* Dynamically fill in a variant's IRQ. */
  1124. if (res->flags & IORESOURCE_IRQ)
  1125. res->start = res->end = block->irq + j;
  1126. }
  1127. platform_blocks &= ~block->block;
  1128. ret = stmpe_add_device(stmpe, block->cell);
  1129. if (ret)
  1130. return ret;
  1131. }
  1132. if (platform_blocks)
  1133. dev_warn(stmpe->dev,
  1134. "platform wants blocks (%#x) not present on variant",
  1135. platform_blocks);
  1136. return ret;
  1137. }
  1138. static void stmpe_of_probe(struct stmpe_platform_data *pdata,
  1139. struct device_node *np)
  1140. {
  1141. struct device_node *child;
  1142. pdata->id = of_alias_get_id(np, "stmpe-i2c");
  1143. if (pdata->id < 0)
  1144. pdata->id = -1;
  1145. pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0,
  1146. &pdata->irq_trigger);
  1147. if (gpio_is_valid(pdata->irq_gpio))
  1148. pdata->irq_over_gpio = 1;
  1149. else
  1150. pdata->irq_trigger = IRQF_TRIGGER_NONE;
  1151. of_property_read_u32(np, "st,autosleep-timeout",
  1152. &pdata->autosleep_timeout);
  1153. pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
  1154. for_each_child_of_node(np, child) {
  1155. if (of_node_name_eq(child, "stmpe_gpio")) {
  1156. pdata->blocks |= STMPE_BLOCK_GPIO;
  1157. } else if (of_node_name_eq(child, "stmpe_keypad")) {
  1158. pdata->blocks |= STMPE_BLOCK_KEYPAD;
  1159. } else if (of_node_name_eq(child, "stmpe_touchscreen")) {
  1160. pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
  1161. } else if (of_node_name_eq(child, "stmpe_adc")) {
  1162. pdata->blocks |= STMPE_BLOCK_ADC;
  1163. } else if (of_node_name_eq(child, "stmpe_pwm")) {
  1164. pdata->blocks |= STMPE_BLOCK_PWM;
  1165. } else if (of_node_name_eq(child, "stmpe_rotator")) {
  1166. pdata->blocks |= STMPE_BLOCK_ROTATOR;
  1167. }
  1168. }
  1169. }
  1170. /* Called from client specific probe routines */
  1171. int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
  1172. {
  1173. struct stmpe_platform_data *pdata;
  1174. struct device_node *np = ci->dev->of_node;
  1175. struct stmpe *stmpe;
  1176. int ret;
  1177. u32 val;
  1178. pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
  1179. if (!pdata)
  1180. return -ENOMEM;
  1181. stmpe_of_probe(pdata, np);
  1182. if (of_find_property(np, "interrupts", NULL) == NULL)
  1183. ci->irq = -1;
  1184. stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
  1185. if (!stmpe)
  1186. return -ENOMEM;
  1187. mutex_init(&stmpe->irq_lock);
  1188. mutex_init(&stmpe->lock);
  1189. if (!of_property_read_u32(np, "st,sample-time", &val))
  1190. stmpe->sample_time = val;
  1191. if (!of_property_read_u32(np, "st,mod-12b", &val))
  1192. stmpe->mod_12b = val;
  1193. if (!of_property_read_u32(np, "st,ref-sel", &val))
  1194. stmpe->ref_sel = val;
  1195. if (!of_property_read_u32(np, "st,adc-freq", &val))
  1196. stmpe->adc_freq = val;
  1197. stmpe->dev = ci->dev;
  1198. stmpe->client = ci->client;
  1199. stmpe->pdata = pdata;
  1200. stmpe->ci = ci;
  1201. stmpe->partnum = partnum;
  1202. stmpe->variant = stmpe_variant_info[partnum];
  1203. stmpe->regs = stmpe->variant->regs;
  1204. stmpe->num_gpios = stmpe->variant->num_gpios;
  1205. stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
  1206. if (!IS_ERR(stmpe->vcc)) {
  1207. ret = regulator_enable(stmpe->vcc);
  1208. if (ret)
  1209. dev_warn(ci->dev, "failed to enable VCC supply\n");
  1210. }
  1211. stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
  1212. if (!IS_ERR(stmpe->vio)) {
  1213. ret = regulator_enable(stmpe->vio);
  1214. if (ret)
  1215. dev_warn(ci->dev, "failed to enable VIO supply\n");
  1216. }
  1217. dev_set_drvdata(stmpe->dev, stmpe);
  1218. if (ci->init)
  1219. ci->init(stmpe);
  1220. if (pdata->irq_over_gpio) {
  1221. ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio,
  1222. GPIOF_DIR_IN, "stmpe");
  1223. if (ret) {
  1224. dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
  1225. ret);
  1226. return ret;
  1227. }
  1228. stmpe->irq = gpio_to_irq(pdata->irq_gpio);
  1229. } else {
  1230. stmpe->irq = ci->irq;
  1231. }
  1232. if (stmpe->irq < 0) {
  1233. /* use alternate variant info for no-irq mode, if supported */
  1234. dev_info(stmpe->dev,
  1235. "%s configured in no-irq mode by platform data\n",
  1236. stmpe->variant->name);
  1237. if (!stmpe_noirq_variant_info[stmpe->partnum]) {
  1238. dev_err(stmpe->dev,
  1239. "%s does not support no-irq mode!\n",
  1240. stmpe->variant->name);
  1241. return -ENODEV;
  1242. }
  1243. stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
  1244. } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
  1245. pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
  1246. }
  1247. ret = stmpe_chip_init(stmpe);
  1248. if (ret)
  1249. return ret;
  1250. if (stmpe->irq >= 0) {
  1251. ret = stmpe_irq_init(stmpe, np);
  1252. if (ret)
  1253. return ret;
  1254. ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
  1255. stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
  1256. "stmpe", stmpe);
  1257. if (ret) {
  1258. dev_err(stmpe->dev, "failed to request IRQ: %d\n",
  1259. ret);
  1260. return ret;
  1261. }
  1262. }
  1263. ret = stmpe_devices_init(stmpe);
  1264. if (!ret)
  1265. return 0;
  1266. dev_err(stmpe->dev, "failed to add children\n");
  1267. mfd_remove_devices(stmpe->dev);
  1268. return ret;
  1269. }
  1270. int stmpe_remove(struct stmpe *stmpe)
  1271. {
  1272. if (!IS_ERR(stmpe->vio))
  1273. regulator_disable(stmpe->vio);
  1274. if (!IS_ERR(stmpe->vcc))
  1275. regulator_disable(stmpe->vcc);
  1276. __stmpe_disable(stmpe, STMPE_BLOCK_ADC);
  1277. mfd_remove_devices(stmpe->dev);
  1278. return 0;
  1279. }
  1280. #ifdef CONFIG_PM
  1281. static int stmpe_suspend(struct device *dev)
  1282. {
  1283. struct stmpe *stmpe = dev_get_drvdata(dev);
  1284. if (stmpe->irq >= 0 && device_may_wakeup(dev))
  1285. enable_irq_wake(stmpe->irq);
  1286. return 0;
  1287. }
  1288. static int stmpe_resume(struct device *dev)
  1289. {
  1290. struct stmpe *stmpe = dev_get_drvdata(dev);
  1291. if (stmpe->irq >= 0 && device_may_wakeup(dev))
  1292. disable_irq_wake(stmpe->irq);
  1293. return 0;
  1294. }
  1295. const struct dev_pm_ops stmpe_dev_pm_ops = {
  1296. .suspend = stmpe_suspend,
  1297. .resume = stmpe_resume,
  1298. };
  1299. #endif