stm32-timers.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2016
  4. * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/mfd/stm32-timers.h>
  8. #include <linux/module.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/reset.h>
  11. #define STM32_TIMERS_MAX_REGISTERS 0x3fc
  12. /* DIER register DMA enable bits */
  13. static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
  14. TIM_DIER_CC1DE,
  15. TIM_DIER_CC2DE,
  16. TIM_DIER_CC3DE,
  17. TIM_DIER_CC4DE,
  18. TIM_DIER_UIE,
  19. TIM_DIER_TDE,
  20. TIM_DIER_COMDE
  21. };
  22. static void stm32_timers_dma_done(void *p)
  23. {
  24. struct stm32_timers_dma *dma = p;
  25. struct dma_tx_state state;
  26. enum dma_status status;
  27. status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
  28. if (status == DMA_COMPLETE)
  29. complete(&dma->completion);
  30. }
  31. /**
  32. * stm32_timers_dma_burst_read - Read from timers registers using DMA.
  33. *
  34. * Read from STM32 timers registers using DMA on a single event.
  35. * @dev: reference to stm32_timers MFD device
  36. * @buf: DMA'able destination buffer
  37. * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
  38. * @reg: registers start offset for DMA to read from (like CCRx for capture)
  39. * @num_reg: number of registers to read upon each DMA request, starting @reg.
  40. * @bursts: number of bursts to read (e.g. like two for pwm period capture)
  41. * @tmo_ms: timeout (milliseconds)
  42. */
  43. int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
  44. enum stm32_timers_dmas id, u32 reg,
  45. unsigned int num_reg, unsigned int bursts,
  46. unsigned long tmo_ms)
  47. {
  48. struct stm32_timers *ddata = dev_get_drvdata(dev);
  49. unsigned long timeout = msecs_to_jiffies(tmo_ms);
  50. struct regmap *regmap = ddata->regmap;
  51. struct stm32_timers_dma *dma = &ddata->dma;
  52. size_t len = num_reg * bursts * sizeof(u32);
  53. struct dma_async_tx_descriptor *desc;
  54. struct dma_slave_config config;
  55. dma_cookie_t cookie;
  56. dma_addr_t dma_buf;
  57. u32 dbl, dba;
  58. long err;
  59. int ret;
  60. /* Sanity check */
  61. if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
  62. return -EINVAL;
  63. if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
  64. (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
  65. return -EINVAL;
  66. if (!dma->chans[id])
  67. return -ENODEV;
  68. mutex_lock(&dma->lock);
  69. /* Select DMA channel in use */
  70. dma->chan = dma->chans[id];
  71. dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
  72. if (dma_mapping_error(dev, dma_buf)) {
  73. ret = -ENOMEM;
  74. goto unlock;
  75. }
  76. /* Prepare DMA read from timer registers, using DMA burst mode */
  77. memset(&config, 0, sizeof(config));
  78. config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
  79. config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  80. ret = dmaengine_slave_config(dma->chan, &config);
  81. if (ret)
  82. goto unmap;
  83. desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
  84. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  85. if (!desc) {
  86. ret = -EBUSY;
  87. goto unmap;
  88. }
  89. desc->callback = stm32_timers_dma_done;
  90. desc->callback_param = dma;
  91. cookie = dmaengine_submit(desc);
  92. ret = dma_submit_error(cookie);
  93. if (ret)
  94. goto dma_term;
  95. reinit_completion(&dma->completion);
  96. dma_async_issue_pending(dma->chan);
  97. /* Setup and enable timer DMA burst mode */
  98. dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
  99. dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
  100. ret = regmap_write(regmap, TIM_DCR, dbl | dba);
  101. if (ret)
  102. goto dma_term;
  103. /* Clear pending flags before enabling DMA request */
  104. ret = regmap_write(regmap, TIM_SR, 0);
  105. if (ret)
  106. goto dcr_clr;
  107. ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
  108. stm32_timers_dier_dmaen[id]);
  109. if (ret)
  110. goto dcr_clr;
  111. err = wait_for_completion_interruptible_timeout(&dma->completion,
  112. timeout);
  113. if (err == 0)
  114. ret = -ETIMEDOUT;
  115. else if (err < 0)
  116. ret = err;
  117. regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
  118. regmap_write(regmap, TIM_SR, 0);
  119. dcr_clr:
  120. regmap_write(regmap, TIM_DCR, 0);
  121. dma_term:
  122. dmaengine_terminate_all(dma->chan);
  123. unmap:
  124. dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
  125. unlock:
  126. dma->chan = NULL;
  127. mutex_unlock(&dma->lock);
  128. return ret;
  129. }
  130. EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
  131. static const struct regmap_config stm32_timers_regmap_cfg = {
  132. .reg_bits = 32,
  133. .val_bits = 32,
  134. .reg_stride = sizeof(u32),
  135. .max_register = STM32_TIMERS_MAX_REGISTERS,
  136. };
  137. static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
  138. {
  139. u32 arr;
  140. /* Backup ARR to restore it after getting the maximum value */
  141. regmap_read(ddata->regmap, TIM_ARR, &arr);
  142. /*
  143. * Only the available bits will be written so when readback
  144. * we get the maximum value of auto reload register
  145. */
  146. regmap_write(ddata->regmap, TIM_ARR, ~0L);
  147. regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
  148. regmap_write(ddata->regmap, TIM_ARR, arr);
  149. }
  150. static int stm32_timers_dma_probe(struct device *dev,
  151. struct stm32_timers *ddata)
  152. {
  153. int i;
  154. int ret = 0;
  155. char name[4];
  156. init_completion(&ddata->dma.completion);
  157. mutex_init(&ddata->dma.lock);
  158. /* Optional DMA support: get valid DMA channel(s) or NULL */
  159. for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
  160. snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
  161. ddata->dma.chans[i] = dma_request_chan(dev, name);
  162. }
  163. ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
  164. ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
  165. ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
  166. for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
  167. if (IS_ERR(ddata->dma.chans[i])) {
  168. /* Save the first error code to return */
  169. if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
  170. ret = PTR_ERR(ddata->dma.chans[i]);
  171. ddata->dma.chans[i] = NULL;
  172. }
  173. }
  174. return ret;
  175. }
  176. static void stm32_timers_dma_remove(struct device *dev,
  177. struct stm32_timers *ddata)
  178. {
  179. int i;
  180. for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
  181. if (ddata->dma.chans[i])
  182. dma_release_channel(ddata->dma.chans[i]);
  183. }
  184. static int stm32_timers_probe(struct platform_device *pdev)
  185. {
  186. struct device *dev = &pdev->dev;
  187. struct stm32_timers *ddata;
  188. struct resource *res;
  189. void __iomem *mmio;
  190. int ret;
  191. ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
  192. if (!ddata)
  193. return -ENOMEM;
  194. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  195. mmio = devm_ioremap_resource(dev, res);
  196. if (IS_ERR(mmio))
  197. return PTR_ERR(mmio);
  198. /* Timer physical addr for DMA */
  199. ddata->dma.phys_base = res->start;
  200. ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
  201. &stm32_timers_regmap_cfg);
  202. if (IS_ERR(ddata->regmap))
  203. return PTR_ERR(ddata->regmap);
  204. ddata->clk = devm_clk_get(dev, NULL);
  205. if (IS_ERR(ddata->clk))
  206. return PTR_ERR(ddata->clk);
  207. stm32_timers_get_arr_size(ddata);
  208. ret = stm32_timers_dma_probe(dev, ddata);
  209. if (ret) {
  210. stm32_timers_dma_remove(dev, ddata);
  211. return ret;
  212. }
  213. platform_set_drvdata(pdev, ddata);
  214. ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  215. if (ret)
  216. stm32_timers_dma_remove(dev, ddata);
  217. return ret;
  218. }
  219. static int stm32_timers_remove(struct platform_device *pdev)
  220. {
  221. struct stm32_timers *ddata = platform_get_drvdata(pdev);
  222. /*
  223. * Don't use devm_ here: enfore of_platform_depopulate() happens before
  224. * DMA are released, to avoid race on DMA.
  225. */
  226. of_platform_depopulate(&pdev->dev);
  227. stm32_timers_dma_remove(&pdev->dev, ddata);
  228. return 0;
  229. }
  230. static const struct of_device_id stm32_timers_of_match[] = {
  231. { .compatible = "st,stm32-timers", },
  232. { /* end node */ },
  233. };
  234. MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
  235. static struct platform_driver stm32_timers_driver = {
  236. .probe = stm32_timers_probe,
  237. .remove = stm32_timers_remove,
  238. .driver = {
  239. .name = "stm32-timers",
  240. .of_match_table = stm32_timers_of_match,
  241. },
  242. };
  243. module_platform_driver(stm32_timers_driver);
  244. MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
  245. MODULE_LICENSE("GPL v2");