rc5t583.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Core driver access RC5T583 power management chip.
  4. *
  5. * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
  6. * Author: Laxman dewangan <ldewangan@nvidia.com>
  7. *
  8. * Based on code
  9. * Copyright (C) 2011 RICOH COMPANY,LTD
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/i2c.h>
  18. #include <linux/mfd/core.h>
  19. #include <linux/mfd/rc5t583.h>
  20. #include <linux/regmap.h>
  21. #define RICOH_ONOFFSEL_REG 0x10
  22. #define RICOH_SWCTL_REG 0x5E
  23. struct deepsleep_control_data {
  24. u8 reg_add;
  25. u8 ds_pos_bit;
  26. };
  27. #define DEEPSLEEP_INIT(_id, _reg, _pos) \
  28. { \
  29. .reg_add = RC5T583_##_reg, \
  30. .ds_pos_bit = _pos, \
  31. }
  32. static struct deepsleep_control_data deepsleep_data[] = {
  33. DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
  34. DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
  35. DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
  36. DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
  37. DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
  38. DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
  39. DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
  40. DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
  41. DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
  42. DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
  43. DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
  44. DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
  45. DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
  46. DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
  47. DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
  48. DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
  49. DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
  50. DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
  51. DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
  52. DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
  53. DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
  54. DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
  55. };
  56. #define EXT_PWR_REQ \
  57. (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
  58. static const struct mfd_cell rc5t583_subdevs[] = {
  59. {.name = "rc5t583-gpio",},
  60. {.name = "rc5t583-regulator",},
  61. {.name = "rc5t583-rtc", },
  62. {.name = "rc5t583-key", }
  63. };
  64. static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
  65. int id, int ext_pwr, int slots)
  66. {
  67. int ret;
  68. uint8_t sleepseq_val = 0;
  69. unsigned int en_bit;
  70. unsigned int slot_bit;
  71. if (id == RC5T583_DS_DC0) {
  72. dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
  73. return -EINVAL;
  74. }
  75. en_bit = deepsleep_data[id].ds_pos_bit;
  76. slot_bit = en_bit + 1;
  77. ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
  78. if (ret < 0) {
  79. dev_err(dev, "Error in reading reg 0x%x\n",
  80. deepsleep_data[id].reg_add);
  81. return ret;
  82. }
  83. sleepseq_val &= ~(0xF << en_bit);
  84. sleepseq_val |= BIT(en_bit);
  85. sleepseq_val |= ((slots & 0x7) << slot_bit);
  86. ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
  87. if (ret < 0) {
  88. dev_err(dev, "Error in updating the 0x%02x register\n",
  89. RICOH_ONOFFSEL_REG);
  90. return ret;
  91. }
  92. ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
  93. if (ret < 0) {
  94. dev_err(dev, "Error in writing reg 0x%x\n",
  95. deepsleep_data[id].reg_add);
  96. return ret;
  97. }
  98. if (id == RC5T583_DS_LDO4) {
  99. ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
  100. if (ret < 0)
  101. dev_err(dev, "Error in writing reg 0x%x\n",
  102. RICOH_SWCTL_REG);
  103. }
  104. return ret;
  105. }
  106. static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
  107. int id, int ext_pwr)
  108. {
  109. int ret;
  110. if (id != RC5T583_DS_DC0) {
  111. dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
  112. return -EINVAL;
  113. }
  114. ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
  115. if (ret < 0)
  116. dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
  117. return ret;
  118. }
  119. int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
  120. int ext_pwr_req, int deepsleep_slot_nr)
  121. {
  122. if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
  123. return -EINVAL;
  124. if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
  125. return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
  126. ext_pwr_req, deepsleep_slot_nr);
  127. if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
  128. return __rc5t583_set_ext_pwrreq2_control(dev,
  129. ds_id, ext_pwr_req);
  130. return 0;
  131. }
  132. EXPORT_SYMBOL(rc5t583_ext_power_req_config);
  133. static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
  134. struct rc5t583_platform_data *pdata)
  135. {
  136. int ret;
  137. int i;
  138. uint8_t on_off_val = 0;
  139. /* Clear ONOFFSEL register */
  140. if (pdata->enable_shutdown)
  141. on_off_val = 0x1;
  142. ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
  143. if (ret < 0)
  144. dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
  145. RICOH_ONOFFSEL_REG, ret);
  146. ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
  147. if (ret < 0)
  148. dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
  149. RICOH_SWCTL_REG, ret);
  150. /* Clear sleep sequence register */
  151. for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
  152. ret = rc5t583_write(rc5t583->dev, i, 0x0);
  153. if (ret < 0)
  154. dev_warn(rc5t583->dev,
  155. "Error in writing reg 0x%02x error: %d\n",
  156. i, ret);
  157. }
  158. return 0;
  159. }
  160. static bool volatile_reg(struct device *dev, unsigned int reg)
  161. {
  162. /* Enable caching in interrupt registers */
  163. switch (reg) {
  164. case RC5T583_INT_EN_SYS1:
  165. case RC5T583_INT_EN_SYS2:
  166. case RC5T583_INT_EN_DCDC:
  167. case RC5T583_INT_EN_RTC:
  168. case RC5T583_INT_EN_ADC1:
  169. case RC5T583_INT_EN_ADC2:
  170. case RC5T583_INT_EN_ADC3:
  171. case RC5T583_GPIO_GPEDGE1:
  172. case RC5T583_GPIO_GPEDGE2:
  173. case RC5T583_GPIO_EN_INT:
  174. return false;
  175. case RC5T583_GPIO_MON_IOIN:
  176. /* This is gpio input register */
  177. return true;
  178. default:
  179. /* Enable caching in gpio registers */
  180. if ((reg >= RC5T583_GPIO_IOSEL) &&
  181. (reg <= RC5T583_GPIO_GPOFUNC))
  182. return false;
  183. /* Enable caching in sleep seq registers */
  184. if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
  185. return false;
  186. /* Enable caching of regulator registers */
  187. if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
  188. return false;
  189. if ((reg >= RC5T583_REG_LDOEN1) &&
  190. (reg <= RC5T583_REG_LDO9DAC_DS))
  191. return false;
  192. break;
  193. }
  194. return true;
  195. }
  196. static const struct regmap_config rc5t583_regmap_config = {
  197. .reg_bits = 8,
  198. .val_bits = 8,
  199. .volatile_reg = volatile_reg,
  200. .max_register = RC5T583_MAX_REG,
  201. .num_reg_defaults_raw = RC5T583_NUM_REGS,
  202. .cache_type = REGCACHE_RBTREE,
  203. };
  204. static int rc5t583_i2c_probe(struct i2c_client *i2c,
  205. const struct i2c_device_id *id)
  206. {
  207. struct rc5t583 *rc5t583;
  208. struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
  209. int ret;
  210. if (!pdata) {
  211. dev_err(&i2c->dev, "Err: Platform data not found\n");
  212. return -EINVAL;
  213. }
  214. rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
  215. if (!rc5t583)
  216. return -ENOMEM;
  217. rc5t583->dev = &i2c->dev;
  218. i2c_set_clientdata(i2c, rc5t583);
  219. rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
  220. if (IS_ERR(rc5t583->regmap)) {
  221. ret = PTR_ERR(rc5t583->regmap);
  222. dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
  223. return ret;
  224. }
  225. ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
  226. if (ret < 0)
  227. return ret;
  228. if (i2c->irq) {
  229. ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
  230. /* Still continue with warning, if irq init fails */
  231. if (ret)
  232. dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
  233. }
  234. ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
  235. ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
  236. if (ret) {
  237. dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
  238. return ret;
  239. }
  240. return 0;
  241. }
  242. static const struct i2c_device_id rc5t583_i2c_id[] = {
  243. {.name = "rc5t583", .driver_data = 0},
  244. {}
  245. };
  246. static struct i2c_driver rc5t583_i2c_driver = {
  247. .driver = {
  248. .name = "rc5t583",
  249. },
  250. .probe = rc5t583_i2c_probe,
  251. .id_table = rc5t583_i2c_id,
  252. };
  253. static int __init rc5t583_i2c_init(void)
  254. {
  255. return i2c_add_driver(&rc5t583_i2c_driver);
  256. }
  257. subsys_initcall(rc5t583_i2c_init);