mt6360-core.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 MediaTek Inc.
  4. *
  5. * Author: Gene Chen <gene_chen@richtek.com>
  6. */
  7. #include <linux/i2c.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mfd/core.h>
  12. #include <linux/module.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/mfd/mt6360.h>
  16. /* reg 0 -> 0 ~ 7 */
  17. #define MT6360_CHG_TREG_EVT (4)
  18. #define MT6360_CHG_AICR_EVT (5)
  19. #define MT6360_CHG_MIVR_EVT (6)
  20. #define MT6360_PWR_RDY_EVT (7)
  21. /* REG 1 -> 8 ~ 15 */
  22. #define MT6360_CHG_BATSYSUV_EVT (9)
  23. #define MT6360_FLED_CHG_VINOVP_EVT (11)
  24. #define MT6360_CHG_VSYSUV_EVT (12)
  25. #define MT6360_CHG_VSYSOV_EVT (13)
  26. #define MT6360_CHG_VBATOV_EVT (14)
  27. #define MT6360_CHG_VBUSOV_EVT (15)
  28. /* REG 2 -> 16 ~ 23 */
  29. /* REG 3 -> 24 ~ 31 */
  30. #define MT6360_WD_PMU_DET (25)
  31. #define MT6360_WD_PMU_DONE (26)
  32. #define MT6360_CHG_TMRI (27)
  33. #define MT6360_CHG_ADPBADI (29)
  34. #define MT6360_CHG_RVPI (30)
  35. #define MT6360_OTPI (31)
  36. /* REG 4 -> 32 ~ 39 */
  37. #define MT6360_CHG_AICCMEASL (32)
  38. #define MT6360_CHGDET_DONEI (34)
  39. #define MT6360_WDTMRI (35)
  40. #define MT6360_SSFINISHI (36)
  41. #define MT6360_CHG_RECHGI (37)
  42. #define MT6360_CHG_TERMI (38)
  43. #define MT6360_CHG_IEOCI (39)
  44. /* REG 5 -> 40 ~ 47 */
  45. #define MT6360_PUMPX_DONEI (40)
  46. #define MT6360_BAT_OVP_ADC_EVT (41)
  47. #define MT6360_TYPEC_OTP_EVT (42)
  48. #define MT6360_ADC_WAKEUP_EVT (43)
  49. #define MT6360_ADC_DONEI (44)
  50. #define MT6360_BST_BATUVI (45)
  51. #define MT6360_BST_VBUSOVI (46)
  52. #define MT6360_BST_OLPI (47)
  53. /* REG 6 -> 48 ~ 55 */
  54. #define MT6360_ATTACH_I (48)
  55. #define MT6360_DETACH_I (49)
  56. #define MT6360_QC30_STPDONE (51)
  57. #define MT6360_QC_VBUSDET_DONE (52)
  58. #define MT6360_HVDCP_DET (53)
  59. #define MT6360_CHGDETI (54)
  60. #define MT6360_DCDTI (55)
  61. /* REG 7 -> 56 ~ 63 */
  62. #define MT6360_FOD_DONE_EVT (56)
  63. #define MT6360_FOD_OV_EVT (57)
  64. #define MT6360_CHRDET_UVP_EVT (58)
  65. #define MT6360_CHRDET_OVP_EVT (59)
  66. #define MT6360_CHRDET_EXT_EVT (60)
  67. #define MT6360_FOD_LR_EVT (61)
  68. #define MT6360_FOD_HR_EVT (62)
  69. #define MT6360_FOD_DISCHG_FAIL_EVT (63)
  70. /* REG 8 -> 64 ~ 71 */
  71. #define MT6360_USBID_EVT (64)
  72. #define MT6360_APWDTRST_EVT (65)
  73. #define MT6360_EN_EVT (66)
  74. #define MT6360_QONB_RST_EVT (67)
  75. #define MT6360_MRSTB_EVT (68)
  76. #define MT6360_OTP_EVT (69)
  77. #define MT6360_VDDAOV_EVT (70)
  78. #define MT6360_SYSUV_EVT (71)
  79. /* REG 9 -> 72 ~ 79 */
  80. #define MT6360_FLED_STRBPIN_EVT (72)
  81. #define MT6360_FLED_TORPIN_EVT (73)
  82. #define MT6360_FLED_TX_EVT (74)
  83. #define MT6360_FLED_LVF_EVT (75)
  84. #define MT6360_FLED2_SHORT_EVT (78)
  85. #define MT6360_FLED1_SHORT_EVT (79)
  86. /* REG 10 -> 80 ~ 87 */
  87. #define MT6360_FLED2_STRB_EVT (80)
  88. #define MT6360_FLED1_STRB_EVT (81)
  89. #define MT6360_FLED2_STRB_TO_EVT (82)
  90. #define MT6360_FLED1_STRB_TO_EVT (83)
  91. #define MT6360_FLED2_TOR_EVT (84)
  92. #define MT6360_FLED1_TOR_EVT (85)
  93. /* REG 11 -> 88 ~ 95 */
  94. /* REG 12 -> 96 ~ 103 */
  95. #define MT6360_BUCK1_PGB_EVT (96)
  96. #define MT6360_BUCK1_OC_EVT (100)
  97. #define MT6360_BUCK1_OV_EVT (101)
  98. #define MT6360_BUCK1_UV_EVT (102)
  99. /* REG 13 -> 104 ~ 111 */
  100. #define MT6360_BUCK2_PGB_EVT (104)
  101. #define MT6360_BUCK2_OC_EVT (108)
  102. #define MT6360_BUCK2_OV_EVT (109)
  103. #define MT6360_BUCK2_UV_EVT (110)
  104. /* REG 14 -> 112 ~ 119 */
  105. #define MT6360_LDO1_OC_EVT (113)
  106. #define MT6360_LDO2_OC_EVT (114)
  107. #define MT6360_LDO3_OC_EVT (115)
  108. #define MT6360_LDO5_OC_EVT (117)
  109. #define MT6360_LDO6_OC_EVT (118)
  110. #define MT6360_LDO7_OC_EVT (119)
  111. /* REG 15 -> 120 ~ 127 */
  112. #define MT6360_LDO1_PGB_EVT (121)
  113. #define MT6360_LDO2_PGB_EVT (122)
  114. #define MT6360_LDO3_PGB_EVT (123)
  115. #define MT6360_LDO5_PGB_EVT (125)
  116. #define MT6360_LDO6_PGB_EVT (126)
  117. #define MT6360_LDO7_PGB_EVT (127)
  118. static const struct regmap_irq mt6360_pmu_irqs[] = {
  119. REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8),
  120. REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8),
  121. REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8),
  122. REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8),
  123. REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8),
  124. REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8),
  125. REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8),
  126. REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8),
  127. REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8),
  128. REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8),
  129. REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8),
  130. REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8),
  131. REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8),
  132. REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8),
  133. REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8),
  134. REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8),
  135. REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8),
  136. REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8),
  137. REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8),
  138. REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8),
  139. REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8),
  140. REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8),
  141. REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8),
  142. REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8),
  143. REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8),
  144. REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8),
  145. REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8),
  146. REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8),
  147. REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8),
  148. REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8),
  149. REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8),
  150. REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8),
  151. REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8),
  152. REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8),
  153. REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8),
  154. REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8),
  155. REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8),
  156. REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8),
  157. REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8),
  158. REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8),
  159. REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8),
  160. REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8),
  161. REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8),
  162. REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8),
  163. REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8),
  164. REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8),
  165. REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8),
  166. REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8),
  167. REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8),
  168. REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8),
  169. REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8),
  170. REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8),
  171. REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8),
  172. REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8),
  173. REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8),
  174. REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8),
  175. REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8),
  176. REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8),
  177. REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8),
  178. REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8),
  179. REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8),
  180. REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8),
  181. REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8),
  182. REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8),
  183. REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8),
  184. REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8),
  185. REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8),
  186. REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8),
  187. REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8),
  188. REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8),
  189. REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8),
  190. REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8),
  191. REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8),
  192. REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8),
  193. REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8),
  194. REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8),
  195. REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8),
  196. REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8),
  197. REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8),
  198. REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8),
  199. REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8),
  200. REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8),
  201. REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8),
  202. REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8),
  203. REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8),
  204. REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8),
  205. };
  206. static int mt6360_pmu_handle_post_irq(void *irq_drv_data)
  207. {
  208. struct mt6360_pmu_data *mpd = irq_drv_data;
  209. return regmap_update_bits(mpd->regmap,
  210. MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG);
  211. }
  212. static struct regmap_irq_chip mt6360_pmu_irq_chip = {
  213. .irqs = mt6360_pmu_irqs,
  214. .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs),
  215. .num_regs = MT6360_PMU_IRQ_REGNUM,
  216. .mask_base = MT6360_PMU_CHG_MASK1,
  217. .status_base = MT6360_PMU_CHG_IRQ1,
  218. .ack_base = MT6360_PMU_CHG_IRQ1,
  219. .init_ack_masked = true,
  220. .use_ack = true,
  221. .handle_post_irq = mt6360_pmu_handle_post_irq,
  222. };
  223. static const struct regmap_config mt6360_pmu_regmap_config = {
  224. .reg_bits = 8,
  225. .val_bits = 8,
  226. .max_register = MT6360_PMU_MAXREG,
  227. };
  228. static const struct resource mt6360_adc_resources[] = {
  229. DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"),
  230. };
  231. static const struct resource mt6360_chg_resources[] = {
  232. DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"),
  233. DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"),
  234. DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"),
  235. DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"),
  236. DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"),
  237. DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"),
  238. DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"),
  239. DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"),
  240. DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"),
  241. DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"),
  242. DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"),
  243. DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"),
  244. DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"),
  245. DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"),
  246. DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"),
  247. };
  248. static const struct resource mt6360_led_resources[] = {
  249. DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"),
  250. DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"),
  251. DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"),
  252. DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"),
  253. DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"),
  254. DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"),
  255. };
  256. static const struct resource mt6360_pmic_resources[] = {
  257. DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"),
  258. DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"),
  259. DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"),
  260. DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"),
  261. DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"),
  262. DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"),
  263. DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"),
  264. DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"),
  265. DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"),
  266. DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),
  267. DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),
  268. DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),
  269. };
  270. static const struct resource mt6360_ldo_resources[] = {
  271. DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"),
  272. DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"),
  273. DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"),
  274. DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"),
  275. DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"),
  276. DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"),
  277. DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"),
  278. DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"),
  279. };
  280. static const struct mfd_cell mt6360_devs[] = {
  281. OF_MFD_CELL("mt6360_adc", mt6360_adc_resources,
  282. NULL, 0, 0, "mediatek,mt6360_adc"),
  283. OF_MFD_CELL("mt6360_chg", mt6360_chg_resources,
  284. NULL, 0, 0, "mediatek,mt6360_chg"),
  285. OF_MFD_CELL("mt6360_led", mt6360_led_resources,
  286. NULL, 0, 0, "mediatek,mt6360_led"),
  287. OF_MFD_CELL("mt6360_pmic", mt6360_pmic_resources,
  288. NULL, 0, 0, "mediatek,mt6360_pmic"),
  289. OF_MFD_CELL("mt6360_ldo", mt6360_ldo_resources,
  290. NULL, 0, 0, "mediatek,mt6360_ldo"),
  291. OF_MFD_CELL("mt6360_tcpc", NULL,
  292. NULL, 0, 0, "mediatek,mt6360_tcpc"),
  293. };
  294. static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = {
  295. MT6360_PMU_SLAVEID,
  296. MT6360_PMIC_SLAVEID,
  297. MT6360_LDO_SLAVEID,
  298. MT6360_TCPC_SLAVEID,
  299. };
  300. static int mt6360_pmu_probe(struct i2c_client *client)
  301. {
  302. struct mt6360_pmu_data *mpd;
  303. unsigned int reg_data;
  304. int i, ret;
  305. mpd = devm_kzalloc(&client->dev, sizeof(*mpd), GFP_KERNEL);
  306. if (!mpd)
  307. return -ENOMEM;
  308. mpd->dev = &client->dev;
  309. i2c_set_clientdata(client, mpd);
  310. mpd->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config);
  311. if (IS_ERR(mpd->regmap)) {
  312. dev_err(&client->dev, "Failed to register regmap\n");
  313. return PTR_ERR(mpd->regmap);
  314. }
  315. ret = regmap_read(mpd->regmap, MT6360_PMU_DEV_INFO, &reg_data);
  316. if (ret) {
  317. dev_err(&client->dev, "Device not found\n");
  318. return ret;
  319. }
  320. mpd->chip_rev = reg_data & CHIP_REV_MASK;
  321. if (mpd->chip_rev != CHIP_VEN_MT6360) {
  322. dev_err(&client->dev, "Device not supported\n");
  323. return -ENODEV;
  324. }
  325. mt6360_pmu_irq_chip.irq_drv_data = mpd;
  326. ret = devm_regmap_add_irq_chip(&client->dev, mpd->regmap, client->irq,
  327. IRQF_TRIGGER_FALLING, 0,
  328. &mt6360_pmu_irq_chip, &mpd->irq_data);
  329. if (ret) {
  330. dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n");
  331. return ret;
  332. }
  333. mpd->i2c[0] = client;
  334. for (i = 1; i < MT6360_SLAVE_MAX; i++) {
  335. mpd->i2c[i] = devm_i2c_new_dummy_device(&client->dev,
  336. client->adapter,
  337. mt6360_slave_addr[i]);
  338. if (IS_ERR(mpd->i2c[i])) {
  339. dev_err(&client->dev,
  340. "Failed to get new dummy I2C device for address 0x%x",
  341. mt6360_slave_addr[i]);
  342. return PTR_ERR(mpd->i2c[i]);
  343. }
  344. i2c_set_clientdata(mpd->i2c[i], mpd);
  345. }
  346. ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO,
  347. mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL,
  348. 0, regmap_irq_get_domain(mpd->irq_data));
  349. if (ret) {
  350. dev_err(&client->dev,
  351. "Failed to register subordinate devices\n");
  352. return ret;
  353. }
  354. return 0;
  355. }
  356. static int __maybe_unused mt6360_pmu_suspend(struct device *dev)
  357. {
  358. struct i2c_client *i2c = to_i2c_client(dev);
  359. if (device_may_wakeup(dev))
  360. enable_irq_wake(i2c->irq);
  361. return 0;
  362. }
  363. static int __maybe_unused mt6360_pmu_resume(struct device *dev)
  364. {
  365. struct i2c_client *i2c = to_i2c_client(dev);
  366. if (device_may_wakeup(dev))
  367. disable_irq_wake(i2c->irq);
  368. return 0;
  369. }
  370. static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops,
  371. mt6360_pmu_suspend, mt6360_pmu_resume);
  372. static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = {
  373. { .compatible = "mediatek,mt6360_pmu", },
  374. {},
  375. };
  376. MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id);
  377. static struct i2c_driver mt6360_pmu_driver = {
  378. .driver = {
  379. .name = "mt6360_pmu",
  380. .pm = &mt6360_pmu_pm_ops,
  381. .of_match_table = of_match_ptr(mt6360_pmu_of_id),
  382. },
  383. .probe_new = mt6360_pmu_probe,
  384. };
  385. module_i2c_driver(mt6360_pmu_driver);
  386. MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");
  387. MODULE_DESCRIPTION("MT6360 PMU I2C Driver");
  388. MODULE_LICENSE("GPL v2");