max8997-irq.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // max8997-irq.c - Interrupt controller support for MAX8997
  4. //
  5. // Copyright (C) 2011 Samsung Electronics Co.Ltd
  6. // MyungJoo Ham <myungjoo.ham@samsung.com>
  7. //
  8. // This driver is based on max8998-irq.c
  9. #include <linux/err.h>
  10. #include <linux/irq.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/mfd/max8997.h>
  13. #include <linux/mfd/max8997-private.h>
  14. static const u8 max8997_mask_reg[] = {
  15. [PMIC_INT1] = MAX8997_REG_INT1MSK,
  16. [PMIC_INT2] = MAX8997_REG_INT2MSK,
  17. [PMIC_INT3] = MAX8997_REG_INT3MSK,
  18. [PMIC_INT4] = MAX8997_REG_INT4MSK,
  19. [FUEL_GAUGE] = MAX8997_REG_INVALID,
  20. [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
  21. [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
  22. [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
  23. [GPIO_LOW] = MAX8997_REG_INVALID,
  24. [GPIO_HI] = MAX8997_REG_INVALID,
  25. [FLASH_STATUS] = MAX8997_REG_INVALID,
  26. };
  27. static struct i2c_client *get_i2c(struct max8997_dev *max8997,
  28. enum max8997_irq_source src)
  29. {
  30. switch (src) {
  31. case PMIC_INT1 ... PMIC_INT4:
  32. return max8997->i2c;
  33. case FUEL_GAUGE:
  34. return NULL;
  35. case MUIC_INT1 ... MUIC_INT3:
  36. return max8997->muic;
  37. case GPIO_LOW ... GPIO_HI:
  38. return max8997->i2c;
  39. case FLASH_STATUS:
  40. return max8997->i2c;
  41. default:
  42. return ERR_PTR(-EINVAL);
  43. }
  44. }
  45. struct max8997_irq_data {
  46. int mask;
  47. enum max8997_irq_source group;
  48. };
  49. #define DECLARE_IRQ(idx, _group, _mask) \
  50. [(idx)] = { .group = (_group), .mask = (_mask) }
  51. static const struct max8997_irq_data max8997_irqs[] = {
  52. DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
  53. DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
  54. DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3),
  55. DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
  56. DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
  57. DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6),
  58. DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7),
  59. DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0),
  60. DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1),
  61. DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2),
  62. DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
  63. DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
  64. DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
  65. DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
  66. DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
  67. DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1),
  68. DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2),
  69. DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3),
  70. DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5),
  71. DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7),
  72. DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
  73. DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1),
  74. DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2),
  75. DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3),
  76. DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4),
  77. DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5),
  78. DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2),
  79. DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
  80. DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0),
  81. DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
  82. DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3),
  83. DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
  84. DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1),
  85. DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
  86. DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2),
  87. };
  88. static void max8997_irq_lock(struct irq_data *data)
  89. {
  90. struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
  91. mutex_lock(&max8997->irqlock);
  92. }
  93. static void max8997_irq_sync_unlock(struct irq_data *data)
  94. {
  95. struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
  96. int i;
  97. for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
  98. u8 mask_reg = max8997_mask_reg[i];
  99. struct i2c_client *i2c = get_i2c(max8997, i);
  100. if (mask_reg == MAX8997_REG_INVALID ||
  101. IS_ERR_OR_NULL(i2c))
  102. continue;
  103. max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
  104. max8997_write_reg(i2c, max8997_mask_reg[i],
  105. max8997->irq_masks_cur[i]);
  106. }
  107. mutex_unlock(&max8997->irqlock);
  108. }
  109. inline static const struct max8997_irq_data *
  110. irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
  111. {
  112. return &max8997_irqs[data->hwirq];
  113. }
  114. static void max8997_irq_mask(struct irq_data *data)
  115. {
  116. struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
  117. const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
  118. data);
  119. max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
  120. }
  121. static void max8997_irq_unmask(struct irq_data *data)
  122. {
  123. struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
  124. const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
  125. data);
  126. max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
  127. }
  128. static struct irq_chip max8997_irq_chip = {
  129. .name = "max8997",
  130. .irq_bus_lock = max8997_irq_lock,
  131. .irq_bus_sync_unlock = max8997_irq_sync_unlock,
  132. .irq_mask = max8997_irq_mask,
  133. .irq_unmask = max8997_irq_unmask,
  134. };
  135. #define MAX8997_IRQSRC_PMIC (1 << 1)
  136. #define MAX8997_IRQSRC_FUELGAUGE (1 << 2)
  137. #define MAX8997_IRQSRC_MUIC (1 << 3)
  138. #define MAX8997_IRQSRC_GPIO (1 << 4)
  139. #define MAX8997_IRQSRC_FLASH (1 << 5)
  140. static irqreturn_t max8997_irq_thread(int irq, void *data)
  141. {
  142. struct max8997_dev *max8997 = data;
  143. u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
  144. u8 irq_src;
  145. int ret;
  146. int i, cur_irq;
  147. ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
  148. if (ret < 0) {
  149. dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
  150. ret);
  151. return IRQ_NONE;
  152. }
  153. if (irq_src & MAX8997_IRQSRC_PMIC) {
  154. /* PMIC INT1 ~ INT4 */
  155. max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
  156. &irq_reg[PMIC_INT1]);
  157. }
  158. if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
  159. /*
  160. * TODO: FUEL GAUGE
  161. *
  162. * This is to be supported by Max17042 driver. When
  163. * an interrupt incurs here, it should be relayed to a
  164. * Max17042 device that is connected (probably by
  165. * platform-data). However, we do not have interrupt
  166. * handling in Max17042 driver currently. The Max17042 IRQ
  167. * driver should be ready to be used as a stand-alone device and
  168. * a Max8997-dependent device. Because it is not ready in
  169. * Max17042-side and it is not too critical in operating
  170. * Max8997, we do not implement this in initial releases.
  171. */
  172. irq_reg[FUEL_GAUGE] = 0;
  173. }
  174. if (irq_src & MAX8997_IRQSRC_MUIC) {
  175. /* MUIC INT1 ~ INT3 */
  176. max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
  177. &irq_reg[MUIC_INT1]);
  178. }
  179. if (irq_src & MAX8997_IRQSRC_GPIO) {
  180. /* GPIO Interrupt */
  181. u8 gpio_info[MAX8997_NUM_GPIO];
  182. irq_reg[GPIO_LOW] = 0;
  183. irq_reg[GPIO_HI] = 0;
  184. max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
  185. MAX8997_NUM_GPIO, gpio_info);
  186. for (i = 0; i < MAX8997_NUM_GPIO; i++) {
  187. bool interrupt = false;
  188. switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
  189. case MAX8997_GPIO_INT_BOTH:
  190. if (max8997->gpio_status[i] != gpio_info[i])
  191. interrupt = true;
  192. break;
  193. case MAX8997_GPIO_INT_RISE:
  194. if ((max8997->gpio_status[i] != gpio_info[i]) &&
  195. (gpio_info[i] & MAX8997_GPIO_DATA_MASK))
  196. interrupt = true;
  197. break;
  198. case MAX8997_GPIO_INT_FALL:
  199. if ((max8997->gpio_status[i] != gpio_info[i]) &&
  200. !(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
  201. interrupt = true;
  202. break;
  203. default:
  204. break;
  205. }
  206. if (interrupt) {
  207. if (i < 8)
  208. irq_reg[GPIO_LOW] |= (1 << i);
  209. else
  210. irq_reg[GPIO_HI] |= (1 << (i - 8));
  211. }
  212. }
  213. }
  214. if (irq_src & MAX8997_IRQSRC_FLASH) {
  215. /* Flash Status Interrupt */
  216. ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
  217. &irq_reg[FLASH_STATUS]);
  218. }
  219. /* Apply masking */
  220. for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
  221. irq_reg[i] &= ~max8997->irq_masks_cur[i];
  222. /* Report */
  223. for (i = 0; i < MAX8997_IRQ_NR; i++) {
  224. if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
  225. cur_irq = irq_find_mapping(max8997->irq_domain, i);
  226. if (cur_irq)
  227. handle_nested_irq(cur_irq);
  228. }
  229. }
  230. return IRQ_HANDLED;
  231. }
  232. int max8997_irq_resume(struct max8997_dev *max8997)
  233. {
  234. if (max8997->irq && max8997->irq_domain)
  235. max8997_irq_thread(0, max8997);
  236. return 0;
  237. }
  238. static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
  239. irq_hw_number_t hw)
  240. {
  241. struct max8997_dev *max8997 = d->host_data;
  242. irq_set_chip_data(irq, max8997);
  243. irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
  244. irq_set_nested_thread(irq, 1);
  245. irq_set_noprobe(irq);
  246. return 0;
  247. }
  248. static const struct irq_domain_ops max8997_irq_domain_ops = {
  249. .map = max8997_irq_domain_map,
  250. };
  251. int max8997_irq_init(struct max8997_dev *max8997)
  252. {
  253. struct irq_domain *domain;
  254. int i;
  255. int ret;
  256. u8 val;
  257. if (!max8997->irq) {
  258. dev_warn(max8997->dev, "No interrupt specified.\n");
  259. return 0;
  260. }
  261. mutex_init(&max8997->irqlock);
  262. /* Mask individual interrupt sources */
  263. for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
  264. struct i2c_client *i2c;
  265. max8997->irq_masks_cur[i] = 0xff;
  266. max8997->irq_masks_cache[i] = 0xff;
  267. i2c = get_i2c(max8997, i);
  268. if (IS_ERR_OR_NULL(i2c))
  269. continue;
  270. if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
  271. continue;
  272. max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
  273. }
  274. for (i = 0; i < MAX8997_NUM_GPIO; i++) {
  275. max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
  276. MAX8997_REG_GPIOCNTL1 + i,
  277. &val)
  278. & MAX8997_GPIO_DATA_MASK) ?
  279. true : false;
  280. }
  281. domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
  282. &max8997_irq_domain_ops, max8997);
  283. if (!domain) {
  284. dev_err(max8997->dev, "could not create irq domain\n");
  285. return -ENODEV;
  286. }
  287. max8997->irq_domain = domain;
  288. ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
  289. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  290. "max8997-irq", max8997);
  291. if (ret) {
  292. dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
  293. max8997->irq, ret);
  294. return ret;
  295. }
  296. if (!max8997->ono)
  297. return 0;
  298. ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
  299. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
  300. IRQF_ONESHOT, "max8997-ono", max8997);
  301. if (ret)
  302. dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
  303. max8997->ono, ret);
  304. return 0;
  305. }
  306. void max8997_irq_exit(struct max8997_dev *max8997)
  307. {
  308. if (max8997->ono)
  309. free_irq(max8997->ono, max8997);
  310. if (max8997->irq)
  311. free_irq(max8997->irq, max8997);
  312. }