max77620.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Maxim MAX77620 MFD Driver
  4. *
  5. * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author:
  8. * Laxman Dewangan <ldewangan@nvidia.com>
  9. * Chaitanya Bandi <bandik@nvidia.com>
  10. * Mallikarjun Kasoju <mkasoju@nvidia.com>
  11. */
  12. /****************** Teminology used in driver ********************
  13. * Here are some terminology used from datasheet for quick reference:
  14. * Flexible Power Sequence (FPS):
  15. * The Flexible Power Sequencer (FPS) allows each regulator to power up under
  16. * hardware or software control. Additionally, each regulator can power on
  17. * independently or among a group of other regulators with an adjustable
  18. * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
  19. * be programmed to be part of a sequence allowing external regulators to be
  20. * sequenced along with internal regulators. 32KHz clock can be programmed to
  21. * be part of a sequence.
  22. * There is 3 FPS confguration registers and all resources are configured to
  23. * any of these FPS or no FPS.
  24. */
  25. #include <linux/i2c.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/mfd/core.h>
  28. #include <linux/mfd/max77620.h>
  29. #include <linux/init.h>
  30. #include <linux/of.h>
  31. #include <linux/of_device.h>
  32. #include <linux/regmap.h>
  33. #include <linux/slab.h>
  34. static struct max77620_chip *max77620_scratch;
  35. static const struct resource gpio_resources[] = {
  36. DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
  37. };
  38. static const struct resource power_resources[] = {
  39. DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
  40. };
  41. static const struct resource rtc_resources[] = {
  42. DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
  43. };
  44. static const struct resource thermal_resources[] = {
  45. DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
  46. DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
  47. };
  48. static const struct regmap_irq max77620_top_irqs[] = {
  49. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
  50. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
  51. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
  52. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
  53. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
  54. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
  55. REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
  56. REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
  57. REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
  58. REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
  59. };
  60. static const struct mfd_cell max77620_children[] = {
  61. { .name = "max77620-pinctrl", },
  62. { .name = "max77620-clock", },
  63. { .name = "max77620-pmic", },
  64. { .name = "max77620-watchdog", },
  65. {
  66. .name = "max77620-gpio",
  67. .resources = gpio_resources,
  68. .num_resources = ARRAY_SIZE(gpio_resources),
  69. }, {
  70. .name = "max77620-rtc",
  71. .resources = rtc_resources,
  72. .num_resources = ARRAY_SIZE(rtc_resources),
  73. }, {
  74. .name = "max77620-power",
  75. .resources = power_resources,
  76. .num_resources = ARRAY_SIZE(power_resources),
  77. }, {
  78. .name = "max77620-thermal",
  79. .resources = thermal_resources,
  80. .num_resources = ARRAY_SIZE(thermal_resources),
  81. },
  82. };
  83. static const struct mfd_cell max20024_children[] = {
  84. { .name = "max20024-pinctrl", },
  85. { .name = "max77620-clock", },
  86. { .name = "max20024-pmic", },
  87. { .name = "max77620-watchdog", },
  88. {
  89. .name = "max77620-gpio",
  90. .resources = gpio_resources,
  91. .num_resources = ARRAY_SIZE(gpio_resources),
  92. }, {
  93. .name = "max77620-rtc",
  94. .resources = rtc_resources,
  95. .num_resources = ARRAY_SIZE(rtc_resources),
  96. }, {
  97. .name = "max20024-power",
  98. .resources = power_resources,
  99. .num_resources = ARRAY_SIZE(power_resources),
  100. },
  101. };
  102. static const struct mfd_cell max77663_children[] = {
  103. { .name = "max77620-pinctrl", },
  104. { .name = "max77620-clock", },
  105. { .name = "max77663-pmic", },
  106. { .name = "max77620-watchdog", },
  107. {
  108. .name = "max77620-gpio",
  109. .resources = gpio_resources,
  110. .num_resources = ARRAY_SIZE(gpio_resources),
  111. }, {
  112. .name = "max77620-rtc",
  113. .resources = rtc_resources,
  114. .num_resources = ARRAY_SIZE(rtc_resources),
  115. }, {
  116. .name = "max77663-power",
  117. .resources = power_resources,
  118. .num_resources = ARRAY_SIZE(power_resources),
  119. },
  120. };
  121. static const struct regmap_range max77620_readable_ranges[] = {
  122. regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
  123. };
  124. static const struct regmap_access_table max77620_readable_table = {
  125. .yes_ranges = max77620_readable_ranges,
  126. .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
  127. };
  128. static const struct regmap_range max20024_readable_ranges[] = {
  129. regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
  130. regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
  131. };
  132. static const struct regmap_access_table max20024_readable_table = {
  133. .yes_ranges = max20024_readable_ranges,
  134. .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
  135. };
  136. static const struct regmap_range max77620_writable_ranges[] = {
  137. regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
  138. };
  139. static const struct regmap_access_table max77620_writable_table = {
  140. .yes_ranges = max77620_writable_ranges,
  141. .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
  142. };
  143. static const struct regmap_range max77620_cacheable_ranges[] = {
  144. regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
  145. regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
  146. };
  147. static const struct regmap_access_table max77620_volatile_table = {
  148. .no_ranges = max77620_cacheable_ranges,
  149. .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
  150. };
  151. static const struct regmap_config max77620_regmap_config = {
  152. .name = "power-slave",
  153. .reg_bits = 8,
  154. .val_bits = 8,
  155. .max_register = MAX77620_REG_DVSSD4 + 1,
  156. .cache_type = REGCACHE_RBTREE,
  157. .rd_table = &max77620_readable_table,
  158. .wr_table = &max77620_writable_table,
  159. .volatile_table = &max77620_volatile_table,
  160. .use_single_write = true,
  161. };
  162. static const struct regmap_config max20024_regmap_config = {
  163. .name = "power-slave",
  164. .reg_bits = 8,
  165. .val_bits = 8,
  166. .max_register = MAX20024_REG_MAX_ADD + 1,
  167. .cache_type = REGCACHE_RBTREE,
  168. .rd_table = &max20024_readable_table,
  169. .wr_table = &max77620_writable_table,
  170. .volatile_table = &max77620_volatile_table,
  171. };
  172. static const struct regmap_range max77663_readable_ranges[] = {
  173. regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
  174. };
  175. static const struct regmap_access_table max77663_readable_table = {
  176. .yes_ranges = max77663_readable_ranges,
  177. .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
  178. };
  179. static const struct regmap_range max77663_writable_ranges[] = {
  180. regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
  181. };
  182. static const struct regmap_access_table max77663_writable_table = {
  183. .yes_ranges = max77663_writable_ranges,
  184. .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
  185. };
  186. static const struct regmap_config max77663_regmap_config = {
  187. .name = "power-slave",
  188. .reg_bits = 8,
  189. .val_bits = 8,
  190. .max_register = MAX77620_REG_CID5 + 1,
  191. .cache_type = REGCACHE_RBTREE,
  192. .rd_table = &max77663_readable_table,
  193. .wr_table = &max77663_writable_table,
  194. .volatile_table = &max77620_volatile_table,
  195. };
  196. /*
  197. * MAX77620 and MAX20024 has the following steps of the interrupt handling
  198. * for TOP interrupts:
  199. * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
  200. * 2. Read IRQTOP and service the interrupt.
  201. * 3. Once all interrupts has been checked and serviced, the interrupt service
  202. * routine un-masks the hardware interrupt line by clearing GLBLM.
  203. */
  204. static int max77620_irq_global_mask(void *irq_drv_data)
  205. {
  206. struct max77620_chip *chip = irq_drv_data;
  207. int ret;
  208. ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
  209. MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
  210. if (ret < 0)
  211. dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
  212. return ret;
  213. }
  214. static int max77620_irq_global_unmask(void *irq_drv_data)
  215. {
  216. struct max77620_chip *chip = irq_drv_data;
  217. int ret;
  218. ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
  219. MAX77620_GLBLM_MASK, 0);
  220. if (ret < 0)
  221. dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
  222. return ret;
  223. }
  224. static struct regmap_irq_chip max77620_top_irq_chip = {
  225. .name = "max77620-top",
  226. .irqs = max77620_top_irqs,
  227. .num_irqs = ARRAY_SIZE(max77620_top_irqs),
  228. .num_regs = 2,
  229. .status_base = MAX77620_REG_IRQTOP,
  230. .mask_base = MAX77620_REG_IRQTOPM,
  231. .handle_pre_irq = max77620_irq_global_mask,
  232. .handle_post_irq = max77620_irq_global_unmask,
  233. };
  234. /* max77620_get_fps_period_reg_value: Get FPS bit field value from
  235. * requested periods.
  236. * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
  237. * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
  238. * 160, 320, 540, 1280 and 2560 microseconds.
  239. * The FPS register has 3 bits field to set the FPS period as
  240. * bits max77620 max20024
  241. * 000 40 20
  242. * 001 80 40
  243. * :::
  244. */
  245. static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
  246. int tperiod)
  247. {
  248. int fps_min_period;
  249. int i;
  250. switch (chip->chip_id) {
  251. case MAX20024:
  252. fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
  253. break;
  254. case MAX77620:
  255. fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
  256. break;
  257. case MAX77663:
  258. fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
  259. break;
  260. default:
  261. return -EINVAL;
  262. }
  263. for (i = 0; i < 7; i++) {
  264. if (fps_min_period >= tperiod)
  265. return i;
  266. fps_min_period *= 2;
  267. }
  268. return i;
  269. }
  270. /* max77620_config_fps: Configure FPS configuration registers
  271. * based on platform specific information.
  272. */
  273. static int max77620_config_fps(struct max77620_chip *chip,
  274. struct device_node *fps_np)
  275. {
  276. struct device *dev = chip->dev;
  277. unsigned int mask = 0, config = 0;
  278. u32 fps_max_period;
  279. u32 param_val;
  280. int tperiod, fps_id;
  281. int ret;
  282. char fps_name[10];
  283. switch (chip->chip_id) {
  284. case MAX20024:
  285. fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
  286. break;
  287. case MAX77620:
  288. fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
  289. break;
  290. case MAX77663:
  291. fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
  292. break;
  293. default:
  294. return -EINVAL;
  295. }
  296. for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
  297. sprintf(fps_name, "fps%d", fps_id);
  298. if (of_node_name_eq(fps_np, fps_name))
  299. break;
  300. }
  301. if (fps_id == MAX77620_FPS_COUNT) {
  302. dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
  303. return -EINVAL;
  304. }
  305. ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
  306. &param_val);
  307. if (!ret) {
  308. mask |= MAX77620_FPS_TIME_PERIOD_MASK;
  309. chip->shutdown_fps_period[fps_id] = min(param_val,
  310. fps_max_period);
  311. tperiod = max77620_get_fps_period_reg_value(chip,
  312. chip->shutdown_fps_period[fps_id]);
  313. config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
  314. }
  315. ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
  316. &param_val);
  317. if (!ret)
  318. chip->suspend_fps_period[fps_id] = min(param_val,
  319. fps_max_period);
  320. ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
  321. &param_val);
  322. if (!ret) {
  323. if (param_val > 2) {
  324. dev_err(dev, "FPS%d event-source invalid\n", fps_id);
  325. return -EINVAL;
  326. }
  327. mask |= MAX77620_FPS_EN_SRC_MASK;
  328. config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
  329. if (param_val == 2) {
  330. mask |= MAX77620_FPS_ENFPS_SW_MASK;
  331. config |= MAX77620_FPS_ENFPS_SW;
  332. }
  333. }
  334. if (!chip->sleep_enable && !chip->enable_global_lpm) {
  335. ret = of_property_read_u32(fps_np,
  336. "maxim,device-state-on-disabled-event",
  337. &param_val);
  338. if (!ret) {
  339. if (param_val == 0)
  340. chip->sleep_enable = true;
  341. else if (param_val == 1)
  342. chip->enable_global_lpm = true;
  343. }
  344. }
  345. ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
  346. mask, config);
  347. if (ret < 0) {
  348. dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
  349. return ret;
  350. }
  351. return 0;
  352. }
  353. static int max77620_initialise_fps(struct max77620_chip *chip)
  354. {
  355. struct device *dev = chip->dev;
  356. struct device_node *fps_np, *fps_child;
  357. u8 config;
  358. int fps_id;
  359. int ret;
  360. for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
  361. chip->shutdown_fps_period[fps_id] = -1;
  362. chip->suspend_fps_period[fps_id] = -1;
  363. }
  364. fps_np = of_get_child_by_name(dev->of_node, "fps");
  365. if (!fps_np)
  366. goto skip_fps;
  367. for_each_child_of_node(fps_np, fps_child) {
  368. ret = max77620_config_fps(chip, fps_child);
  369. if (ret < 0) {
  370. of_node_put(fps_child);
  371. return ret;
  372. }
  373. }
  374. config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
  375. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
  376. MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
  377. if (ret < 0) {
  378. dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
  379. return ret;
  380. }
  381. skip_fps:
  382. if (chip->chip_id == MAX77663)
  383. return 0;
  384. /* Enable wake on EN0 pin */
  385. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
  386. MAX77620_ONOFFCNFG2_WK_EN0,
  387. MAX77620_ONOFFCNFG2_WK_EN0);
  388. if (ret < 0) {
  389. dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
  390. return ret;
  391. }
  392. /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
  393. if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
  394. config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
  395. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
  396. config, config);
  397. if (ret < 0) {
  398. dev_err(dev, "Failed to update SLPEN: %d\n", ret);
  399. return ret;
  400. }
  401. }
  402. return 0;
  403. }
  404. static int max77620_read_es_version(struct max77620_chip *chip)
  405. {
  406. unsigned int val;
  407. u8 cid_val[6];
  408. int i;
  409. int ret;
  410. for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
  411. ret = regmap_read(chip->rmap, i, &val);
  412. if (ret < 0) {
  413. dev_err(chip->dev, "Failed to read CID: %d\n", ret);
  414. return ret;
  415. }
  416. dev_dbg(chip->dev, "CID%d: 0x%02x\n",
  417. i - MAX77620_REG_CID0, val);
  418. cid_val[i - MAX77620_REG_CID0] = val;
  419. }
  420. /* CID4 is OTP Version and CID5 is ES version */
  421. dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
  422. cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
  423. return ret;
  424. }
  425. static void max77620_pm_power_off(void)
  426. {
  427. struct max77620_chip *chip = max77620_scratch;
  428. regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
  429. MAX77620_ONOFFCNFG1_SFT_RST,
  430. MAX77620_ONOFFCNFG1_SFT_RST);
  431. }
  432. static int max77620_probe(struct i2c_client *client,
  433. const struct i2c_device_id *id)
  434. {
  435. const struct regmap_config *rmap_config;
  436. struct max77620_chip *chip;
  437. const struct mfd_cell *mfd_cells;
  438. int n_mfd_cells;
  439. bool pm_off;
  440. int ret;
  441. chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
  442. if (!chip)
  443. return -ENOMEM;
  444. i2c_set_clientdata(client, chip);
  445. chip->dev = &client->dev;
  446. chip->chip_irq = client->irq;
  447. chip->chip_id = (enum max77620_chip_id)id->driver_data;
  448. switch (chip->chip_id) {
  449. case MAX77620:
  450. mfd_cells = max77620_children;
  451. n_mfd_cells = ARRAY_SIZE(max77620_children);
  452. rmap_config = &max77620_regmap_config;
  453. break;
  454. case MAX20024:
  455. mfd_cells = max20024_children;
  456. n_mfd_cells = ARRAY_SIZE(max20024_children);
  457. rmap_config = &max20024_regmap_config;
  458. break;
  459. case MAX77663:
  460. mfd_cells = max77663_children;
  461. n_mfd_cells = ARRAY_SIZE(max77663_children);
  462. rmap_config = &max77663_regmap_config;
  463. break;
  464. default:
  465. dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
  466. return -EINVAL;
  467. }
  468. chip->rmap = devm_regmap_init_i2c(client, rmap_config);
  469. if (IS_ERR(chip->rmap)) {
  470. ret = PTR_ERR(chip->rmap);
  471. dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
  472. return ret;
  473. }
  474. ret = max77620_read_es_version(chip);
  475. if (ret < 0)
  476. return ret;
  477. max77620_top_irq_chip.irq_drv_data = chip;
  478. ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
  479. IRQF_ONESHOT | IRQF_SHARED, 0,
  480. &max77620_top_irq_chip,
  481. &chip->top_irq_data);
  482. if (ret < 0) {
  483. dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
  484. return ret;
  485. }
  486. ret = max77620_initialise_fps(chip);
  487. if (ret < 0)
  488. return ret;
  489. ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
  490. mfd_cells, n_mfd_cells, NULL, 0,
  491. regmap_irq_get_domain(chip->top_irq_data));
  492. if (ret < 0) {
  493. dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
  494. return ret;
  495. }
  496. pm_off = of_device_is_system_power_controller(client->dev.of_node);
  497. if (pm_off && !pm_power_off) {
  498. max77620_scratch = chip;
  499. pm_power_off = max77620_pm_power_off;
  500. }
  501. return 0;
  502. }
  503. #ifdef CONFIG_PM_SLEEP
  504. static int max77620_set_fps_period(struct max77620_chip *chip,
  505. int fps_id, int time_period)
  506. {
  507. int period = max77620_get_fps_period_reg_value(chip, time_period);
  508. int ret;
  509. ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
  510. MAX77620_FPS_TIME_PERIOD_MASK,
  511. period << MAX77620_FPS_TIME_PERIOD_SHIFT);
  512. if (ret < 0) {
  513. dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
  514. return ret;
  515. }
  516. return 0;
  517. }
  518. static int max77620_i2c_suspend(struct device *dev)
  519. {
  520. struct max77620_chip *chip = dev_get_drvdata(dev);
  521. struct i2c_client *client = to_i2c_client(dev);
  522. unsigned int config;
  523. int fps;
  524. int ret;
  525. for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
  526. if (chip->suspend_fps_period[fps] < 0)
  527. continue;
  528. ret = max77620_set_fps_period(chip, fps,
  529. chip->suspend_fps_period[fps]);
  530. if (ret < 0)
  531. return ret;
  532. }
  533. /*
  534. * For MAX20024: No need to configure SLPEN on suspend as
  535. * it will be configured on Init.
  536. */
  537. if (chip->chip_id == MAX20024)
  538. goto out;
  539. config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
  540. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
  541. MAX77620_ONOFFCNFG1_SLPEN,
  542. config);
  543. if (ret < 0) {
  544. dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
  545. return ret;
  546. }
  547. if (chip->chip_id == MAX77663)
  548. goto out;
  549. /* Disable WK_EN0 */
  550. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
  551. MAX77620_ONOFFCNFG2_WK_EN0, 0);
  552. if (ret < 0) {
  553. dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
  554. return ret;
  555. }
  556. out:
  557. disable_irq(client->irq);
  558. return 0;
  559. }
  560. static int max77620_i2c_resume(struct device *dev)
  561. {
  562. struct max77620_chip *chip = dev_get_drvdata(dev);
  563. struct i2c_client *client = to_i2c_client(dev);
  564. int ret;
  565. int fps;
  566. for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
  567. if (chip->shutdown_fps_period[fps] < 0)
  568. continue;
  569. ret = max77620_set_fps_period(chip, fps,
  570. chip->shutdown_fps_period[fps]);
  571. if (ret < 0)
  572. return ret;
  573. }
  574. /*
  575. * For MAX20024: No need to configure WKEN0 on resume as
  576. * it is configured on Init.
  577. */
  578. if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
  579. goto out;
  580. /* Enable WK_EN0 */
  581. ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
  582. MAX77620_ONOFFCNFG2_WK_EN0,
  583. MAX77620_ONOFFCNFG2_WK_EN0);
  584. if (ret < 0) {
  585. dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
  586. return ret;
  587. }
  588. out:
  589. enable_irq(client->irq);
  590. return 0;
  591. }
  592. #endif
  593. static const struct i2c_device_id max77620_id[] = {
  594. {"max77620", MAX77620},
  595. {"max20024", MAX20024},
  596. {"max77663", MAX77663},
  597. {},
  598. };
  599. static const struct dev_pm_ops max77620_pm_ops = {
  600. SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
  601. };
  602. static struct i2c_driver max77620_driver = {
  603. .driver = {
  604. .name = "max77620",
  605. .pm = &max77620_pm_ops,
  606. },
  607. .probe = max77620_probe,
  608. .id_table = max77620_id,
  609. };
  610. builtin_i2c_driver(max77620_driver);