intel_soc_pmic_crc.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device access for Crystal Cove PMIC
  4. *
  5. * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
  6. *
  7. * Author: Yang, Bin <bin.yang@intel.com>
  8. * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
  9. */
  10. #include <linux/interrupt.h>
  11. #include <linux/regmap.h>
  12. #include <linux/mfd/core.h>
  13. #include <linux/mfd/intel_soc_pmic.h>
  14. #include "intel_soc_pmic_core.h"
  15. #define CRYSTAL_COVE_MAX_REGISTER 0xC6
  16. #define CRYSTAL_COVE_REG_IRQLVL1 0x02
  17. #define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
  18. #define CRYSTAL_COVE_IRQ_PWRSRC 0
  19. #define CRYSTAL_COVE_IRQ_THRM 1
  20. #define CRYSTAL_COVE_IRQ_BCU 2
  21. #define CRYSTAL_COVE_IRQ_ADC 3
  22. #define CRYSTAL_COVE_IRQ_CHGR 4
  23. #define CRYSTAL_COVE_IRQ_GPIO 5
  24. #define CRYSTAL_COVE_IRQ_VHDMIOCP 6
  25. static struct resource gpio_resources[] = {
  26. DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
  27. };
  28. static struct resource pwrsrc_resources[] = {
  29. DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
  30. };
  31. static struct resource adc_resources[] = {
  32. DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
  33. };
  34. static struct resource thermal_resources[] = {
  35. DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
  36. };
  37. static struct resource bcu_resources[] = {
  38. DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
  39. };
  40. static struct mfd_cell crystal_cove_byt_dev[] = {
  41. {
  42. .name = "crystal_cove_pwrsrc",
  43. .num_resources = ARRAY_SIZE(pwrsrc_resources),
  44. .resources = pwrsrc_resources,
  45. },
  46. {
  47. .name = "crystal_cove_adc",
  48. .num_resources = ARRAY_SIZE(adc_resources),
  49. .resources = adc_resources,
  50. },
  51. {
  52. .name = "crystal_cove_thermal",
  53. .num_resources = ARRAY_SIZE(thermal_resources),
  54. .resources = thermal_resources,
  55. },
  56. {
  57. .name = "crystal_cove_bcu",
  58. .num_resources = ARRAY_SIZE(bcu_resources),
  59. .resources = bcu_resources,
  60. },
  61. {
  62. .name = "crystal_cove_gpio",
  63. .num_resources = ARRAY_SIZE(gpio_resources),
  64. .resources = gpio_resources,
  65. },
  66. {
  67. .name = "byt_crystal_cove_pmic",
  68. },
  69. {
  70. .name = "crystal_cove_pwm",
  71. },
  72. };
  73. static struct mfd_cell crystal_cove_cht_dev[] = {
  74. {
  75. .name = "crystal_cove_gpio",
  76. .num_resources = ARRAY_SIZE(gpio_resources),
  77. .resources = gpio_resources,
  78. },
  79. {
  80. .name = "cht_crystal_cove_pmic",
  81. },
  82. {
  83. .name = "crystal_cove_pwm",
  84. },
  85. };
  86. static const struct regmap_config crystal_cove_regmap_config = {
  87. .reg_bits = 8,
  88. .val_bits = 8,
  89. .max_register = CRYSTAL_COVE_MAX_REGISTER,
  90. .cache_type = REGCACHE_NONE,
  91. };
  92. static const struct regmap_irq crystal_cove_irqs[] = {
  93. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
  94. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
  95. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
  96. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
  97. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
  98. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
  99. REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
  100. };
  101. static const struct regmap_irq_chip crystal_cove_irq_chip = {
  102. .name = "Crystal Cove",
  103. .irqs = crystal_cove_irqs,
  104. .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
  105. .num_regs = 1,
  106. .status_base = CRYSTAL_COVE_REG_IRQLVL1,
  107. .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
  108. };
  109. struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
  110. .irq_flags = IRQF_TRIGGER_RISING,
  111. .cell_dev = crystal_cove_byt_dev,
  112. .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
  113. .regmap_config = &crystal_cove_regmap_config,
  114. .irq_chip = &crystal_cove_irq_chip,
  115. };
  116. struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
  117. .irq_flags = IRQF_TRIGGER_RISING,
  118. .cell_dev = crystal_cove_cht_dev,
  119. .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
  120. .regmap_config = &crystal_cove_regmap_config,
  121. .irq_chip = &crystal_cove_irq_chip,
  122. };