intel_msic.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Intel MSIC
  4. *
  5. * Copyright (C) 2011, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/err.h>
  9. #include <linux/gpio.h>
  10. #include <linux/io.h>
  11. #include <linux/init.h>
  12. #include <linux/mfd/core.h>
  13. #include <linux/mfd/intel_msic.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <asm/intel_scu_ipc.h>
  17. #define MSIC_VENDOR(id) ((id >> 6) & 3)
  18. #define MSIC_VERSION(id) (id & 0x3f)
  19. #define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
  20. #define MSIC_MINOR(id) (id & 7)
  21. /*
  22. * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
  23. * Since IRQ block starts from address 0x002 we need to subtract that from
  24. * the actual IRQ status register address.
  25. */
  26. #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
  27. #define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
  28. /*
  29. * The SCU hardware has limitation of 16 bytes per read/write buffer on
  30. * Medfield.
  31. */
  32. #define SCU_IPC_RWBUF_LIMIT 16
  33. /**
  34. * struct intel_msic - an MSIC MFD instance
  35. * @pdev: pointer to the platform device
  36. * @vendor: vendor ID
  37. * @version: chip version
  38. * @irq_base: base address of the mapped MSIC SRAM interrupt tree
  39. */
  40. struct intel_msic {
  41. struct platform_device *pdev;
  42. unsigned vendor;
  43. unsigned version;
  44. void __iomem *irq_base;
  45. };
  46. static struct resource msic_touch_resources[] = {
  47. DEFINE_RES_IRQ(0),
  48. };
  49. static struct resource msic_adc_resources[] = {
  50. DEFINE_RES_IRQ(0),
  51. };
  52. static struct resource msic_battery_resources[] = {
  53. DEFINE_RES_IRQ(0),
  54. };
  55. static struct resource msic_gpio_resources[] = {
  56. DEFINE_RES_IRQ(0),
  57. };
  58. static struct resource msic_audio_resources[] = {
  59. DEFINE_RES_IRQ_NAMED(0, "IRQ"),
  60. /*
  61. * We will pass IRQ_BASE to the driver now but this can be removed
  62. * when/if the driver starts to use intel_msic_irq_read().
  63. */
  64. DEFINE_RES_MEM_NAMED(MSIC_IRQ_STATUS_ACCDET, 1, "IRQ_BASE"),
  65. };
  66. static struct resource msic_hdmi_resources[] = {
  67. DEFINE_RES_IRQ(0),
  68. };
  69. static struct resource msic_thermal_resources[] = {
  70. DEFINE_RES_IRQ(0),
  71. };
  72. static struct resource msic_power_btn_resources[] = {
  73. DEFINE_RES_IRQ(0),
  74. };
  75. static struct resource msic_ocd_resources[] = {
  76. DEFINE_RES_IRQ(0),
  77. };
  78. /*
  79. * Devices that are part of the MSIC and are available via firmware
  80. * populated SFI DEVS table.
  81. */
  82. static struct mfd_cell msic_devs[] = {
  83. [INTEL_MSIC_BLOCK_TOUCH] = {
  84. .name = "msic_touch",
  85. .num_resources = ARRAY_SIZE(msic_touch_resources),
  86. .resources = msic_touch_resources,
  87. },
  88. [INTEL_MSIC_BLOCK_ADC] = {
  89. .name = "msic_adc",
  90. .num_resources = ARRAY_SIZE(msic_adc_resources),
  91. .resources = msic_adc_resources,
  92. },
  93. [INTEL_MSIC_BLOCK_BATTERY] = {
  94. .name = "msic_battery",
  95. .num_resources = ARRAY_SIZE(msic_battery_resources),
  96. .resources = msic_battery_resources,
  97. },
  98. [INTEL_MSIC_BLOCK_GPIO] = {
  99. .name = "msic_gpio",
  100. .num_resources = ARRAY_SIZE(msic_gpio_resources),
  101. .resources = msic_gpio_resources,
  102. },
  103. [INTEL_MSIC_BLOCK_AUDIO] = {
  104. .name = "msic_audio",
  105. .num_resources = ARRAY_SIZE(msic_audio_resources),
  106. .resources = msic_audio_resources,
  107. },
  108. [INTEL_MSIC_BLOCK_HDMI] = {
  109. .name = "msic_hdmi",
  110. .num_resources = ARRAY_SIZE(msic_hdmi_resources),
  111. .resources = msic_hdmi_resources,
  112. },
  113. [INTEL_MSIC_BLOCK_THERMAL] = {
  114. .name = "msic_thermal",
  115. .num_resources = ARRAY_SIZE(msic_thermal_resources),
  116. .resources = msic_thermal_resources,
  117. },
  118. [INTEL_MSIC_BLOCK_POWER_BTN] = {
  119. .name = "msic_power_btn",
  120. .num_resources = ARRAY_SIZE(msic_power_btn_resources),
  121. .resources = msic_power_btn_resources,
  122. },
  123. [INTEL_MSIC_BLOCK_OCD] = {
  124. .name = "msic_ocd",
  125. .num_resources = ARRAY_SIZE(msic_ocd_resources),
  126. .resources = msic_ocd_resources,
  127. },
  128. };
  129. /*
  130. * Other MSIC related devices which are not directly available via SFI DEVS
  131. * table. These can be pseudo devices, regulators etc. which are needed for
  132. * different purposes.
  133. *
  134. * These devices appear only after the MSIC driver itself is initialized so
  135. * we can guarantee that the SCU IPC interface is ready.
  136. */
  137. static const struct mfd_cell msic_other_devs[] = {
  138. /* Audio codec in the MSIC */
  139. {
  140. .id = -1,
  141. .name = "sn95031",
  142. },
  143. };
  144. /**
  145. * intel_msic_reg_read - read a single MSIC register
  146. * @reg: register to read
  147. * @val: register value is placed here
  148. *
  149. * Read a single register from MSIC. Returns %0 on success and negative
  150. * errno in case of failure.
  151. *
  152. * Function may sleep.
  153. */
  154. int intel_msic_reg_read(unsigned short reg, u8 *val)
  155. {
  156. return intel_scu_ipc_ioread8(reg, val);
  157. }
  158. EXPORT_SYMBOL_GPL(intel_msic_reg_read);
  159. /**
  160. * intel_msic_reg_write - write a single MSIC register
  161. * @reg: register to write
  162. * @val: value to write to that register
  163. *
  164. * Write a single MSIC register. Returns 0 on success and negative
  165. * errno in case of failure.
  166. *
  167. * Function may sleep.
  168. */
  169. int intel_msic_reg_write(unsigned short reg, u8 val)
  170. {
  171. return intel_scu_ipc_iowrite8(reg, val);
  172. }
  173. EXPORT_SYMBOL_GPL(intel_msic_reg_write);
  174. /**
  175. * intel_msic_reg_update - update a single MSIC register
  176. * @reg: register to update
  177. * @val: value to write to the register
  178. * @mask: specifies which of the bits are updated (%0 = don't update,
  179. * %1 = update)
  180. *
  181. * Perform an update to a register @reg. @mask is used to specify which
  182. * bits are updated. Returns %0 in case of success and negative errno in
  183. * case of failure.
  184. *
  185. * Function may sleep.
  186. */
  187. int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
  188. {
  189. return intel_scu_ipc_update_register(reg, val, mask);
  190. }
  191. EXPORT_SYMBOL_GPL(intel_msic_reg_update);
  192. /**
  193. * intel_msic_bulk_read - read an array of registers
  194. * @reg: array of register addresses to read
  195. * @buf: array where the read values are placed
  196. * @count: number of registers to read
  197. *
  198. * Function reads @count registers from the MSIC using addresses passed in
  199. * @reg. Read values are placed in @buf. Reads are performed atomically
  200. * wrt. MSIC.
  201. *
  202. * Returns %0 in case of success and negative errno in case of failure.
  203. *
  204. * Function may sleep.
  205. */
  206. int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count)
  207. {
  208. if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
  209. return -EINVAL;
  210. return intel_scu_ipc_readv(reg, buf, count);
  211. }
  212. EXPORT_SYMBOL_GPL(intel_msic_bulk_read);
  213. /**
  214. * intel_msic_bulk_write - write an array of values to the MSIC registers
  215. * @reg: array of registers to write
  216. * @buf: values to write to each register
  217. * @count: number of registers to write
  218. *
  219. * Function writes @count registers in @buf to MSIC. Writes are performed
  220. * atomically wrt MSIC. Returns %0 in case of success and negative errno in
  221. * case of failure.
  222. *
  223. * Function may sleep.
  224. */
  225. int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count)
  226. {
  227. if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
  228. return -EINVAL;
  229. return intel_scu_ipc_writev(reg, buf, count);
  230. }
  231. EXPORT_SYMBOL_GPL(intel_msic_bulk_write);
  232. /**
  233. * intel_msic_irq_read - read a register from an MSIC interrupt tree
  234. * @msic: MSIC instance
  235. * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
  236. * %INTEL_MSIC_RESETIRQ2)
  237. * @val: value of the register is placed here
  238. *
  239. * This function can be used by an MSIC subdevice interrupt handler to read
  240. * a register value from the MSIC interrupt tree. In this way subdevice
  241. * drivers don't have to map in the interrupt tree themselves but can just
  242. * call this function instead.
  243. *
  244. * Function doesn't sleep and is callable from interrupt context.
  245. *
  246. * Returns %-EINVAL if @reg is outside of the allowed register region.
  247. */
  248. int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val)
  249. {
  250. if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2))
  251. return -EINVAL;
  252. *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
  253. return 0;
  254. }
  255. EXPORT_SYMBOL_GPL(intel_msic_irq_read);
  256. static int intel_msic_init_devices(struct intel_msic *msic)
  257. {
  258. struct platform_device *pdev = msic->pdev;
  259. struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
  260. int ret, i;
  261. if (pdata->gpio) {
  262. struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];
  263. cell->platform_data = pdata->gpio;
  264. cell->pdata_size = sizeof(*pdata->gpio);
  265. }
  266. if (pdata->ocd) {
  267. unsigned gpio = pdata->ocd->gpio;
  268. ret = devm_gpio_request_one(&pdev->dev, gpio,
  269. GPIOF_IN, "ocd_gpio");
  270. if (ret) {
  271. dev_err(&pdev->dev, "failed to register OCD GPIO\n");
  272. return ret;
  273. }
  274. ret = gpio_to_irq(gpio);
  275. if (ret < 0) {
  276. dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
  277. return ret;
  278. }
  279. /* Update the IRQ number for the OCD */
  280. pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
  281. }
  282. for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
  283. if (!pdata->irq[i])
  284. continue;
  285. ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
  286. pdata->irq[i], NULL);
  287. if (ret)
  288. goto fail;
  289. }
  290. ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
  291. ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
  292. if (ret)
  293. goto fail;
  294. return 0;
  295. fail:
  296. mfd_remove_devices(&pdev->dev);
  297. return ret;
  298. }
  299. static void intel_msic_remove_devices(struct intel_msic *msic)
  300. {
  301. struct platform_device *pdev = msic->pdev;
  302. mfd_remove_devices(&pdev->dev);
  303. }
  304. static int intel_msic_probe(struct platform_device *pdev)
  305. {
  306. struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
  307. struct intel_msic *msic;
  308. struct resource *res;
  309. u8 id0, id1;
  310. int ret;
  311. if (!pdata) {
  312. dev_err(&pdev->dev, "no platform data passed\n");
  313. return -EINVAL;
  314. }
  315. /* First validate that we have an MSIC in place */
  316. ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
  317. if (ret) {
  318. dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
  319. return -ENXIO;
  320. }
  321. ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
  322. if (ret) {
  323. dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
  324. return -ENXIO;
  325. }
  326. if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
  327. dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
  328. return -ENXIO;
  329. }
  330. msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
  331. if (!msic)
  332. return -ENOMEM;
  333. msic->vendor = MSIC_VENDOR(id0);
  334. msic->version = MSIC_VERSION(id0);
  335. msic->pdev = pdev;
  336. /*
  337. * Map in the MSIC interrupt tree area in SRAM. This is exposed to
  338. * the clients via intel_msic_irq_read().
  339. */
  340. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  341. msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
  342. if (IS_ERR(msic->irq_base))
  343. return PTR_ERR(msic->irq_base);
  344. platform_set_drvdata(pdev, msic);
  345. ret = intel_msic_init_devices(msic);
  346. if (ret) {
  347. dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
  348. return ret;
  349. }
  350. dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
  351. MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
  352. msic->vendor);
  353. return 0;
  354. }
  355. static int intel_msic_remove(struct platform_device *pdev)
  356. {
  357. struct intel_msic *msic = platform_get_drvdata(pdev);
  358. intel_msic_remove_devices(msic);
  359. return 0;
  360. }
  361. static struct platform_driver intel_msic_driver = {
  362. .probe = intel_msic_probe,
  363. .remove = intel_msic_remove,
  364. .driver = {
  365. .name = "intel_msic",
  366. },
  367. };
  368. builtin_platform_driver(intel_msic_driver);